Compare commits

..

129 commits

Author SHA1 Message Date
Dzmitry Sankouski
2b7263cccc fixup: pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander
This fixes 4a1528ea3c in 6.1 kernel.
Change remove function signature: return void.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
2023-02-05 21:34:21 +03:00
Dzmitry Sankouski
22da203ef8 arm64: dts: qcom: sagit: add reserved memory nodes and chassis type
This taken from upstream patch, and fixes wifi.
fix adsp size, slpi size, reorganize reserved memory nodes
2022-11-02 20:30:00 +03:00
Jami Kettunen
4f782f4c3f [WIP] arm64: msm8998-oneplus-common: fix node names for reserved mem 2022-10-31 02:05:05 +02:00
Jami Kettunen
d23c7879c3 msm8998-oneplus-common: Drop GPU down to 257 MHz for better stability 2022-10-31 02:03:17 +02:00
Jami Kettunen
ae7254d494 arm64: msm8998_defconfig: Add for 6.1
Based on allnoconfig msm8998.config pmos.config cleanup.config.
2022-10-31 02:03:17 +02:00
Jami Kettunen
38feeb3074 arm64: oneplus5_defconfig: Add for 6.1
Based on allnoconfig msm8998.config oneplus5.config pmos.config cleanup.config.
2022-10-31 02:03:17 +02:00
Dzmitry Sankouski
a8eef75016 arm64: dts: qcom: sagit: add initial device tree for sagit
New device support - Xiaomi Mi6 phone

Signed-off-by: Degdag Mohamed <degdagmohamed@gmail.com>
2022-10-31 02:03:17 +02:00
Konrad Dybcio
9479a999eb arm64: dts: qcom: msm8998*: Keep MMCC & MMSS_SMMU enabled by default
MMCC is a component of the SoC that should always be configured. It was kept
off due to misconfiguration on clamshell machines. Keep it disabled on these
ones and enable it by default on all the others.

Exactly the same story applies to MMSS_SMMU, which directly depends on MMCC.

Do note, that if a platform doesn't use neither EFIFB (only applies to WoA
devices in this case) or simplefb (applies to precisely 2 msm8998 devices
as of this commit), this will not cause any harm.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
2022-10-31 02:03:17 +02:00
Konrad Dybcio
7b4df030bf arm64: dts: qcom: msm8998-yoshino: Fix up SMD regulators formatting
Add a new line between each subnode and make the { } consistent.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
2022-10-31 02:03:17 +02:00
Jami Kettunen
48f3cc5f01 arm64: dts: msm8998-oneplus-common: enable SMB2 2022-10-31 02:03:17 +02:00
Jami Kettunen
a106139665 arm64: dts: qcom: msm8998-oneplus-common: enable RRADC 2022-10-31 02:03:17 +02:00
Jami Kettunen
007c711d46 arm64: dts: qcom: msm8998-oneplus-common: add simple-battery 2022-10-31 02:03:14 +02:00
Jami Kettunen
31fcc8d96d arm64: dts: qcom: msm8998-oneplus-common: Add fuel gauge
The OnePlus 5/5T feature a BQ27411 fuel gauge for reading the battery
stats.
2022-10-31 02:03:11 +02:00
Jami Kettunen
fa3def2129 [TEMP] oneplus5: disable all speaker amp stuff
We don't want to blow this up while messing around with audio stuff
early on...
2022-10-31 02:03:11 +02:00
Jami Kettunen
f2922a7943 arm64: dts: msm8998-oneplus-common: Add TFA9890 speaker amp bindings 2022-10-31 02:03:11 +02:00
Jami Kettunen
43f9c1b6df msm8998-oneplus-common: Configure Adreno 540 GPU 2022-10-31 02:03:07 +02:00
Jami Kettunen
705df38a9e arm64: dts: msm8998-oneplus-*: Configure S6E3FA5 & S6E3FC1 panels
These Samsung DSI panels are used on the OnePlus 5/5T respectively.
Additionally disable simplefb until a proper handoff solution can be
found to avoid conflicts between it and the MSM DRM driver.
2022-10-31 02:03:05 +02:00
Jami Kettunen
324c137044 msm8998-oneplus-common: Configure IPA for cellular data 2022-10-31 02:03:05 +02:00
Jami Kettunen
fbfe0bb714 msm8998-oneplus-common: Configure CPUfreq scaling hardware 2022-10-31 02:03:05 +02:00
Jami Kettunen
5c0b2f4545 arm64: dts: msm8998-oneplus-cheeseburger: Configure RMI4 F1A buttons
This allows the capacitive buttons below the touchscreen to be used on
e.g. Android normally :)
2022-10-31 02:03:04 +02:00
Jami Kettunen
3e22a6e8a3 msm8998-oneplus-common: Add remoteproc configuration & enable WLAN 2022-10-31 02:03:02 +02:00
Jami Kettunen
ab047e6597 [DROPME?] msm8998-oneplus-common: Configure blsp1_i2c5_sleep (TS) as no-pull 2022-10-31 02:03:02 +02:00
Jami Kettunen
53da3375c4 dt-bindings: display: panel: Document Samsung S6E3FC1 display panel 2022-10-31 02:02:59 +02:00
Jami Kettunen
246f4d6148 drm/panel: Add panel driver for Samsung S6E3FC1
The S6E3FC1 is 6" 1080x2160 MIPI DSI command mode AMOLED LCD display
found on OnePlus 5T (2017) smartphones.

The panel needs to be enabled from a device tree using the
"samsung,s6e3fc1" compatible.

This driver was generated using the following & includes some minor
cleanup (such as s/to_s6e3fc1/to_s6e3fc1_panel/g):
$ python3 lmdpdg.py dumpling.dtb -r vddio
2022-10-31 02:02:59 +02:00
Jami Kettunen
8b90216819 drm/panel: samsung-s6e3fa5: Implement .get_orientation callback
Other drivers supporting this were already changed as a part of the
following series: https://patchwork.freedesktop.org/series/104807/
2022-10-31 02:02:55 +02:00
Jami Kettunen
7cca9eb36d [SQUASHME?] drm/panel: s6e3fa5: Read panel orientation
The panel is mounted upside down on the OnePlus 5, so we need to handle
this in the driver.
2022-10-31 02:02:41 +02:00
Jami Kettunen
3ea414062d dt-bindings: display: panel: Document Samsung S6E3FA5 display panel 2022-10-31 02:02:37 +02:00
Jami Kettunen
73e0c82858 drm/panel: Add panel driver for Samsung S6E3FA5
The S6E3FA5 is 5.5" 1080x1920 MIPI DSI command mode AMOLED LCD display
found on OnePlus 5 (2017) smartphones.

The panel needs to be enabled from a device tree using the
"samsung,s6e3fa5" compatible.

This driver was generated using the following & includes some minor
cleanup (such as s/to_s6e3fa5/to_s6e3fa5_panel/g):
$ python3 lmdpdg.py cheeseburger.dtb -r vddio

Signed-off-by: Jami Kettunen <jami.kettunen@protonmail.com>
2022-10-31 02:02:37 +02:00
Jami Kettunen
39cd6b976d arm64: dts: qcom: msm8998-oneplus-common: Enable PMI8998 LPG leds
Now the RGB notification LEDs can each be controlled individually :)
2022-10-31 02:02:34 +02:00
Jami Kettunen
b408f19a4f arm64: dts: qcom: msm8998-oneplus-common: Enable PMI8998 haptics
The OnePlus 5 and 5T both have a haptics engine connected to PMI8998.

Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org>
Signed-off-by: Caleb Connolly <caleb@connolly.tech>
2022-10-31 02:02:34 +02:00
Jami Kettunen
35d1ed29cc [ANNOTATION] Apply some F(x)tec Pro1 patches 2022-10-31 02:02:34 +02:00
Danct12
158d9831bf arm64: dts: msm8998-fxtec-pro1: Add remoteproc configuration 2022-10-31 02:02:34 +02:00
Danct12
8535dcd7c2 arm64: dts: msm8998-fxtec-pro1: Enable PMI8998 haptics 2022-10-31 02:02:33 +02:00
Danct12
fdd5838e2b arm64: dts: msm8998-fxtec-pro1: Configure PMI8998 fuel gauge
This will account for battery statistics reporting on the Fxtec Pro1 (QX1000)
2022-10-31 02:02:33 +02:00
Jami Kettunen
b5da4afe50 pinctrl: Fix compilation of Awinic AW9523/B I2C GPIO Expander
Fixes the following link-time error:

    LD      .tmp_vmlinux.kallsyms1
  aarch64-linux-gnu-ld: Unexpected GOT/PLT entries detected!
  aarch64-linux-gnu-ld: Unexpected run-time procedure linkages detected!
  aarch64-linux-gnu-ld: drivers/pinctrl/pinctrl-aw9523.o: in function `aw9523_probe':
  .../drivers/pinctrl/pinctrl-aw9523.c:1004: undefined reference to `__devm_regmap_init_i2c'
  make[1]: *** [.../Makefile:1155: vmlinux] Error 1

Fixes: 96e86abbb4 ("pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander")
2022-10-31 02:02:33 +02:00
Jami Kettunen
bca8458787 [HACK] pinctrl: aw9523: Add workaround for F(x)tec Pro1 keyboard
This is a hack because the correct interrupt type(s) should should be
defined in msm8998-fxtec-pro1.dts instead of the driver.

(originally from Danct12)

This is a workaround for keyboard not working on Fxtec Pro1.

  genirq: Setting trigger mode 12 for irq 123 failed (aw9523_gpio_irq_type+0x0/0x20)
  gpio-fastmatrix-keyboard gpio-keyboard: Cannot get IRQ for gpio302
2022-10-31 02:02:33 +02:00
Jami Kettunen
c974cc82e4 [ANNOTATION] Apply miscellaneous hacks and patches 2022-10-31 02:02:33 +02:00
Jami Kettunen
37d1583665 [HACK] drm/msm: Always report CTL status as started for MSM8998
This register always appears to read 0 on <SDM845 generations so simply
ignore it to avoid refreshing at ~3 Hz as seen on OnePlus 5 with a
command-mode panel with the following spammed in dmesg every time the
screen refreshes:

  [drm:_dpu_encoder_phys_cmd_wait_for_ctl_start:660] [dpu error]enc31 intf1 ctl start interrupt wait failed
  [drm:dpu_kms_wait_for_commit_done:525] [dpu error]wait for commit done returned -22
  ...
2022-10-31 02:02:33 +02:00
Jami Kettunen
5cdf191d57 module: demote invalid ELF header magic error message to pr_debug
This happens anytime busybox modprobe loads a compressed module and
looks especially ugly on postmarketOS for example (or basically any
initramfs); this error is rather pointless since the module is loaded
anyway afterwards.

Upstream (busybox) has no plans to do anything about this error getting
spammed:
https://www.mail-archive.com/busybox@busybox.net/msg27078.html
2022-10-31 02:02:33 +02:00
Jami Kettunen
b7e8630c76 Input: synaptics-rmi4 - add support for F1A
RMI4 F1A supports the simple capacitive buttons function, it's used for
example on embedded devices such as smartphones for capacitive Android
back and recents buttons.
2022-10-31 02:02:30 +02:00
Jami Kettunen
37df9e8b9c arm64: dts: qcom: msm8998: add IPA information
Add support for the MSM8998 SoC, which includes IPA version 3.1.
2022-10-31 02:02:30 +02:00
Jami Kettunen
f639e1729f [HACK] net: ipa: Disable automatic suspend
1aac309d32 ("net: ipa: use autosuspend") currently causes my device to
enter 900E crashdump mode as soon as IPA is probed :/

With this we at least can run ModemManager once again...
2022-10-31 02:02:30 +02:00
Jami Kettunen
019ec6d0a5 [HACK] ath10k: Fake MSA ready event after event server arrival
This finally allowed me to get past the 2 ath10k_info()'s in qmi.c!

However, this doesn't fix everything; it seems you *have* to run
diag-router from https://github.com/andersson/diag to calm the firmware
down and stop constantly crashing; need to look into a way to get Wi-Fi
working later without needing this debug crap to be running.

This should possible be submitted as a quirk to the ath10k driver as
modem on mainline 8998 should be running now as well...
2022-10-31 02:02:25 +02:00
Jami Kettunen
46f0bbbca4 drm/msm: add missing a540 MODULE_FIRMWARE declarations 2022-10-31 02:02:19 +02:00
Jami Kettunen
4d927cb2d9 drm/msm: Mention DSI 10nm PHY support for MSM8998 2022-10-31 02:02:15 +02:00
Jami Kettunen
72ffd69b45 [HACK] scripts: Stop appending "+" to localversion
This always gets added and doesn't look nice in the version string, so
it's purely for aesthetic reasons :p
2022-10-31 02:02:15 +02:00
Caleb Connolly
dae71dc9a5 arm64: dts: qcom: pmi8998: add charger node
Add a node for the smb2 charger hardware found on the pmi8998.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2022-10-31 02:02:14 +02:00
Caleb Connolly
119430dc18 arm64: dts: qcom: pmi8998: add rradc node
Add a DT node for the Round Robin ADC found in the PMI8998 PMIC.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2022-10-31 02:02:14 +02:00
Caleb Connolly
e2c631ebcf arm64: dts: qcom: pmi8998: introduce spmi haptics
Add bindings for Qualcomm SPMI haptics on platforms using pmi8998.

Signed-off-by: Caleb Connolly <caleb@connolly.tech>
(JAMI: fixup for v6.0-rc2 & v7 of driver patches)
2022-10-31 02:02:14 +02:00
Jami Kettunen
4b341bc463 [ANNOTATION] Import WIP "Qualcomm SPMI Fuel Gauge" driver
https://gitlab.com/sdm845-mainline/linux/-/commits/driver/pmi8998_fg/
+ drop pmi8994 DTS changes though.
+ random pieces from https://gitlab.com/sdm845-mainline/linux/-/commits/sdm845/5.19-release :/
2022-10-31 02:02:14 +02:00
Jami Kettunen
1918745f5f power: supply: qcom_fg: Report online property 2022-10-31 02:02:14 +02:00
Yassine Oudjana
f96cfaff29 power: pmi8998_fg: Rename to qcom_fg and add support for PMI8994/6
This adds support for accessing SRAM. That includes requesting and releasing
access to SRAM by setting some registers and handling the mem-avail IRQ,
configuring access, and reading from/writing to it.

Pre-gen3 fuel gauges require reading from SRAM to get voltage, current
and temperature data. Getting capacity is identical to gen3.

Tested on Xiaomi Mi Note 2 with PMI8996.
2022-10-31 02:02:14 +02:00
Yassine Oudjana
cf062a5c35 power: pmi8998_fg: Remove some trailing spaces and tabs
This should be squashed.
2022-10-31 02:02:14 +02:00
Joel Selvaraj
6ab2aa8358 fg: clean and read charge full and max voltage from dts 2022-10-31 02:02:14 +02:00
Joel Selvaraj
e5f8763d74 power: supply: add battery charging status feature 2022-10-31 02:02:14 +02:00
Caleb Connolly
7214b14a7b arm64: dts: qcom: pmi8998: Add fuel gauge
Add a node for qcom,pmi8998-fg.
2022-10-31 02:02:14 +02:00
Joel Selvaraj
f74131008a power: supply: introduce pmi8998 fuel guage driver 2022-10-31 02:02:14 +02:00
Jami Kettunen
aadef46ad8 [ANNOTATION] Import Qualcomm smb2 charger driver v6 (2022-10-09)
Link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20221008183753.249514-1-caleb.connolly@linaro.org/
2022-10-31 02:02:14 +02:00
Caleb Connolly
ea0538d030 dt-bindings: power: supply: qcom,pmi8998-charger: add bindings for smb2 driver
Add devicetree bindings for the Qualcomm PMI8998/PM660 SMB2 charger
driver.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-31 02:02:14 +02:00
Caleb Connolly
15864e39c0 power: supply: add Qualcomm PMI8998 SMB2 Charger driver
Add a driver for the SMB2 charger block found in the Qualcomm PMI8998
and PM660.
This driver adds initial support for detecting USB cables and managing
basic battery charging.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2022-10-31 02:02:14 +02:00
Jami Kettunen
e5788ea5dd [ANNOTATION] Import SPMI haptics driver v7 (2022-10-18)
Link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20221015172915.1436236-1-caleb@connolly.tech/
2022-10-31 02:02:14 +02:00
Caleb Connolly
80b7e7d1a0 input: add Qualcomm SPMI haptics driver
Add support for the haptics found in pmi8998 and related PMICs.
Based on the ff-memless interface. Currently this driver provides
a partial implementation of hardware features.

This driver only supports LRAs (Linear Resonant Actuators) in the "buffer"
mode with a single wave pattern.

Signed-off-by: Caleb Connolly <caleb@connolly.tech>
2022-10-31 02:02:14 +02:00
Caleb Connolly
cd56ff1567 dt-bindings: input: document Qualcomm PMI8998 haptics driver
Add bindings for qcom PMIC PMI8998 haptics driver.

Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-31 02:02:14 +02:00
Jami Kettunen
6a627ac6b7 [ANNOTATION] Base @ angelo/5.14-msm8998-audio-working
I also rebased this tree on the linus/v5.18-rc1 tag and while at it
finally dropped changes irrelevant to msm8998.
2022-10-31 02:02:13 +02:00
AngeloGioacchino Del Regno
b1953b7b81 adreno 5xx: TTBR1 extravaganza on MSM8998
(JAMI: fixup for 5.16)
2022-10-31 02:02:13 +02:00
Jami Kettunen
2c83fb4bc9 arm64: dts: qcom: msm8998-xperia: various tests
Originally from: c215a022
2022-10-31 02:02:13 +02:00
Jami Kettunen
a3e55d753a ASoC: wcd9335: various tests
Originally from: c215a022
2022-10-31 02:02:13 +02:00
AngeloGioacchino Del Regno
8720300aa3 iommu/arm-smmu-qcom: Add MSM8998 and SDM660 mss compatibles for identity
Add MSM8998 and SDM660's mss-pil compatibles to switch the default
iommu domain type to IDENTITY, as similarly required by SDM845 and
others.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for 6.0-rc2)
2022-10-31 02:02:13 +02:00
AngeloGioacchino Del Regno
1d7018b903 iommu/arm-smmu-qcom: Skip the TTBR1 quirk for MSM8998 and SDM630
Similarly to MSM8996 DragonBoard 820c, MSM8998 and SDM630 are equipped
with Adreno 5xx series, which doesn't have separate pagetables support
at the moment of writing.
Skip the TTBR1 quirk for these two SoCs as to get Adreno in a usable
state.
2022-10-31 02:02:13 +02:00
AngeloGioacchino Del Regno
f2e1fd09d4 arm64: dts: qcom: AUDIO WORKS oon MSM8998 Sony Yoshino platform!!! 2022-10-31 02:02:13 +02:00
AngeloGioacchino Del Regno
e0bb18b783 ASoC: codecs: wcd9335: Fix headphone jack commit for new upstream kernel 2022-10-31 02:02:13 +02:00
Srinivas Kandagatla
c97a787623 ASoC: wcd9335: add mbhc support
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2022-10-31 02:02:13 +02:00
Jami Kettunen
6944fd8b93 arm64: dts: qcom: Enable audio on MSM8998 Sony Yoshino platform
Originally from: d95b982a
(JAMI: fixup for 6.0-rc2)
2022-10-31 02:02:13 +02:00
Jami Kettunen
df09ff004c arm64: dts: qcom: msm8998: More audio related node changes
Originally from: d95b982a
2022-10-31 02:02:13 +02:00
Jami Kettunen
88f9d846d6 [DROPME?] fixup! arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU 2022-10-31 02:02:08 +02:00
Jami Kettunen
83b748720a mfd: wcd9335: Add support to wcd9335 codec
Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC.

This codec has integrated SoundWire controller, pin controller and
interrupt controller.

Originally from: d95b982a
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
a92cc30ae8 arm64: dts: qcom: msm8998: Add disabled slimbus support
Add generic slimbus configuration to MSM8998 and keep it disabled.
It is expected that this will be enabled in board-specific device
trees when supported, along with the right audio codec.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
Jami Kettunen
ad7c17af90 ASoC: qcom: lpass-msm8998: Add platform driver for lpass audio
Add platform driver for configuring msm8998 lpass core I2S and
DMA configuration to support playback & capture to external codecs
connected over primary & secondary MI2S interfaces.

(driver originally split from 4d7e1ead3b ("fastmatrix yaml fix"))
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
5be5c146c2 ASoC: qcom: Add MSM8998 sound card support
Add MSM8998 sound support: this driver supports basic functionality
and headphone jack.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for 5.17 & 6.0-rc2)
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
08f802d982 arm64: dts: qcom: msm8998-xperia: Enable lpass smmu
To support audio dsp functionality, enable the lpass smmu.
The firmware distributed with the MSM8998 Sony Xperia smartphones
requires us to skip resetting CB12 of this SMMU and to use CB11
as a context bank to emulate bypass streams.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixed up for v5.16-rc1)
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
b32ea4a02e arm64: dts: qcom: msm8998: Add APR services configuration
Add the standard APR Q6 services configuration for MSM8998, used by
boards supporting the audio dsp.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
327e8d1483 arm64: dts: qcom: msm8998: Define fastrpc ADSP compute context banks
If the target board supports ADSP, it is essential to have fastrpc
compute context banks defined. This commit adds the always usable
unsecured context banks only.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
d5b12139e6 arm64: dts: qcom: msm8998: Add disabled support for lpass iommu for q6
Add support for the LPASS (Q6) SMMU and keep it disabled as this is
used only when the audio DSP is present and used, which is not
mandatory to have.
It is expected for board-specific device-trees to enable this node
if supported.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
f2386073b9 clk: qcom: gcc-msm8998: Add LPASS adsp and core GDSCs
As a final step to entirely enable the required clock tree for the
lpass iommu and audio dsp, add the lpass core/adsp GDSCs.

As a side note, it was found out that disabling the lpass core GDSC
at any time would cause a system lockup (and reboot): disabling
this GDSC will leave the lpass iommu completely unclocked, losing
its state entirely - including the secure contexts that have been
previously set-up from the bootloader/TrustZone.
Losing this IOMMU configuration will trigger a hypervisor fault,
which will reboot the system; the only workaround for this issue
is to declare the lpass core gdsc as always-on.

It should also not be forgotten that this is all about firmware and
there may be a version of it that doesn't enable this GDSC at all
before booting Linux, which is the reason why this specific declaration
wasn't simply omitted.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
03cf81d3a0 dt-bindings: clock: gcc-msm8998: Add LPASS adsp/core GDSCs definitions
Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
190a5aaae0 clk: qcom: gcc-msm8998: Add q6 bimc and lpass core, adsp SMMU clocks
Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related
functionality on MSM8998 and APQ variants. Please note that the Q6 and
the lpass iommu also need GDSCs to be enabled in order to initialize,
which are going to be added in a later commit.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for 6.0-rc2)
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
051c715c75 dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: merge with e122a6a4 for 5.17 & fixup for 6.0-rc1)
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
695a65ac50 arm64: dts: qcom: msm8998: Add imem pil-reloc-info for firmware loading
Firmware loading (mainly the modem) may require IMEM PIL relocation
informations: specify this imem region in dt for qcom_pil_info to
use it.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
0eec71b3b3 arm64: dts: qcom: msm8998: Add qcom,adreno-smmu compatible 2022-10-31 01:55:33 +02:00
Jami Kettunen
4dbc2501ff regulator: qcom-labibb: Always disable interrupts during OCP & SC
Originally from: cd95ecae
2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
2633780796 yoshino: Fix too high overheating backlight, enable all wled strings maple 2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
707f3fc86f drm/msm/dsi_phy_10nm: Fix bad VCO rate calculation 2022-10-31 01:55:33 +02:00
AngeloGioacchino Del Regno
878adc3107 clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks
The pixel and byte clocks rate should not be cached, as a VCO shutdown
may clear the frequency setup and this may not be set again due to the
cached rate being present.
This will also be useful when shadow clocks will be implemented in
the DSI PLL for seamless timing/resolution switch.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
59798e0590 clk: qcom: gcc-msm8998: Set MISC flags, mark hmss/gpu-ahb critical
It is being evaluated whether this commit is really needed.
DONOTUPSTREAM.

(JAMI: fixed up for v5.16-rc1)
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
0dbc76cebe input: keyboard: Add Fast GPIO-driven keyboard/keypad matrix driver
This driver is a reimplementation of matrix_keyboard, on which it
is heavily based: the former was made back in 2009 and then
lightly updated in 2012 to add some support for device-tree / OF.

It turns out that this is not enough, nor OF is fully supported,
as the global (or "clustered") interrupt is never probed, nor it
made usage of the GPIOD API which, nowadays, really simplifies
the job - but not only: it also provides means to set GPIO arrays
for controllers that are supporting this.
The latter is very important when dealing with slow GPIOs such as
I2C and/or SPI expanders (and, again, not only); by using the new
APIs everything fits the new systems, from simplifications of the
probe/remove functions to opening possibility of using expanders
to drive key matrices with or without protection diodes.

But then, why wasn't the old matrix_keyboard driver modified
instead of creating a new one?
The problem there is that the old driver is made to support the
old platform_device style and it's currently still being used by
some PXA boards that are not (yet?) ported to device-tree, so it
would be impossible to modernize it for good, which means that to
support GPIOD (which is - really - required for the aforementioned
reasons) and to fully support DT it would be necessary to wrap the
old GPIO API around the new GPIOD one, creating overhead and also
probably unnecessary memory usage, other than a very big driver
which, at least on embedded devices (having limited resources),
would be simply bad. Leaving the fact that I haven't got any old
board so it's impossible for me to analyze and optimize for them.

Since 98% of the users of the old driver are infact platforms that
have been ported to (or are born with) DT, the introduction of a
new driver that's purely made for them seemed to be the best
choice, also because the expectations are (I think) that all of
the old ARM-based boards will be ported to DT anyway, which will
actually deprecate the good old matrix_keyboard driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
f9a159ad15 dt-bindings: input: Add binding for gpio-fastmatrix-keyboard
Add documentation for the gpio-fastmatrix-keyboard driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: merge with e7aa905a for 5.17)
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
b540916109 dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
3809f25c85 pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander
The Awinic AW9523(B) is a multi-function I2C gpio expander in a
TQFN-24L package, featuring PWM (max 37mA per pin, or total max
power 3.2Watts) for LED driving capability.

It has two ports with 8 pins per port (for a total of 16 pins),
configurable as either PWM with 1/256 stepping or GPIO input/output,
1.8V logic input; each GPIO can be configured as input or output
independently from each other.

This IC also has an internal interrupt controller, which is capable
of generating an interrupt for each GPIO, depending on the
configuration, and will raise an interrupt on the INTN pin to
advertise this to an external interrupt controller.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
Jami Kettunen
90a10c9650 interconnect: msm8998: Ignore return value of icc_provider_del() in .remove()
A similar fix for sm8450 was done in fa80a2994d, fixes compilation on
v6.1-rc1.
2022-10-31 01:55:32 +02:00
Caleb Connolly
b76ed0ff8e interconnect: qcom: msm8998: fix a typo'd QNODE
Fixes a WARN generated by referencing the same node id multiple times
2022-10-31 01:55:32 +02:00
Konrad Dybcio
0b2c00208c interconnect: qcom: Add MSM8998 interconnect provider driver
Introduce a driver for the Qualcomm interconnect busses found in
the MSM/APQ8998 SoCs.
The topology consists of several NoCs that are controlled by a
remote processor that collects the aggregated bandwidth for each
master-slave pairs.

On a note, these chips are managing the "bus QoS" in a "hybrid"
fashion: some of the paths in the topology are managed through
and by, of course) the RPM uC, while some others are "AP Owned",
meaning that the AP shall do direct writes to the appropriate
QoS registers for the specific paths and ports, instead of sending
an indication to the RPM and leaving the job to that one.

Co-authored-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for 5.17)
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
0b98021c39 dt-bindings: interconnect: Add bindings for Qualcomm MSM8998 NoC
Add the bindings for the Qualcomm MSM8998 NoC interconnects.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
e3dd005322 dt-bindings: i2c: qcom,i2c-qup: Document noise rejection properties
Document the new noise rejection properties "qcom,noise-reject-sda"
and "qcom,noise-reject-scl".

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
0615adf07d i2c: qup: Introduce SCL/SDA noise rejection
Some I2C devices may be glitchy due to electrical noise coming
from the device itself or because of possible board design issues.
To overcome this issue, the QUP's I2C in Qualcomm SoCs supports
a noise rejection setting for both SCL and SDA lines.

Introduce a setting for noise rejection through device properties,
"qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will
be used to set the level of noise rejection sensitivity.
If the properties are not specified, noise rejection will not be
enabled.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
da725ffc9e arm64: dts: msm8998: Add SAW, CPRh and CPUFREQ to enable CPU scaling
Add the SAW (SPM), CPR-Hardened, CPUFREQ-HW nodes and relative OPP
tables (and also assign them to the CPU nodes, as required) in order
to enable CPU scaling on the MSM8998 SoC.

The CPR-Hardened and CPUFREQ-HW nodes are disabled by default as to
not change the previous default behavior. Since the drivers are not
yet accounting for speed-binning, these OPPs are referred to the
most common binning for this chip, which I have found on six phones
from Sony and one from FxTec (silver bin0, perf bin2).

At least until speed-binning gets done in the cpufreq-hw and CPR
drivers, users should enable CPR-Hardened and CPUFREQ in their own
board DT.
This is done like that because these drivers are really big, so the
idea is to keep the "base" version easier (but perfectly working),
before adding speed-binning "complications", which may... or may not
be necessary.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Fixed up for 5.18 & 6.0-rc2 by Jami]
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
75b6187a2b arm64: dts: msm8998: Wire up interconnects to MDP and GPU
Wire up the interconnects to both the MDP and the Adreno GPU in
order to get the right balance between performance and power
consumption of both devices.
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
4f3aac8982 arm64: dts: qcom: Enable panel etc. on MSM8998 F(x)tec Pro1 QX1000
(JAMI: fixup for 5.16 & 6.0-rc2)
2022-10-31 01:55:32 +02:00
Konrad Dybcio
5633d34633 arm64: dts: qcom: pm8998: Add VREF_1P25 and REF_GND VADC channels
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
2022-10-31 01:55:32 +02:00
AngeloGioacchino Del Regno
62b32a6973 arm64: dts: msm8998: Wire up interconnects and OPPs to sdhci port 2
Wire up the OPP table and interconnects to the SDHCI port 2 to
improve performance and power consumption.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
ad14529669 arm64: dts: msm8998: Add interconnect nodes
This SoC features Network-on-Chip (NoC) and Bus Integrated Memory
Controller (BIMC) interconnects: add the required nodes now that
the driver is present.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
7c3825a968 arm64: dts: msm8998: Add disabled configuration for DPU1/DSI
This SoC supports both the MDP5 and DPU1 drivers, but the
latter was chosen as it's more feature-complete;

Configure the DPU1, DSI and related phy and pll in order to
achieve display functionality and keep it disabled.
Enabling it will be done on board specific DT when needed,
as not all boards have a usable display attached to them.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
c48720e33d arm64: dts: qcom: Enable panel etc. on MSM8998 Sony Yoshino platform
(JAMI: fixup for 5.16 & 6.0-rc2)
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
d9a01e884d dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
Add the bindings for the CPR3 driver to the documentation.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Rob Herring <robh@kernel.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
8d333acb7b MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
9b789ad11d soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened
This commit introduces a new driver, based on the one for cpr v1,
to enable support for the newer Qualcomm Core Power Reduction
hardware, known downstream as CPR3, CPR4 and CPRh, and support
for MSM8998 and SDM630 CPU power reduction.

In these new versions of the hardware, support for various new
features was introduced, including voltage reduction for the GPU,
security hardening and a new way of controlling CPU DVFS,
consisting in internal communication between microcontrollers,
specifically the CPR-Hardened and the Operating State Manager.

The CPR v3, v4 and CPRh are present in a broad range of SoCs,
from the mid-range to the high end ones including, but not limited
to, MSM8953/8996/8998, SDM630/636/660/845.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
b56256fdb4 arm64: qcom: qcs404: Change CPR nvmem-names
The CPR driver's common functions were split and put in another
file in order to support newer CPR revisions: to simplify the
commonization, the expected names of the fuses had to be changed
in order for both new and old support to use the same fuse name
retrieval function and keeping the naming consistent.

The thread id was added to the fuse name and, since CPRv1 does
not support threads, it is expected to always read ID 0, which
means that the expected name here is now "cpr0_(fuse_name)"
instead of "cpr_(fuse_name)": luckily, QCS404 is the only user
so change it accordingly.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
b50e0add79 soc: qcom: cpr: Move common functions to new file
In preparation for implementing a new driver that will be handling
CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new
file.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

(JAMI: fixup for 5.15 & 5.17)
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
85a644a841 dt-bindings: cpufreq: qcom-hw: Make reg-names a required property
The property reg-names is required after the addition of the OSM
programming sequence, as that mandates specifying different register
domains; to avoid confusion and improve devicetree readability,
specifying the regions names was made mandatory.
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
c53501d155 dt-bindings: cpufreq: qcom-hw: Add bindings for 8998
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Fixed up for 5.18 by Jami]
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
b1305a65ab cpufreq: qcom-hw: Allow getting the maximum transition latency for OPPs
In order to fine-tune the frequency scaling from various governors,
allow to set a maximum transition latency from OPPs, which may be
different depending on the SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Fixup for 5.18 by Jami]
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
1c85136168 cpufreq: qcom-hw: Implement CPRh aware OSM programming
On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is
being programmed in the bootloader and write-protected by the
hypervisor, leaving to the OS read-only access to some of its
registers (in order to read the Lookup Tables and also some
status registers) and write access to the p-state register, for
for the OS to request a specific performance state to trigger a
DVFS switch on the CPU through the OSM hardware.

On old SoCs though (MSM8998, SDM630/660 and variants), the
bootloader will *not* initialize the OSM (and the CPRh, as it
is a requirement for it) before booting the OS, making any
request to trigger a performance state change ineffective, as
the hardware doesn't have any Lookup Table, nor is storing any
parameter to trigger a DVFS switch. In this case, basically all
of the OSM registers are *not* write protected for the OS, even
though some are - but write access is granted through SCM calls.

This commit introduces support for OSM programming, which has to
be done on these old SoCs that were distributed (almost?) always
with a bootloader that does not do any CPRh nor OSM init before
booting the kernel.
In order to program the OSM on these SoCs, it is necessary to
fullfill a "special" requirement: the Core Power Reduction
Hardened (CPRh) hardware block must be initialized, as the OSM
is "talking" to it in order to perform the Voltage part of DVFS;
here, we are calling initialization of this through Linux generic
power domains, specifically by requesting a genpd attach from the
qcom-cpufreq-hw driver, which will give back voltages associated
to each CPU frequency that has been declared in the OPPs, scaled
and interpolated with the previous one, and will also give us
parameters for the Array Power Mux (APM) and mem-acc, in order
for this driver to be then able to generate the Lookup Tables
that will be finally programmed to the OSM hardware.

After writing the parameters to the OSM and enabling it, all the
programming work will never happen anymore until a OS reboot, so
all of the allocations and "the rest" will be disposed-of: this
is done mainly to leave the code that was referred only to the
new SoCs intact, as to also emphasize on the fact that the OSM
HW is, in the end, the exact same; apart some register offsets
that are slightly different, the entire logic is the same.

This also adds the parameters to support CPU scaling on SDM630
and MSM8998.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Fixup for 5.18 & 6.0-rc1 by Jami]
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
67e553ce4b cpufreq: qcom-hw: Add kerneldoc to some functions
Some functions may not be very straightforward to understand:
add kerneldoc to some ones in order to improve readability.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
Manivannan Sadhasivam
00f981b1fa dt-bindings: arm: cpus: Document 'qcom,freq-domain' property
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
2970b7e726 cpufreq: Add MSM8998 to cpufreq-dt-platdev blocklist
Add the MSM8998 to the blocklist since the CPU scaling is handled
out of this.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:31 +02:00
AngeloGioacchino Del Regno
1cfedf9384 iommu/arm-smmu-qcom: Don't modify sACR on hypervisor secured iommus
Avoid modifying the contents of the secure Auxiliary Control Register
on some Qualcomm SoCs: due to a hypervisor configuration on some
firmware versions, this would result in a system crash.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:30 +02:00
AngeloGioacchino Del Regno
fb0b12c66d iommu/arm-smmu-qcom: Avoid disabling secured context banks
Some Qualcomm SoCs' TZ/hypervisor configuration is disallowing the
disablement of some context banks, being them used for tzapps and/or
remote processors; any attempt to disable such CBs will result in
triggering a fault and the system will freeze and/or reset.

For this reason, get a list of context banks that should never get
disabled during smmu initialization through a DT array property
`qcom,reset-nodisable-cbs`.
It was chosen to not hardcode the CBs as this is dependant on the
SoC's firmware, which may vary on different boards.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for v6.0-rc1)
2022-10-31 01:55:30 +02:00
AngeloGioacchino Del Regno
047a452f3f iommu/arm-smmu: Allow skipping context bank disable at reset time
On some SoCs some IOMMU context banks are actively used from TZ
during system boot, or some hypervisor configurations will trigger
a system reset upon disabling some protected/secured CBs.

Allow skipping the disablement of such contexts at IOMMU reset time
during initialization with a new implementation detail to work around
this quirk.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
2022-10-31 01:55:30 +02:00
AngeloGioacchino Del Regno
1a7ce19c97 iommu/arm-smmu-qcom: Allow choosing a custom bypass emulation context
It cannot be taken for granted that the last IOMMU context is free
and available for us to use it to emulate bypass streams and, at least
on MSM8998's lpass iommu, using the last one will produce a crash;
please note that this may not be only dependant on the SoC, but also
on the firmware version.

To overcome to this issue, allow specifying a different context for
bypass emulation with the optional DT property "qcom,bypass-cbndx":
if this property is not found this means that we are either booting
with ACPI instead or that we don't want to specify a custom cb because
the default one (the last context bank) is fine.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
(JAMI: fixup for v6.0-rc1)
2022-10-31 01:55:30 +02:00
Marijn Suijten
2f64669614 leds: ledtrig-pattern: Use last_repeat when applying hw pattern
`last_repeat` holds the actual value requested by the user whereas
`repeat` is a software iteration variable that is unused in hardware
patterns.

Furthermore `last_repeat` is the field returned to the user when reading
the `repeat` sysfs property.  This field is initialized to `-1` which is
- together with `1` - the only valid value in the upcoming Qualcomm LPG
driver.  It is thus unexpected when `repeat` with an initialization
value of `0` is passed into the the driver, when the sysfs property
clearly presents a value of `-1`.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
2022-10-31 01:55:30 +02:00
1489 changed files with 43175 additions and 50869 deletions

View file

@ -535,7 +535,6 @@ ForEachMacros:
- 'perf_hpp_list__for_each_sort_list_safe'
- 'perf_pmu__for_each_hybrid_pmu'
- 'ping_portaddr_for_each_entry'
- 'ping_portaddr_for_each_entry_rcu'
- 'plist_for_each'
- 'plist_for_each_continue'
- 'plist_for_each_entry'

View file

@ -29,7 +29,6 @@ Alexandre Belloni <alexandre.belloni@bootlin.com> <alexandre.belloni@free-electr
Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
Alex Hung <alexhung@gmail.com> <alex.hung@canonical.com>
Alex Shi <alexs@kernel.org> <alex.shi@intel.com>
Alex Shi <alexs@kernel.org> <alex.shi@linaro.org>
Alex Shi <alexs@kernel.org> <alex.shi@linux.alibaba.com>
@ -287,7 +286,6 @@ Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>
Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>
Matthias Fuchs <socketcan@esd.eu> <matthias.fuchs@esd.eu>
Matthieu CASTET <castet.matthieu@free.fr>
Matti Vaittinen <mazziesaccount@gmail.com> <matti.vaittinen@fi.rohmeurope.com>
Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
@ -373,8 +371,6 @@ Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev> <guro@fb.com>
Roman Gushchin <roman.gushchin@linux.dev> <guroan@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev> <klamm@yandex-team.ru>
Muchun Song <muchun.song@linux.dev> <songmuchun@bytedance.com>
Muchun Song <muchun.song@linux.dev> <smuchun@gmail.com>
Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
Rudolf Marek <R.Marek@sh.cvut.cz>
Rui Saraiva <rmps@joel.ist.utl.pt>
@ -386,7 +382,6 @@ Santosh Shilimkar <santosh.shilimkar@oracle.org>
Santosh Shilimkar <ssantosh@kernel.org>
Sarangdhar Joshi <spjoshi@codeaurora.org>
Sascha Hauer <s.hauer@pengutronix.de>
Satya Priya <quic_c_skakit@quicinc.com> <skakit@codeaurora.org>
S.Çağlar Onur <caglar@pardus.org.tr>
Sean Christopherson <seanjc@google.com> <sean.j.christopherson@intel.com>
Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
@ -394,7 +389,6 @@ Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>
Sebastian Reichel <sre@kernel.org> <sre@debian.org>
Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de>
Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com>
Shannon Nelson <shannon.nelson@amd.com> <snelson@pensando.io>
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
@ -422,7 +416,6 @@ TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com>
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Uwe Kleine-König <ukleinek@strlen.de>

View file

@ -918,11 +918,6 @@ S: Ottawa, Ontario
S: K1N 6Z9
S: CANADA
N: Vivien Didelot
E: vivien.didelot@gmail.com
D: DSA framework and MV88E6XXX driver
S: Montreal, Quebec, Canada
N: Jeff Dike
E: jdike@karaya.com
W: http://user-mode-linux.sourceforge.net
@ -2452,10 +2447,6 @@ S: 482 Shadowgraph Dr.
S: San Jose, CA 95110
S: USA
N: Michal Marek
E: michal.lkml@markovi.net
D: Kbuild Maintainer 2009-2017
N: Martin Mares
E: mj@ucw.cz
W: http://www.ucw.cz/~mj/

View file

@ -6959,14 +6959,3 @@
memory, and other data can't be written using
xmon commands.
off xmon is disabled.
amd_pstate= [X86]
disable
Do not enable amd_pstate as the default
scaling driver for the supported processors
passive
Use amd_pstate as a scaling driver, driver requests a
desired performance on this abstract scale and the power
management firmware translates the requests into actual
hardware states (core frequency, data fabric and memory
clocks etc.)

View file

@ -283,19 +283,23 @@ efficiency frequency management method on AMD processors.
Kernel Module Options for ``amd-pstate``
=========================================
Passive Mode
------------
.. _shared_mem:
``amd_pstate=passive``
``shared_mem``
Use a module param (shared_mem) to enable related processors manually with
**amd_pstate.shared_mem=1**.
Due to the performance issue on the processors with `Shared Memory Support
<perf_cap_>`_, we disable it presently and will re-enable this by default
once we address performance issue with this solution.
It will be enabled if the ``amd_pstate=passive`` is passed to the kernel in the command line.
In this mode, ``amd_pstate`` driver software specifies a desired QoS target in the CPPC
performance scale as a relative number. This can be expressed as percentage of nominal
performance (infrastructure max). Below the nominal sustained performance level,
desired performance expresses the average performance level of the processor subject
to the Performance Reduction Tolerance register. Above the nominal performance level,
processor must provide at least nominal performance requested and go higher if current
operating conditions allow.
To check whether the current processor is using `Full MSR Support <perf_cap_>`_
or `Shared Memory Support <perf_cap_>`_ : ::
ray@hr-test1:~$ lscpu | grep cppc
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
If the CPU flags have ``cppc``, then this processor supports `Full MSR Support
<perf_cap_>`_. Otherwise, it supports `Shared Memory Support <perf_cap_>`_.
``cpupower`` tool support for ``amd-pstate``

View file

@ -340,14 +340,6 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
- HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
- HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
- HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
- HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)
- If EL3 is present:

View file

@ -92,7 +92,7 @@ operation if the source belongs to the supported system register space.
The infrastructure emulates only the following system register space::
Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
(See Table C5-6 'System instruction encodings for non-Debug System
register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
@ -293,42 +293,6 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| FPDP | [11-8] | y |
+------------------------------+---------+---------+
11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| SIMDFMAC | [31-28] | y |
+------------------------------+---------+---------+
| SIMDSP | [19-16] | y |
+------------------------------+---------+---------+
| SIMDInt | [15-12] | y |
+------------------------------+---------+---------+
| SIMDLS | [11-8] | y |
+------------------------------+---------+---------+
12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| CRC32 | [19-16] | y |
+------------------------------+---------+---------+
| SHA2 | [15-12] | y |
+------------------------------+---------+---------+
| SHA1 | [11-8] | y |
+------------------------------+---------+---------+
| AES | [7-4] | y |
+------------------------------+---------+---------+
Appendix I: Example
-------------------

View file

@ -67,7 +67,6 @@ uninitialized in the local variable, as well as the stack where the value was
copied to another memory location before use.
A use of uninitialized value ``v`` is reported by KMSAN in the following cases:
- in a condition, e.g. ``if (v) { ... }``;
- in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``;
- when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``;

View file

@ -148,7 +148,7 @@ allOf:
items:
- const: oscclk
- const: dout_clkcmu_fsys1_bus
- const: gout_clkcmu_fsys1_mmc_card
- const: dout_clkcmu_fsys1_mmc_card
- const: dout_clkcmu_fsys1_usbdrd
- if:

View file

@ -15,22 +15,9 @@ description:
properties:
compatible:
oneOf:
- enum:
- qcom,sfpb-mutex
- qcom,tcsr-mutex
- items:
- enum:
- qcom,apq8084-tcsr-mutex
- qcom,ipq6018-tcsr-mutex
- qcom,msm8226-tcsr-mutex
- qcom,msm8994-tcsr-mutex
- const: qcom,tcsr-mutex
- items:
- enum:
- qcom,msm8974-tcsr-mutex
- const: qcom,tcsr-mutex
- const: syscon
enum:
- qcom,sfpb-mutex
- qcom,tcsr-mutex
reg:
maxItems: 1
@ -47,9 +34,9 @@ additionalProperties: false
examples:
- |
hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
#hwlock-cells = <1>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
#hwlock-cells = <1>;
};
...

View file

@ -62,6 +62,13 @@ properties:
description:
Inform the driver that last channel will be used to sensor battery.
aspeed,trim-data-valid:
type: boolean
description: |
The ADC reference voltage can be calibrated to obtain the trimming
data which will be stored in otp. This property informs the driver that
the data store in the otp is valid.
required:
- compatible
- reg

View file

@ -16,11 +16,8 @@ description:
properties:
compatible:
oneOf:
items:
- const: goodix,gt7375p
- items:
- const: goodix,gt7986u
- const: goodix,gt7375p
reg:
enum:

View file

@ -24,7 +24,7 @@ properties:
oneOf:
- items:
- enum:
- qcom,sc7280-cpu-bwmon
- qcom,sc7280-bwmon
- qcom,sdm845-bwmon
- const: qcom,msm8998-bwmon
- const: qcom,msm8998-bwmon # BWMON v4

View file

@ -36,9 +36,6 @@ properties:
resets:
maxItems: 1
iommus:
maxItems: 1
required:
- compatible
- reg
@ -46,7 +43,6 @@ required:
- clocks
- clock-names
- resets
- iommus
additionalProperties: false
@ -63,7 +59,6 @@ examples:
clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_VP9>;
iommus = <&iommu 5>;
};
...

View file

@ -47,7 +47,7 @@ properties:
nvmem-cells: true
nvmem-cell-names: true
nvmem-cells-names: true
phy-connection-type:
enum:

View file

@ -81,9 +81,6 @@ properties:
power-supply: true
power-domains:
maxItems: 1
resets:
description: |
A number of phandles to resets that need to be asserted during

View file

@ -8,7 +8,7 @@ title: Audio codec controlled by ChromeOS EC
maintainers:
- Cheng-Yi Chiang <cychiang@chromium.org>
- Tzung-Bi Shih <tzungbi@kernel.org>
- Tzung-Bi Shih <tzungbi@google.com>
description: |
Google's ChromeOS EC codec is a digital mic codec provided by the

View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek rt1015p codec devicetree bindings
maintainers:
- Tzung-Bi Shih <tzungbi@kernel.org>
- Tzung-Bi Shih <tzungbi@google.com>
description: |
Rt1015p is a rt1015 variant which does not support I2C and

View file

@ -279,7 +279,6 @@ GPIO
devm_gpio_request_one()
I2C
devm_i2c_add_adapter()
devm_i2c_new_dummy_device()
IIO

View file

@ -16,10 +16,11 @@ Parallel Port Devices
16x50 UART Driver
=================
.. kernel-doc:: drivers/tty/serial/8250/8250_core.c
.. kernel-doc:: drivers/tty/serial/serial_core.c
:export:
See serial/driver.rst for related APIs.
.. kernel-doc:: drivers/tty/serial/8250/8250_core.c
:export:
Pulse-Width Modulation (PWM)
============================

View file

@ -119,16 +119,6 @@ To avoid this, you can make the vDSO different for different
kernel versions by including an arbitrary string of "salt" in it.
This is specified by the Kconfig symbol ``CONFIG_BUILD_SALT``.
Git
---
Uncommitted changes or different commit ids in git can also lead
to different compilation results. For example, after executing
``git reset HEAD^``, even if the code is the same, the
``include/config/kernel.release`` generated during compilation
will be different, which will eventually lead to binary differences.
See ``scripts/setlocalversion`` for details.
.. _KBUILD_BUILD_TIMESTAMP: kbuild.html#kbuild-build-timestamp
.. _KBUILD_BUILD_USER and KBUILD_BUILD_HOST: kbuild.html#kbuild-build-user-kbuild-build-host
.. _KCFLAGS: kbuild.html#kcflags

View file

@ -120,7 +120,7 @@ You can tell you are in a softirq (or tasklet) using the
.. warning::
Beware that this will return a false positive if a
:ref:`bottom half lock <local_bh_disable>` is held.
:ref:`botton half lock <local_bh_disable>` is held.
Some Basic Rules
================

View file

@ -1,42 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
=======================
Booting Linux/LoongArch
=======================
:Author: Yanteng Si <siyanteng@loongson.cn>
:Date: 18 Nov 2022
Information passed from BootLoader to kernel
============================================
LoongArch supports ACPI and FDT. The information that needs to be passed
to the kernel includes the memmap, the initrd, the command line, optionally
the ACPI/FDT tables, and so on.
The kernel is passed the following arguments on `kernel_entry` :
- a0 = efi_boot: `efi_boot` is a flag indicating whether
this boot environment is fully UEFI-compliant.
- a1 = cmdline: `cmdline` is a pointer to the kernel command line.
- a2 = systemtable: `systemtable` points to the EFI system table.
All pointers involved at this stage are in physical addresses.
Header of Linux/LoongArch kernel images
=======================================
Linux/LoongArch kernel images are EFI images. Being PE files, they have
a 64-byte header structured like::
u32 MZ_MAGIC /* "MZ", MS-DOS header */
u32 res0 = 0 /* Reserved */
u64 kernel_entry /* Kernel entry point */
u64 _end - _text /* Kernel image effective size */
u64 load_offset /* Kernel image load offset from start of RAM */
u64 res1 = 0 /* Reserved */
u64 res2 = 0 /* Reserved */
u64 res3 = 0 /* Reserved */
u32 LINUX_PE_MAGIC /* Magic number */
u32 pe_header - _head /* Offset to the PE header */

View file

@ -9,7 +9,6 @@ LoongArch Architecture
:numbered:
introduction
booting
irq-chip-model
features

View file

@ -6,4 +6,4 @@ Generic Netlink
A wiki document on how to use Generic Netlink can be found here:
* https://wiki.linuxfoundation.org/networking/generic_netlink_howto
* http://www.linuxfoundation.org/collaborate/workgroups/networking/generic_netlink_howto

View file

@ -126,10 +126,17 @@ than one development cycle past their initial release. So, for example, the
5.2.21 was the final stable update of the 5.2 release.
Some kernels are designated "long term" kernels; they will receive support
for a longer period. Please refer to the following link for the list of active
long term kernel versions and their maintainers:
for a longer period. As of this writing, the current long term kernels
and their maintainers are:
https://www.kernel.org/category/releases.html
====== ================================ =======================
3.16 Ben Hutchings (very long-term kernel)
4.4 Greg Kroah-Hartman & Sasha Levin (very long-term kernel)
4.9 Greg Kroah-Hartman & Sasha Levin
4.14 Greg Kroah-Hartman & Sasha Levin
4.19 Greg Kroah-Hartman & Sasha Levin
5.4 Greg Kroah-Hartman & Sasha Levin
====== ================================ =======================
The selection of a kernel for long-term support is purely a matter of a
maintainer having the need and the time to maintain that release. There

View file

@ -51,7 +51,7 @@ the Technical Advisory Board (TAB) or other maintainers if you're
uncertain how to handle situations that come up. It will not be
considered a violation report unless you want it to be. If you are
uncertain about approaching the TAB or any other maintainers, please
reach out to our conflict mediator, Joanna Lee <jlee@linuxfoundation.org>.
reach out to our conflict mediator, Joanna Lee <joanna.lee@gesmer.com>.
In the end, "be kind to each other" is really what the end goal is for
everybody. We know everyone is human and we all fail at times, but the

View file

@ -36,7 +36,7 @@ experience, the following books are good for, if anything, reference:
- "C: A Reference Manual" by Harbison and Steele [Prentice Hall]
The kernel is written using GNU C and the GNU toolchain. While it
adheres to the ISO C11 standard, it uses a number of extensions that are
adheres to the ISO C89 standard, it uses a number of extensions that are
not featured in the standard. The kernel is a freestanding C
environment, with no reliance on the standard C library, so some
portions of the C standard are not supported. Arbitrary long long

View file

@ -39,7 +39,7 @@ Documentation written by Tom Zanussi
will use the event's kernel stacktrace as the key. The keywords
'keys' or 'key' can be used to specify keys, and the keywords
'values', 'vals', or 'val' can be used to specify values. Compound
keys consisting of up to three fields can be specified by the 'keys'
keys consisting of up to two fields can be specified by the 'keys'
keyword. Hashing a compound key produces a unique entry in the
table for each unique combination of component keys, and can be
useful for providing more fine-grained summaries of event data.

View file

@ -44,7 +44,7 @@ altro, utili riferimenti:
- "C: A Reference Manual" di Harbison and Steele [Prentice Hall]
Il kernel è stato scritto usando GNU C e la toolchain GNU.
Sebbene si attenga allo standard ISO C11, esso utilizza una serie di
Sebbene si attenga allo standard ISO C89, esso utilizza una serie di
estensioni che non sono previste in questo standard. Il kernel è un
ambiente C indipendente, che non ha alcuna dipendenza dalle librerie
C standard, così alcune parti del C standard non sono supportate.

View file

@ -65,7 +65,7 @@ Linux カーネル開発のやり方
- 『新・詳説 C 言語 H&S リファレンス』 (サミュエル P ハービソン/ガイ L スティール共著 斉藤 信男監訳)[ソフトバンク]
カーネルは GNU C と GNU ツールチェインを使って書かれています。カーネル
は ISO C11 仕様に準拠して書く一方で、標準には無い言語拡張を多く使って
は ISO C89 仕様に準拠して書く一方で、標準には無い言語拡張を多く使って
います。カーネルは標準 C ライブラリに依存しない、C 言語非依存環境です。
そのため、C の標準の中で使えないものもあります。特に任意の long long
の除算や浮動小数点は使えません。カーネルがツールチェインや C 言語拡張

View file

@ -62,7 +62,7 @@ Documentation/process/howto.rst
- "Practical C Programming" by Steve Oualline [O'Reilly]
- "C: A Reference Manual" by Harbison and Steele [Prentice Hall]
커널은 GNU C와 GNU 툴체인을 사용하여 작성되었다. 이 툴들은 ISO C11 표준을
커널은 GNU C와 GNU 툴체인을 사용하여 작성되었다. 이 툴들은 ISO C89 표준을
따르는 반면 표준에 있지 않은 많은 확장기능도 가지고 있다. 커널은 표준 C
라이브러리와는 관계없이 freestanding C 환경이어서 C 표준의 일부는
지원되지 않는다. 임의의 long long 나누기나 floating point는 지원되지 않는다.

View file

@ -1,48 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0
.. include:: ../disclaimer-zh_CN.rst
:Original: Documentation/loongarch/booting.rst
:翻译:
司延腾 Yanteng Si <siyanteng@loongson.cn>
====================
启动 Linux/LoongArch
====================
:作者: 司延腾 <siyanteng@loongson.cn>
:日期: 2022年11月18日
BootLoader传递给内核的信息
==========================
LoongArch支持ACPI和FDT启动需要传递给内核的信息包括memmap、initrd、cmdline、可
选的ACPI/FDT表等。
内核在 `kernel_entry` 入口处被传递以下参数:
- a0 = efi_boot: `efi_boot` 是一个标志表示这个启动环境是否完全符合UEFI
的要求。
- a1 = cmdline: `cmdline` 是一个指向内核命令行的指针。
- a2 = systemtable: `systemtable` 指向EFI的系统表在这个阶段涉及的所有
指针都是物理地址。
Linux/LoongArch内核镜像文件头
=============================
内核镜像是EFI镜像。作为PE文件它们有一个64字节的头部结构体如下所示::
u32 MZ_MAGIC /* "MZ", MS-DOS 头 */
u32 res0 = 0 /* 保留 */
u64 kernel_entry /* 内核入口点 */
u64 _end - _text /* 内核镜像有效大小 */
u64 load_offset /* 加载内核镜像相对内存起始地址的偏移量 */
u64 res1 = 0 /* 保留 */
u64 res2 = 0 /* 保留 */
u64 res3 = 0 /* 保留 */
u32 LINUX_PE_MAGIC /* 魔术数 */
u32 pe_header - _head /* 到PE头的偏移量 */

View file

@ -14,7 +14,6 @@ LoongArch体系结构
:numbered:
introduction
booting
irq-chip-model
features

View file

@ -70,8 +70,8 @@ LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0而其
================= ================== =================== ==========
.. note::
注意:在一些遗留代码中有时可能见到 ``$fv0````$fv1`` ,它们是
``$fa0````$fa1`` 的别名,属于已经废弃的用法。
注意:在一些遗留代码中有时可能见到 ``$v0````$v1`` ,它们是
``$a0````$a1`` 的别名,属于已经废弃的用法。
向量寄存器

View file

@ -45,7 +45,7 @@ Linux内核大部分是由C语言写成的一些体系结构相关的代码
- "C: A Reference Manual" by Harbison and Steele [Prentice Hall]
《C语言参考手册原书第5版邱仲潘 等译)[机械工业出版社]
Linux内核使用GNU C和GNU工具链开发。虽然它遵循ISO C11标准,但也用到了一些
Linux内核使用GNU C和GNU工具链开发。虽然它遵循ISO C89标准,但也用到了一些
标准中没有定义的扩展。内核是自给自足的C环境不依赖于标准C库的支持所以
并不支持C标准中的部分定义。比如long long类型的大数除法和浮点运算就不允许
使用。有时候确实很难弄清楚内核对工具链的要求和它所使用的扩展,不幸的是目

View file

@ -48,7 +48,7 @@ Linux內核大部分是由C語言寫成的一些體系結構相關的代碼
- "C: A Reference Manual" by Harbison and Steele [Prentice Hall]
《C語言參考手冊原書第5版邱仲潘 等譯)[機械工業出版社]
Linux內核使用GNU C和GNU工具鏈開發。雖然它遵循ISO C11標準,但也用到了一些
Linux內核使用GNU C和GNU工具鏈開發。雖然它遵循ISO C89標準,但也用到了一些
標準中沒有定義的擴展。內核是自給自足的C環境不依賴於標準C庫的支持所以
並不支持C標準中的部分定義。比如long long類型的大數除法和浮點運算就不允許
使用。有時候確實很難弄清楚內核對工具鏈的要求和它所使用的擴展,不幸的是目

View file

@ -7213,13 +7213,14 @@ veto the transition.
:Parameters: args[0] is the maximum poll time in nanoseconds
:Returns: 0 on success; -1 on error
KVM_CAP_HALT_POLL overrides the kvm.halt_poll_ns module parameter to set the
maximum halt-polling time for all vCPUs in the target VM. This capability can
be invoked at any time and any number of times to dynamically change the
maximum halt-polling time.
This capability overrides the kvm module parameter halt_poll_ns for the
target VM.
See Documentation/virt/kvm/halt-polling.rst for more information on halt
polling.
VCPU polling allows a VCPU to poll for wakeup events instead of immediately
scheduling during guest halts. The maximum time a VCPU can spend polling is
controlled by the kvm module parameter halt_poll_ns. This capability allows
the maximum halt time to specified on a per-VM basis, effectively overriding
the module parameter for the target VM.
7.21 KVM_CAP_X86_USER_SPACE_MSR
-------------------------------

View file

@ -215,7 +215,6 @@ KVM_S390_VM_TOD_EXT).
:Parameters: address of a buffer in user space to store the data (u8) to
:Returns: -EFAULT if the given address is not accessible from kernel space;
-EINVAL if setting the TOD clock extension to != 0 is not supported
-EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
3.2. ATTRIBUTE: KVM_S390_VM_TOD_LOW
-----------------------------------
@ -225,7 +224,6 @@ the POP (u64).
:Parameters: address of a buffer in user space to store the data (u64) to
:Returns: -EFAULT if the given address is not accessible from kernel space
-EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
3.3. ATTRIBUTE: KVM_S390_VM_TOD_EXT
-----------------------------------
@ -239,7 +237,6 @@ it, it is stored as 0 and not allowed to be set to a value != 0.
(kvm_s390_vm_tod_clock) to
:Returns: -EFAULT if the given address is not accessible from kernel space;
-EINVAL if setting the TOD clock extension to != 0 is not supported
-EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
4. GROUP: KVM_S390_VM_CRYPTO
============================

View file

@ -17,5 +17,4 @@ KVM
locking
vcpu-requests
halt-polling
review-checklist

View file

@ -119,19 +119,6 @@ These module parameters can be set from the debugfs files in:
Note: that these module parameters are system wide values and are not able to
be tuned on a per vm basis.
Any changes to these parameters will be picked up by new and existing vCPUs the
next time they halt, with the notable exception of VMs using KVM_CAP_HALT_POLL
(see next section).
KVM_CAP_HALT_POLL
=================
KVM_CAP_HALT_POLL is a VM capability that allows userspace to override halt_poll_ns
on a per-VM basis. VMs using KVM_CAP_HALT_POLL ignore halt_poll_ns completely (but
still obey halt_poll_ns_grow, halt_poll_ns_grow_start, and halt_poll_ns_shrink).
See Documentation/virt/kvm/api.rst for more information on this capability.
Further Notes
=============

View file

@ -10,6 +10,7 @@ KVM for x86 systems
amd-memory-encryption
cpuid
errata
halt-polling
hypercalls
mmu
msr

View file

@ -2197,7 +2197,7 @@ M: Wei Xu <xuwei5@hisilicon.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
W: http://www.hisilicon.com
T: git https://github.com/hisilicon/linux-hisi.git
T: git git://github.com/hisilicon/linux-hisi.git
F: arch/arm/boot/dts/hi3*
F: arch/arm/boot/dts/hip*
F: arch/arm/boot/dts/hisi*
@ -3984,7 +3984,7 @@ M: Rafał Miłecki <rafal@milecki.pl>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
F: arch/arm64/boot/dts/broadcom/bcmbca/*
N: bcmbca
@ -4009,7 +4009,7 @@ R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
F: drivers/pci/controller/pcie-brcmstb.c
F: drivers/staging/vc04_services
@ -4023,7 +4023,7 @@ M: Ray Jui <rjui@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
S: Maintained
T: git https://github.com/broadcom/mach-bcm
T: git git://github.com/broadcom/mach-bcm
F: arch/arm/mach-bcm/
N: bcm281*
N: bcm113*
@ -4088,7 +4088,7 @@ M: Florian Fainelli <f.fainelli@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
F: arch/arm/boot/dts/bcm7*.dts*
F: arch/arm/include/asm/hardware/cache-b15-rac.h
@ -4121,7 +4121,7 @@ M: Florian Fainelli <f.fainelli@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-mips@vger.kernel.org
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: arch/mips/bmips/*
F: arch/mips/boot/dts/brcm/bcm*.dts*
F: arch/mips/include/asm/mach-bmips/*
@ -4262,7 +4262,7 @@ M: Scott Branden <sbranden@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: arch/arm64/boot/dts/broadcom/northstar2/*
F: arch/arm64/boot/dts/broadcom/stingray/*
F: drivers/clk/bcm/clk-ns*
@ -4332,7 +4332,7 @@ M: Florian Fainelli <f.fainelli@gmail.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
L: linux-pm@vger.kernel.org
S: Maintained
T: git https://github.com/broadcom/stblinux.git
T: git git://github.com/broadcom/stblinux.git
F: drivers/soc/bcm/bcm63xx/bcm-pmb.c
F: include/dt-bindings/soc/bcm-pmb.h
@ -4809,7 +4809,7 @@ R: Jeff Layton <jlayton@kernel.org>
L: ceph-devel@vger.kernel.org
S: Supported
W: http://ceph.com/
T: git https://github.com/ceph/ceph-client.git
T: git git://github.com/ceph/ceph-client.git
F: include/linux/ceph/
F: include/linux/crush/
F: net/ceph/
@ -4821,7 +4821,7 @@ R: Jeff Layton <jlayton@kernel.org>
L: ceph-devel@vger.kernel.org
S: Supported
W: http://ceph.com/
T: git https://github.com/ceph/ceph-client.git
T: git git://github.com/ceph/ceph-client.git
F: Documentation/filesystems/ceph.rst
F: fs/ceph/
@ -4911,7 +4911,7 @@ F: drivers/platform/chrome/
CHROMEOS EC CODEC DRIVER
M: Cheng-Yi Chiang <cychiang@chromium.org>
M: Tzung-Bi Shih <tzungbi@kernel.org>
M: Tzung-Bi Shih <tzungbi@google.com>
R: Guenter Roeck <groeck@chromium.org>
L: chrome-platform@lists.linux.dev
S: Maintained
@ -5041,7 +5041,7 @@ F: drivers/scsi/snic/
CISCO VIC ETHERNET NIC DRIVER
M: Christian Benvenuti <benve@cisco.com>
M: Satish Kharat <satishkh@cisco.com>
M: Govindarajulu Varadarajan <_govind@gmx.com>
S: Supported
F: drivers/net/ethernet/cisco/enic/
@ -5299,7 +5299,7 @@ M: Johannes Weiner <hannes@cmpxchg.org>
M: Michal Hocko <mhocko@kernel.org>
M: Roman Gushchin <roman.gushchin@linux.dev>
M: Shakeel Butt <shakeelb@google.com>
R: Muchun Song <muchun.song@linux.dev>
R: Muchun Song <songmuchun@bytedance.com>
L: cgroups@vger.kernel.org
L: linux-mm@kvack.org
S: Maintained
@ -5585,6 +5585,8 @@ F: drivers/scsi/cxgbi/cxgb3i
CXGB4 CRYPTO DRIVER (chcr)
M: Ayush Sawal <ayush.sawal@chelsio.com>
M: Vinay Kumar Yadav <vinay.yadav@chelsio.com>
M: Rohit Maheshwari <rohitm@chelsio.com>
L: linux-crypto@vger.kernel.org
S: Supported
W: http://www.chelsio.com
@ -5592,6 +5594,8 @@ F: drivers/crypto/chelsio
CXGB4 INLINE CRYPTO DRIVER
M: Ayush Sawal <ayush.sawal@chelsio.com>
M: Vinay Kumar Yadav <vinay.yadav@chelsio.com>
M: Rohit Maheshwari <rohitm@chelsio.com>
L: netdev@vger.kernel.org
S: Supported
W: http://www.chelsio.com
@ -8598,8 +8602,8 @@ F: include/asm-generic/
F: include/uapi/asm-generic/
GENERIC PHY FRAMEWORK
M: Kishon Vijay Abraham I <kishon@ti.com>
M: Vinod Koul <vkoul@kernel.org>
M: Kishon Vijay Abraham I <kishon@kernel.org>
L: linux-phy@lists.infradead.org
S: Supported
Q: https://patchwork.kernel.org/project/linux-phy/list/
@ -9213,7 +9217,7 @@ W: https://www.hisilicon.com
F: drivers/i2c/busses/i2c-hisi.c
HISILICON LPC BUS DRIVER
M: Jay Fang <f.fangjian@huawei.com>
M: john.garry@huawei.com
S: Maintained
W: http://www.hisilicon.com
F: Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml
@ -9337,7 +9341,7 @@ S: Maintained
F: drivers/crypto/hisilicon/trng/trng.c
HISILICON V3XX SPI NOR FLASH Controller Driver
M: Jay Fang <f.fangjian@huawei.com>
M: John Garry <john.garry@huawei.com>
S: Maintained
W: http://www.hisilicon.com
F: drivers/spi/spi-hisi-sfc-v3xx.c
@ -9439,7 +9443,7 @@ F: drivers/net/ethernet/huawei/hinic/
HUGETLB SUBSYSTEM
M: Mike Kravetz <mike.kravetz@oracle.com>
M: Muchun Song <muchun.song@linux.dev>
M: Muchun Song <songmuchun@bytedance.com>
L: linux-mm@kvack.org
S: Maintained
F: Documentation/ABI/testing/sysfs-kernel-mm-hugepages
@ -9503,6 +9507,7 @@ F: drivers/media/i2c/hi847.c
Hyper-V/Azure CORE AND DRIVERS
M: "K. Y. Srinivasan" <kys@microsoft.com>
M: Haiyang Zhang <haiyangz@microsoft.com>
M: Stephen Hemminger <sthemmin@microsoft.com>
M: Wei Liu <wei.liu@kernel.org>
M: Dexuan Cui <decui@microsoft.com>
L: linux-hyperv@vger.kernel.org
@ -9773,10 +9778,7 @@ S: Supported
F: drivers/pci/hotplug/rpaphp*
IBM Power SRIOV Virtual NIC Device Driver
M: Haren Myneni <haren@linux.ibm.com>
M: Rick Lindsley <ricklind@linux.ibm.com>
R: Nick Child <nnac123@linux.ibm.com>
R: Dany Madden <danymadden@us.ibm.com>
M: Dany Madden <drt@linux.ibm.com>
R: Thomas Falcon <tlfalcon@linux.ibm.com>
L: netdev@vger.kernel.org
S: Supported
@ -10283,7 +10285,7 @@ T: git https://github.com/intel/gvt-linux.git
F: drivers/gpu/drm/i915/gvt/
INTEL HID EVENT DRIVER
M: Alex Hung <alexhung@gmail.com>
M: Alex Hung <alex.hung@canonical.com>
L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/intel/hid.c
@ -11031,7 +11033,6 @@ KCONFIG
M: Masahiro Yamada <masahiroy@kernel.org>
L: linux-kbuild@vger.kernel.org
S: Maintained
Q: https://patchwork.kernel.org/project/linux-kbuild/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kconfig
F: Documentation/kbuild/kconfig*
F: scripts/Kconfig.include
@ -11089,12 +11090,10 @@ F: fs/autofs/
KERNEL BUILD + files below scripts/ (unless maintained elsewhere)
M: Masahiro Yamada <masahiroy@kernel.org>
R: Nathan Chancellor <nathan@kernel.org>
M: Michal Marek <michal.lkml@markovi.net>
R: Nick Desaulniers <ndesaulniers@google.com>
R: Nicolas Schier <nicolas@fjasle.eu>
L: linux-kbuild@vger.kernel.org
S: Maintained
Q: https://patchwork.kernel.org/project/linux-kbuild/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
F: Documentation/kbuild/
F: Makefile
@ -11249,7 +11248,7 @@ L: kvm@vger.kernel.org
L: kvm-riscv@lists.infradead.org
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/kvm-riscv/linux.git
T: git git://github.com/kvm-riscv/linux.git
F: arch/riscv/include/asm/kvm*
F: arch/riscv/include/uapi/asm/kvm*
F: arch/riscv/kvm/
@ -12224,6 +12223,7 @@ F: arch/mips/boot/dts/img/pistachio*
MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
M: Andrew Lunn <andrew@lunn.ch>
M: Vivien Didelot <vivien.didelot@gmail.com>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/marvell.txt
@ -13624,12 +13624,6 @@ S: Supported
F: drivers/misc/atmel-ssc.c
F: include/linux/atmel-ssc.h
MICROCHIP SOC DRIVERS
M: Conor Dooley <conor@kernel.org>
S: Supported
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: drivers/soc/microchip/
MICROCHIP USB251XB DRIVER
M: Richard Leitner <richard.leitner@skidata.com>
L: linux-usb@vger.kernel.org
@ -14327,6 +14321,7 @@ F: drivers/net/wireless/
NETWORKING [DSA]
M: Andrew Lunn <andrew@lunn.ch>
M: Vivien Didelot <vivien.didelot@gmail.com>
M: Florian Fainelli <f.fainelli@gmail.com>
M: Vladimir Oltean <olteanv@gmail.com>
S: Maintained
@ -15635,7 +15630,7 @@ F: drivers/input/serio/gscps2.c
F: drivers/input/serio/hp_sdc*
F: drivers/parisc/
F: drivers/parport/parport_gsc.*
F: drivers/tty/serial/8250/8250_parisc.c
F: drivers/tty/serial/8250/8250_gsc.c
F: drivers/video/console/sti*
F: drivers/video/fbdev/sti*
F: drivers/video/logo/logo_parisc*
@ -15948,7 +15943,6 @@ Q: https://patchwork.kernel.org/project/linux-pci/list/
B: https://bugzilla.kernel.org
C: irc://irc.oftc.net/linux-pci
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
F: Documentation/devicetree/bindings/pci/
F: drivers/pci/controller/
F: drivers/pci/pci-bridge-emul.c
F: drivers/pci/pci-bridge-emul.h
@ -16055,7 +16049,7 @@ F: Documentation/devicetree/bindings/pci/microchip*
F: drivers/pci/controller/*microchip*
PCIE DRIVER FOR QUALCOMM MSM
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
M: Stanimir Varbanov <svarbanov@mm-sol.com>
L: linux-pci@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
@ -16145,8 +16139,7 @@ F: include/linux/peci-cpu.h
F: include/linux/peci.h
PENSANDO ETHERNET DRIVERS
M: Shannon Nelson <shannon.nelson@amd.com>
M: Brett Creeley <brett.creeley@amd.com>
M: Shannon Nelson <snelson@pensando.io>
M: drivers@pensando.io
L: netdev@vger.kernel.org
S: Supported
@ -17235,7 +17228,7 @@ R: Dongsheng Yang <dongsheng.yang@easystack.cn>
L: ceph-devel@vger.kernel.org
S: Supported
W: http://ceph.com/
T: git https://github.com/ceph/ceph-client.git
T: git git://github.com/ceph/ceph-client.git
F: Documentation/ABI/testing/sysfs-bus-rbd
F: drivers/block/rbd.c
F: drivers/block/rbd_types.h
@ -17488,8 +17481,10 @@ S: Maintained
F: drivers/net/wireless/realtek/rtw89/
REDPINE WIRELESS DRIVER
M: Amitkumar Karwar <amitkarwar@gmail.com>
M: Siva Rebbagondla <siva8118@gmail.com>
L: linux-wireless@vger.kernel.org
S: Orphan
S: Maintained
F: drivers/net/wireless/rsi/
REGISTER MAP ABSTRACTION
@ -17734,7 +17729,7 @@ F: arch/riscv/
N: riscv
K: riscv
RISC-V MICROCHIP FPGA SUPPORT
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Conor Dooley <conor.dooley@microchip.com>
M: Daire McNamara <daire.mcnamara@microchip.com>
L: linux-riscv@lists.infradead.org
@ -17752,26 +17747,17 @@ F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
F: arch/riscv/boot/dts/microchip/
F: drivers/char/hw_random/mpfs-rng.c
F: drivers/clk/microchip/clk-mpfs.c
F: drivers/i2c/busses/i2c-microchip-corei2c.c
F: drivers/i2c/busses/i2c-microchip-core.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/pcie-microchip-host.c
F: drivers/reset/reset-mpfs.c
F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/mpfs-sys-controller.c
F: drivers/soc/microchip/
F: drivers/spi/spi-microchip-core-qspi.c
F: drivers/spi/spi-microchip-core.c
F: drivers/usb/musb/mpfs.c
F: include/soc/microchip/mpfs.h
RISC-V MISC SOC SUPPORT
M: Conor Dooley <conor@kernel.org>
L: linux-riscv@lists.infradead.org
S: Maintained
Q: https://patchwork.kernel.org/project/linux-riscv/list/
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: Documentation/devicetree/bindings/riscv/
F: arch/riscv/boot/dts/
RNBD BLOCK DRIVERS
M: Md. Haris Iqbal <haris.iqbal@ionos.com>
M: Jack Wang <jinpu.wang@ionos.com>
@ -18012,7 +17998,7 @@ L: linux-fbdev@vger.kernel.org
S: Maintained
F: drivers/video/fbdev/savage/
S390 ARCHITECTURE
S390
M: Heiko Carstens <hca@linux.ibm.com>
M: Vasily Gorbik <gor@linux.ibm.com>
M: Alexander Gordeev <agordeev@linux.ibm.com>
@ -18067,15 +18053,6 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/s390/net/
S390 MM
M: Alexander Gordeev <agordeev@linux.ibm.com>
M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
L: linux-s390@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git
F: arch/s390/include/asm/pgtable.h
F: arch/s390/mm
S390 PCI SUBSYSTEM
M: Niklas Schnelle <schnelle@linux.ibm.com>
M: Gerald Schaefer <gerald.schaefer@linux.ibm.com>
@ -18807,6 +18784,7 @@ M: Palmer Dabbelt <palmer@dabbelt.com>
M: Paul Walmsley <paul.walmsley@sifive.com>
L: linux-riscv@lists.infradead.org
S: Supported
T: git https://github.com/sifive/riscv-linux.git
N: sifive
K: [^@]sifive
@ -18825,13 +18803,6 @@ S: Maintained
F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
F: drivers/dma/sf-pdma/
SIFIVE SOC DRIVERS
M: Conor Dooley <conor@kernel.org>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: drivers/soc/sifive/
SILEAD TOUCHSCREEN DRIVER
M: Hans de Goede <hdegoede@redhat.com>
L: linux-input@vger.kernel.org
@ -19633,11 +19604,6 @@ M: Ion Badulescu <ionut@badula.org>
S: Odd Fixes
F: drivers/net/ethernet/adaptec/starfire*
STARFIVE DEVICETREES
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
F: arch/riscv/boot/dts/starfive/
STARFIVE JH7100 CLOCK DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained

View file

@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 0
EXTRAVERSION =
EXTRAVERSION = -rc3
NAME = Hurr durr I'ma ninja sloth
# *DOCUMENTATION*
@ -1218,7 +1218,7 @@ quiet_cmd_ar_vmlinux.a = AR $@
cmd_ar_vmlinux.a = \
rm -f $@; \
$(AR) cDPrST $@ $(KBUILD_VMLINUX_OBJS); \
$(AR) mPiT $$($(AR) t $@ | sed -n 1p) $@ $$($(AR) t $@ | grep -F -f $(srctree)/scripts/head-object-list.txt)
$(AR) mPiT $$($(AR) t $@ | head -n1) $@ $$($(AR) t $@ | grep -F --file=$(srctree)/scripts/head-object-list.txt)
targets += vmlinux.a
vmlinux.a: $(KBUILD_VMLINUX_OBJS) scripts/head-object-list.txt autoksyms_recursive FORCE

View file

@ -12,20 +12,22 @@
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx";
/* Power */
vcc3v3: fixedregulator1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
regulators {
vcc3v3: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
vcc1v8: fixedregulator2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
vcc1v8: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
};
/* User IO */

View file

@ -666,7 +666,7 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "pclk", "hclk";
status = "disabled";
};

View file

@ -39,13 +39,6 @@
};
usb1 {
pinctrl_usb1_vbus_gpio: usb1_vbus_gpio {
atmel,pins =
<AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PC5 GPIO */
};
};
mmc0_slot1 {
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
atmel,pins =
@ -91,8 +84,6 @@
};
usb1: gadget@fffa4000 {
pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
pinctrl-names = "default";
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};

View file

@ -364,8 +364,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
ref-clock-frequency = <38400000>;
tcxo-clock-frequency = <19200000>;
ref-clock-frequency = "38400000";
tcxo-clock-frequency = "19200000";
};
};

View file

@ -33,10 +33,6 @@
status = "okay";
};
&reg_pu {
regulator-always-on;
};
&reg_usb_h1_vbus {
status = "okay";
};

View file

@ -29,7 +29,7 @@
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};

View file

@ -26,7 +26,7 @@
user-pb {
label = "user_pb";
gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};

View file

@ -33,10 +33,6 @@
status = "okay";
};
&reg_pu {
regulator-always-on;
};
&reg_usb_h1_vbus {
status = "okay";
};

View file

@ -69,12 +69,6 @@
pins = "GPIO_35", "GPIO_36";
function = "can0_b";
};
sgpio_a_pins: sgpio-a-pins {
/* SCK, D0, D1, LD */
pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
function = "sgpio_a";
};
};
&can0 {
@ -124,20 +118,6 @@
status = "okay";
};
&sgpio {
pinctrl-0 = <&sgpio_a_pins>;
pinctrl-names = "default";
microchip,sgpio-port-ranges = <0 3>, <8 11>;
status = "okay";
gpio@0 {
ngpios = <64>;
};
gpio@1 {
ngpios = <64>;
};
};
&switch {
status = "okay";
};

View file

@ -35,10 +35,11 @@
&i2c1 {
status = "okay";
hym8563: rtc@51 {
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};

View file

@ -32,7 +32,7 @@
keyup-threshold-microvolt = <2500000>;
poll-interval = <100>;
button-recovery {
recovery {
label = "recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <0>;

View file

@ -71,7 +71,7 @@
#sound-dai-cells = <0>;
};
ir_recv: ir-receiver {
ir_recv: gpio-ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";

View file

@ -379,7 +379,7 @@
rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
};
lcdc1_rgb24: lcdc1-rgb24 {
lcdc1_rgb24: ldcd1-rgb24 {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_none>,
<2 RK_PA2 1 &pcfg_pull_none>,
@ -607,6 +607,7 @@
&global_timer {
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
status = "disabled";
};
&local_timer {

View file

@ -54,7 +54,7 @@
vin-supply = <&vcc_sys>;
};
rtc@51 {
hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;

View file

@ -28,19 +28,19 @@
press-threshold-microvolt = <300000>;
};
button-menu {
menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <640000>;
};
button-esc {
esc {
label = "Esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1000000>;
};
button-home {
home {
label = "Home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <1300000>;

View file

@ -233,10 +233,11 @@
vin-supply = <&vcc_sys>;
};
hym8563: rtc@51 {
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio7>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;

View file

@ -162,10 +162,11 @@
vin-supply = <&vcc_sys>;
};
hym8563: rtc@51 {
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};

View file

@ -165,10 +165,11 @@
};
&i2c0 {
hym8563: rtc@51 {
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;

View file

@ -241,6 +241,7 @@
interrupt-parent = <&gpio5>;
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;

View file

@ -76,13 +76,6 @@
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
status = "disabled";
/* The clock source and the sched_clock provided by the arm_global_timer
* on Rockchip rk3066a/rk3188 are quite unstable because their rates
* depend on the CPU frequency.
* Keep the arm_global_timer disabled in order to have the
* DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
*/
};
local_timer: local-timer@1013c600 {

View file

@ -261,7 +261,7 @@
#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3 35
#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)

View file

@ -24,14 +24,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -28,14 +28,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -44,14 +44,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -57,14 +57,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -30,14 +30,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -35,14 +35,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -30,14 +30,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -34,14 +34,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -30,14 +30,6 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
trips {
battery-crit-hi {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};

View file

@ -17,7 +17,7 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->ARM_pc = (__ip); \
frame_pointer((regs)) = (unsigned long) __builtin_frame_address(0); \
(regs)->ARM_fp = (unsigned long) __builtin_frame_address(0); \
(regs)->ARM_sp = current_stack_pointer; \
(regs)->ARM_cpsr = SVC_MODE; \
}

View file

@ -44,6 +44,12 @@
typedef pte_t *pte_addr_t;
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
#define ZERO_PAGE(vaddr) (virt_to_page(0))
/*
* Mark the prot value as uncacheable and unbufferable.
*/

View file

@ -10,15 +10,6 @@
#include <linux/const.h>
#include <asm/proc-fns.h>
#ifndef __ASSEMBLY__
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
extern struct page *empty_zero_page;
#define ZERO_PAGE(vaddr) (empty_zero_page)
#endif
#ifndef CONFIG_MMU
#include <asm-generic/pgtable-nopud.h>
@ -148,6 +139,13 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
*/
#ifndef __ASSEMBLY__
/*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
extern struct page *empty_zero_page;
#define ZERO_PAGE(vaddr) (empty_zero_page)
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];

View file

@ -169,15 +169,10 @@ sr_ena_2:
cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
bne sr_ena_2
/* Disable DX DLLs for non-backup modes. */
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
cmp r7, #AT91_PM_BACKUP
beq sr_ena_3
/* Do not soft reset the AC DLL. */
ldr tmp1, [r3, DDR3PHY_ACDLLCR]
bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
str tmp1, [r3, DDR3PHY_ACDLLCR]
/* Disable DX DLLs. */
ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS

View file

@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
static void __init sama5_secure_cache_init(void)
{
sam_secure_init();
if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
if (sam_linux_is_optee_available())
outer_cache.write_sec = sama5_l2c310_write_sec;
}

View file

@ -393,10 +393,8 @@ static void __init mxs_machine_init(void)
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
if (ret) {
kfree(soc_dev_attr);
if (ret)
return;
}
soc_dev_attr->family = "Freescale MXS Family";
soc_dev_attr->soc_id = mxs_get_soc_id();

View file

@ -105,19 +105,6 @@ static inline bool is_write_fault(unsigned int fsr)
return (fsr & FSR_WRITE) && !(fsr & FSR_CM);
}
static inline bool is_translation_fault(unsigned int fsr)
{
int fs = fsr_fs(fsr);
#ifdef CONFIG_ARM_LPAE
if ((fs & FS_MMU_NOLL_MASK) == FS_TRANS_NOLL)
return true;
#else
if (fs == FS_L1_TRANS || fs == FS_L2_TRANS)
return true;
#endif
return false;
}
static void die_kernel_fault(const char *msg, struct mm_struct *mm,
unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
@ -153,8 +140,7 @@ __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
if (addr < PAGE_SIZE) {
msg = "NULL pointer dereference";
} else {
if (is_translation_fault(fsr) &&
kfence_handle_page_fault(addr, is_write_fault(fsr), regs))
if (kfence_handle_page_fault(addr, is_write_fault(fsr), regs))
return;
msg = "paging request";
@ -222,7 +208,7 @@ static inline bool is_permission_fault(unsigned int fsr)
{
int fs = fsr_fs(fsr);
#ifdef CONFIG_ARM_LPAE
if ((fs & FS_MMU_NOLL_MASK) == FS_PERM_NOLL)
if ((fs & FS_PERM_NOLL_MASK) == FS_PERM_NOLL)
return true;
#else
if (fs == FS_L1_PERM || fs == FS_L2_PERM)

View file

@ -14,9 +14,8 @@
#ifdef CONFIG_ARM_LPAE
#define FSR_FS_AEA 17
#define FS_TRANS_NOLL 0x4
#define FS_PERM_NOLL 0xC
#define FS_MMU_NOLL_MASK 0x3C
#define FS_PERM_NOLL_MASK 0x3C
static inline int fsr_fs(unsigned int fsr)
{
@ -24,10 +23,8 @@ static inline int fsr_fs(unsigned int fsr)
}
#else
#define FSR_FS_AEA 22
#define FS_L1_TRANS 0x5
#define FS_L2_TRANS 0x7
#define FS_L1_PERM 0xD
#define FS_L2_PERM 0xF
#define FS_L1_PERM 0xD
#define FS_L2_PERM 0xF
static inline int fsr_fs(unsigned int fsr)
{

View file

@ -26,13 +26,6 @@
unsigned long vectors_base;
/*
* empty_zero_page is a special page that is used for
* zero-initialized data and COW.
*/
struct page *empty_zero_page;
EXPORT_SYMBOL(empty_zero_page);
#ifdef CONFIG_ARM_MPU
struct mpu_rgn_info mpu_rgn_info;
#endif
@ -155,21 +148,9 @@ void __init adjust_lowmem_bounds(void)
*/
void __init paging_init(const struct machine_desc *mdesc)
{
void *zero_page;
early_trap_init((void *)vectors_base);
mpu_setup();
/* allocate the zero page. */
zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!zero_page)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
bootmem_init();
empty_zero_page = virt_to_page(zero_page);
flush_dcache_page(empty_zero_page);
}
/*

View file

@ -161,7 +161,6 @@
clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_VP9>;
iommus = <&iommu 5>;
};
video-codec@1c0e000 {

View file

@ -751,26 +751,12 @@
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
trips {
pmic_crit0: trip0 {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
soc {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
trips {
soc_crit0: trip0 {
temperature = <80000>;
hysteresis = <2000>;
type = "critical";
};
};
};
big_cluster_thermal_zone: big-cluster {

View file

@ -779,9 +779,6 @@
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
};
@ -791,9 +788,6 @@
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
};

View file

@ -532,9 +532,6 @@
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@ -544,9 +541,6 @@
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};

View file

@ -1385,9 +1385,6 @@
#address-cells = <1>;
#size-cells = <0>;
little-endian;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@ -1398,9 +1395,6 @@
little-endian;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <2500000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};

View file

@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>,
<&sdhc0_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "ahb", "per";
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>,
<&sdhc1_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "ahb", "per";
<&sdhc1_lpcg IMX_LPCG_CLK_5>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>,
<&sdhc2_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "ahb", "per";
<&sdhc2_lpcg IMX_LPCG_CLK_5>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};

View file

@ -250,21 +250,21 @@
/* SODIMM 96 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
/* CPLD_D[7] */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
/* CPLD_D[6] */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
/* CPLD_D[5] */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
/* CPLD_D[4] */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
/* CPLD_D[3] */
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
/* CPLD_D[2] */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
/* CPLD_D[1] */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
/* CPLD_D[0] */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
/* KBD_intK */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
/* DISP_reset */

View file

@ -34,25 +34,11 @@
off-on-delay-us = <12000>;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
label = "X19";
extcon_usbotg1: extcon-usbotg1 {
compatible = "linux,extcon-usb-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_connector>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_dr_connector: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
pinctrl-0 = <&pinctrl_usb1_extcon>;
id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
};
@ -119,19 +105,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
extcon = <&extcon_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
over-current-active-low;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&usb_dr_connector>;
};
};
};
&usbotg2 {
@ -251,7 +231,7 @@
<MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>;
};
pinctrl_usb1_connector: usb1-connectorgrp {
pinctrl_usb1_extcon: usb1-extcongrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
};

View file

@ -276,7 +276,6 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
usbphynop2: usbphynop2 {
@ -286,7 +285,6 @@
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg2>;
};
soc: soc@0 {
@ -676,11 +674,13 @@
pgc_otg1: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_otg2: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@4 {
@ -1186,7 +1186,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_hsiomix>;
power-domains = <&pgc_otg1>;
status = "disabled";
};
@ -1206,7 +1206,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_hsiomix>;
power-domains = <&pgc_otg2>;
status = "disabled";
};
@ -1244,10 +1244,10 @@
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: nand-controller@33002000 {
gpmi: nand-controller@33002000{
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

View file

@ -662,6 +662,7 @@
pgc_otg1: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MN_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@2 {
@ -1075,7 +1076,7 @@
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_hsiomix>;
power-domains = <&pgc_otg1>;
status = "disabled";
};
@ -1102,7 +1103,7 @@
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@ -1174,6 +1175,5 @@
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
power-domains = <&pgc_otg1>;
};
};

View file

@ -544,14 +544,14 @@
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
>;
};

View file

@ -354,6 +354,16 @@
"SODIMM_82",
"SODIMM_70",
"SODIMM_72";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
&gpio3 {
@ -422,16 +432,6 @@
"SODIMM_256",
"SODIMM_48",
"SODIMM_44";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */

0
arch/arm64/boot/dts/freescale/imx93-pinfunc.h Normal file → Executable file
View file

View file

@ -451,7 +451,7 @@
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
<&clk IMX93_CLK_GPIO2_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 4 30>;
gpio-ranges = <&iomuxc 0 32 32>;
};
gpio3: gpio@43820080 {
@ -465,8 +465,7 @@
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
<&clk IMX93_CLK_GPIO3_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
gpio-ranges = <&iomuxc 0 64 32>;
};
gpio4: gpio@43830080 {
@ -480,7 +479,7 @@
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
<&clk IMX93_CLK_GPIO4_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
gpio-ranges = <&iomuxc 0 96 32>;
};
gpio1: gpio@47400080 {
@ -494,7 +493,7 @@
clocks = <&clk IMX93_CLK_GPIO1_GATE>,
<&clk IMX93_CLK_GPIO1_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 92 16>;
gpio-ranges = <&iomuxc 0 0 32>;
};
s4muap: mailbox@47520000 {
@ -502,7 +501,7 @@
reg = <0x47520000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
interrupt-names = "txirq", "rxirq";
#mbox-cells = <2>;
};

View file

@ -668,7 +668,7 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
reg = <0x0b111000 0x6000>;
#clock-cells = <1>;
#mbox-cells = <1>;

View file

@ -3504,7 +3504,7 @@
};
saw3: syscon@9a10000 {
compatible = "syscon";
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x09a10000 0x1000>;
};

View file

@ -142,22 +142,20 @@
reg = <0x0 0xf6800000 0x0 0x5000>;
no-map;
};
zap_shader_region: gpu@f6900000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf6900000 0x0 0x2000>;
no-map;
};
};
blp637: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3300000>;
voltage-max-design-microvolt = <4370000>;
voltage-min-design-microvolt = <3700000>;
energy-full-design-microwatt-hours = <12700000>;
//operating-range-celsius = <0 45>;
blp637_bat: battery {
compatible = "simple-battery";
voltage-max-design-microvolt = <4370000>;
voltage-min-design-microvolt = <3700000>;
charge-full-design-microamp-hours = <3300000>;
energy-full-design-microwatt-hours = <12700000>;
operating-range-celsius = <0 45>;
};
};
gpio-keys {
@ -320,7 +318,11 @@
compatible = "ti,bq27411";
reg = <0x55>;
monitored-battery = <&blp637>;
/*
* TODO: Adding this appears to not change any reported stats in:
* $ cat /sys/class/power_supply/bq27411-0/uevent
*/
monitored-battery = <&blp637_bat>;
};
};
@ -383,9 +385,10 @@
&pmi8998_charger {
status = "okay";
monitored-battery = <&blp637>;
monitored-battery = <&blp637_bat>;
};
// cat /sys/bus/iio/devices/iio:device0/in_current0_*
&pmi8998_rradc {
status = "okay";
};

Some files were not shown because too many files have changed in this diff Show more