dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
Add the bindings for the CPR3 driver to the documentation. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org>
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AngeloGioacchino Del Regno
Jami Kettunen
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Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
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Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
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description: |
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CPR (Core Power Reduction) is a technology to reduce core power on a CPU
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or other device. Each OPP of a device corresponds to a "corner" that has
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a range of valid voltages for a particular frequency. While the device is
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running at a particular frequency, CPR monitors dynamic factors such as
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temperature, etc. and suggests or, in the CPR-Hardened case performs,
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adjustments to the voltage to save power and meet silicon characteristic
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requirements.
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
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properties:
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compatible:
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oneOf:
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- description: CPRv3 controller
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items:
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- const: qcom,cpr3
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- description: CPRv4 controller
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items:
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- const: qcom,cpr4
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- description: CPRv4-Hardened controller
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items:
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- enum:
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- qcom,msm8998-cprh
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- qcom,sdm630-cprh
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- const: qcom,cprh
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reg:
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description: Base address and size of the CPR controller(s)
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minItems: 1
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maxItems: 2
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: "ref"
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clocks:
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items:
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- description: CPR reference clock
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vdd-supply:
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description: Autonomous Phase Control (APC) or other power supply
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'#power-domain-cells':
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const: 1
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acc-syscon:
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description: phandle to syscon for writing ACC settings
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nvmem-cells:
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description: Cells containing the fuse corners and revision data
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minItems: 10
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maxItems: 32
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nvmem-cell-names:
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minItems: 10
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maxItems: 32
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operating-points-v2: true
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required:
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- compatible
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- reg
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- clock-names
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- clocks
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- "#power-domain-cells"
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- nvmem-cells
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- nvmem-cell-names
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- operating-points-v2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,kryo280";
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device_type = "cpu";
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reg = <0x0 0x0>;
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operating-points-v2 = <&cpu_gold_opp_table>;
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power-domains = <&apc_cprh 0>;
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power-domain-names = "cprh";
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};
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cpu@100 {
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compatible = "qcom,kryo280";
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device_type = "cpu";
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reg = <0x0 0x0>;
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operating-points-v2 = <&cpu_silver_opp_table>;
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power-domains = <&apc_cprh 1>;
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power-domain-names = "cprh";
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};
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};
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cpu_silver_opp_table: cpu-silver-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1843200000 {
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opp-hz = /bits/ 64 <1843200000>;
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required-opps = <&cprh_opp3>;
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};
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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required-opps = <&cprh_opp2>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&cprh_opp1>;
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};
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};
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cpu_gold_opp_table: cpu-gold-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-2208000000 {
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opp-hz = /bits/ 64 <2208000000>;
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required-opps = <&cprh_opp3>;
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};
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opp-1113600000 {
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opp-hz = /bits/ 64 <1113600000>;
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required-opps = <&cprh_opp2>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&cprh_opp1>;
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};
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};
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cprh_opp_table: cpr-hardened-opp-table {
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compatible = "operating-points-v2-qcom-level";
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cprh_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cprh_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cprh_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <2 3>;
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};
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};
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apc_cprh: power-controller@179c8000 {
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compatible = "qcom,msm8998-cprh", "qcom,cprh";
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reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
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clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
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clock-names = "ref";
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#power-domain-cells = <1>;
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operating-points-v2 = <&cprh_opp_table>;
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nvmem-cells = <&cpr_efuse_speedbin>,
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<&cpr_fuse_revision>,
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<&cpr_quot0_pwrcl>,
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<&cpr_quot1_pwrcl>,
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<&cpr_quot2_pwrcl>,
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<&cpr_quot3_pwrcl>,
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<&cpr_quot_offset1_pwrcl>,
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<&cpr_quot_offset2_pwrcl>,
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<&cpr_quot_offset3_pwrcl>,
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<&cpr_init_voltage0_pwrcl>,
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<&cpr_init_voltage1_pwrcl>,
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<&cpr_init_voltage2_pwrcl>,
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<&cpr_init_voltage3_pwrcl>,
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<&cpr_ro_sel0_pwrcl>,
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<&cpr_ro_sel1_pwrcl>,
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<&cpr_ro_sel2_pwrcl>,
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<&cpr_ro_sel3_pwrcl>,
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<&cpr_quot0_perfcl>,
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<&cpr_quot1_perfcl>,
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<&cpr_quot2_perfcl>,
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<&cpr_quot3_perfcl>,
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<&cpr_quot_offset1_perfcl>,
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<&cpr_quot_offset2_perfcl>,
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<&cpr_quot_offset3_perfcl>,
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<&cpr_init_voltage0_perfcl>,
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<&cpr_init_voltage1_perfcl>,
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<&cpr_init_voltage2_perfcl>,
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<&cpr_init_voltage3_perfcl>,
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<&cpr_ro_sel0_perfcl>,
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<&cpr_ro_sel1_perfcl>,
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<&cpr_ro_sel2_perfcl>,
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<&cpr_ro_sel3_perfcl>;
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nvmem-cell-names = "cpr_speed_bin",
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"cpr_fuse_revision",
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"cpr0_quotient1",
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"cpr0_quotient2",
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"cpr0_quotient3",
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"cpr0_quotient4",
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"cpr0_quotient_offset2",
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"cpr0_quotient_offset3",
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"cpr0_quotient_offset4",
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"cpr0_init_voltage1",
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"cpr0_init_voltage2",
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"cpr0_init_voltage3",
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"cpr0_init_voltage4",
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"cpr0_ring_osc1",
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"cpr0_ring_osc2",
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"cpr0_ring_osc3",
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"cpr0_ring_osc4",
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"cpr1_quotient1",
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"cpr1_quotient2",
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"cpr1_quotient3",
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"cpr1_quotient4",
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"cpr1_quotient_offset2",
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"cpr1_quotient_offset3",
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"cpr1_quotient_offset4",
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"cpr1_init_voltage1",
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"cpr1_init_voltage2",
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"cpr1_init_voltage3",
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"cpr1_init_voltage4",
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"cpr1_ring_osc1",
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"cpr1_ring_osc2",
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"cpr1_ring_osc3",
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"cpr1_ring_osc4";
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};
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...
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