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901481 commits

Author SHA1 Message Date
Arnd Bergmann
ca1fa06bdb mvebu arm for 5.6 (part 1)
Various cleanup:
 
 On Orion5x:
 - Drop unneeded select of PCI_DOMAINS_GENERIC
 - Remove unneeded variable ret
 - Replace setup_irq() by request_irq()
 
 On Dove: Mark dove_io_desc as __maybe_unused
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Merge tag 'mvebu-arm-5.7-1' of git://git.infradead.org/linux-mvebu into arm/soc

mvebu arm for 5.6 (part 1)

Various cleanup:

On Orion5x:
- Drop unneeded select of PCI_DOMAINS_GENERIC
- Remove unneeded variable ret
- Replace setup_irq() by request_irq()

On Dove: Mark dove_io_desc as __maybe_unused

* tag 'mvebu-arm-5.7-1' of git://git.infradead.org/linux-mvebu:
  arm: mach-dove: Mark dove_io_desc as __maybe_unused
  ARM: orion: replace setup_irq() by request_irq()
  ARM: orion5x: ts78xx: Remove unneeded variable ret
  ARM: orion5x: Drop unneeded select of PCI_DOMAINS_GENERIC

Link: https://lore.kernel.org/r/87eetux7um.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:00:52 +01:00
Arnd Bergmann
10996b2404 ARM: tegra: Core changes for v5.7-rc1
These patches a preparatory work to move the CPU idle drivers into
 drivers/cpuidle.
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Merge tag 'tegra-for-5.7-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

ARM: tegra: Core changes for v5.7-rc1

These patches a preparatory work to move the CPU idle drivers into
drivers/cpuidle.

* tag 'tegra-for-5.7-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: cpuidle: Remove unnecessary memory barrier
  ARM: tegra: cpuidle: Make abort_flag atomic
  ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2
  ARM: tegra: Make outer_disable() open-coded
  ARM: tegra: Rename some of the newly exposed PM functions
  ARM: tegra: Expose PM functions required for new cpuidle driver
  ARM: tegra: Propagate error from tegra_idle_lp2_last()
  ARM: tegra: Change tegra_set_cpu_in_lp2() type to void
  ARM: tegra: Remove pen-locking from cpuidle-tegra20
  ARM: tegra: Add tegra_pm_park_secondary_cpu()
  ARM: tegra: Compile sleep-tegra20/30.S unconditionally

Link: https://lore.kernel.org/r/20200313165848.2915133-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:58:56 +01:00
Arnd Bergmann
94af02c4bc soc/tegra: Changes for v5.7-rc1
These changes implement various clocks that are controlled by the PMC
 and add support for configuring the voltage level of some pins (needed
 for example to support high-speed modes on the SD/MMC interfaces).
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Merge tag 'tegra-for-5.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

soc/tegra: Changes for v5.7-rc1

These changes implement various clocks that are controlled by the PMC
and add support for configuring the voltage level of some pins (needed
for example to support high-speed modes on the SD/MMC interfaces).

* tag 'tegra-for-5.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Cleanup whitespace usage
  soc/tegra: pmc: Add pins for Tegra194
  soc/tegra: Add support for 32 kHz blink clock
  soc/tegra: Add Tegra PMC clocks registration into PMC driver
  dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding
  dt-bindings: phy: tegra-xusb: Add usb-role-switch
  dt-bindings: phy: tegra: Add Tegra194 support
  dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
  dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
  dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  dt-bindings: clock: tegra: Add IDs for OSC clocks

Link: https://lore.kernel.org/r/20200313165848.2915133-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:56:55 +01:00
Arnd Bergmann
2d5c31a072 STM32 SoC updates for v5.7, round 1
Highlights:
 ----------
 
  - Add early console support for all STM32 SoCs: F4/F7/H7/MP1
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Merge tag 'stm32-soc-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/soc

STM32 SoC updates for v5.7, round 1

Highlights:
----------

 - Add early console support for all STM32 SoCs: F4/F7/H7/MP1

* tag 'stm32-soc-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: debug: stm32: add UART early console support for STM32MP1
  ARM: debug: stm32: add UART early console support for STM32H7
  ARM: debug: stm32: add UART early console configuration for STM32F7
  ARM: debug: stm32: add UART early console configuration for STM32F4

Link: https://lore.kernel.org/r/4e427e37-99c9-239a-f3f8-a3bf50eb1eb2@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:56:29 +01:00
Arnd Bergmann
ce5b71d3ff Allwinner Core Changes for v5.7
Just one change for our mach code for including the correct clk header.
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Merge tag 'sunxi-core-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/soc

Allwinner Core Changes for v5.7

Just one change for our mach code for including the correct clk header.

* tag 'sunxi-core-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: sunxi: Replace <linux/clk-provider.h> by <linux/of_clk.h>

Link: https://lore.kernel.org/r/20200313055342.GA19760@wens.csie.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:55:54 +01:00
Arnd Bergmann
7cd6fa6062 This pull request contains Broadcom ARM64 SoCs changes for 5.7, please
pull the following:
 
 - Geert drops the non-existent HAVE_ARM_ARCH_TIMER symbol select for
   ARCH_BCM2835
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Merge tag 'arm-soc/for-5.7/soc-arm64' of https://github.com/Broadcom/stblinux into arm/soc

This pull request contains Broadcom ARM64 SoCs changes for 5.7, please
pull the following:

- Geert drops the non-existent HAVE_ARM_ARCH_TIMER symbol select for
  ARCH_BCM2835

* tag 'arm-soc/for-5.7/soc-arm64' of https://github.com/Broadcom/stblinux:
  arm64: bcm2835: Drop select of nonexistent HAVE_ARM_ARCH_TIMER

Link: https://lore.kernel.org/r/20200311212012.9418-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:55:15 +01:00
Arnd Bergmann
27262a7544 This pull request contains Broadcom ARM-based SoCs changes for 5.7,
please pull the following:
 
 - Geert drops redundant selects for Broadcom SoCs which are already
   implied by ARCH_MULTI_V6_V7
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Merge tag 'arm-soc/for-5.7/soc' of https://github.com/Broadcom/stblinux into arm/soc

This pull request contains Broadcom ARM-based SoCs changes for 5.7,
please pull the following:

- Geert drops redundant selects for Broadcom SoCs which are already
  implied by ARCH_MULTI_V6_V7

* tag 'arm-soc/for-5.7/soc' of https://github.com/Broadcom/stblinux:
  ARM: bcm: Drop unneeded select of PCI_DOMAINS_GENERIC, HAVE_SMP, TIMER_OF

Link: https://lore.kernel.org/r/20200311212012.9418-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:54:38 +01:00
Arnd Bergmann
f40969fb56 PM changes for am335x and am437x for v5.7 merge window
A series of changes from Dave Gerlach to enable basic cpuidle support
 for am335x and am437x based on generic cpuidle-arm driver.
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Merge tag 'omap-for-v5.7/pm33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

PM changes for am335x and am437x for v5.7 merge window

A series of changes from Dave Gerlach to enable basic cpuidle support
for am335x and am437x based on generic cpuidle-arm driver.

* tag 'omap-for-v5.7/pm33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: omap2plus_defconfig: Add CONFIG_ARM_CPUIDLE
  soc: ti: pm33xx: Add base cpuidle support
  ARM: OMAP2+: pm33xx-core: Extend platform_data ops for cpuidle
  ARM: OMAP2+: pm33xx-core: Add cpuidle_ops for am335x/am437x
  dt-bindings: arm: cpu: Add TI AM335x and AM437x enable method

Link: https://lore.kernel.org/r/pull-1583511417-919838@atomide.com-2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:52:42 +01:00
Arnd Bergmann
6480e7b38d SoC changes for omaps for v5.7 merge window
A change to improve the warning output for device tree data
 mismatch as compared to legacy platform data for ti-sysc
 related interconnect target modules.
 
 And change omap1 to request_irq() instead of setup_irq().
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Merge tag 'omap-for-v5.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

SoC changes for omaps for v5.7 merge window

A change to improve the warning output for device tree data
mismatch as compared to legacy platform data for ti-sysc
related interconnect target modules.

And change omap1 to request_irq() instead of setup_irq().

* tag 'omap-for-v5.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP: replace setup_irq() by request_irq()
  ARM: OMAP2+: Improve handling of ti-sysc related sysc_fields

Link: https://lore.kernel.org/r/pull-1583511417-919838@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:52:08 +01:00
Arnd Bergmann
af839cb0b3 Renesas ARM SoC updates for v5.7
- Enable ARM global timer on Cortex-A9 MPCore SoCs,
   - A minor cleanup.
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Merge tag 'renesas-arm-soc-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc

Renesas ARM SoC updates for v5.7

  - Enable ARM global timer on Cortex-A9 MPCore SoCs,
  - A minor cleanup.

* tag 'renesas-arm-soc-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: shmobile: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  ARM: shmobile: Enable ARM_GLOBAL_TIMER on Cortex-A9 MPCore SoCs

Link: https://lore.kernel.org/r/20200226110221.19288-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:49:02 +01:00
Vincenzo Frascino
afb80cf1e6 arm: mach-dove: Mark dove_io_desc as __maybe_unused
Without this, we get the warnings below when CONFIG_MMU is disabled:

linux/arch/arm/mach-dove/common.c:51:24: warning: ‘dove_io_desc’ defined
but not used [-Wunused-variable]
static struct map_desc dove_io_desc[] __initdata = {
                       ^~~~~~~~~~~~

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-13 21:44:50 +01:00
afzal mohammed
37b146e3f2 ARM: orion: replace setup_irq() by request_irq()
request_irq() is preferred over setup_irq(). Invocations of setup_irq()
occur after memory allocators are ready.

Per tglx[1], setup_irq() existed in olden days when allocators were not
ready by the time early interrupts were initialized.

Hence replace setup_irq() by request_irq().

[1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos

Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-13 21:37:15 +01:00
Erwan Le Ray
62c1594d38 ARM: debug: stm32: add UART early console support for STM32MP1
Add support of early console for STM32MP1. Default UART instance is UART4,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.

Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-03-13 17:05:07 +01:00
Erwan Le Ray
33cab8954a ARM: debug: stm32: add UART early console support for STM32H7
Add support of early console for STM32H7. Default UART instance is USART1,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.

Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-03-13 17:05:07 +01:00
Erwan Le Ray
13f71fa885 ARM: debug: stm32: add UART early console configuration for STM32F7
Early console is hardcoded on USART1 in current implementation.
With this patch, default UART instance is USART1, but other UART instances
can be configured by setting physical and virtual base addresses in
menuconfig.

Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-03-13 17:05:07 +01:00
Erwan Le Ray
79d5cfd19d ARM: debug: stm32: add UART early console configuration for STM32F4
Early console is hardcoded on USART1 in current implementation.
With this patch, default UART instance is USART1, but other UART instances
can be configured by setting physical and virtual base addresses in
menuconfig.

Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-03-13 17:05:07 +01:00
Dmitry Osipenko
650a941c34 ARM: tegra: cpuidle: Remove unnecessary memory barrier
There is no good justification for smp_rmb() after returning from LP2
because there are no memory operations that require SMP synchronization.
Thus remove the confusing barrier.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:23:10 +01:00
Dmitry Osipenko
f0c69bdfb0 ARM: tegra: cpuidle: Make abort_flag atomic
Replace memory accessors with atomic API just to make code consistent
with the abort_barrier. The new variant may be even more correct now
since atomic_read() will prevent compiler from generating wrong things
like carrying abort_flag value in a register instead of re-fetching it
from memory.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:23:09 +01:00
Dmitry Osipenko
51da5f1cd8 ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2
It is possible that something may go wrong with the secondary CPU, in
that case it is much nicer to get a dump of the flow-controller state
before hanging machine.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:23:09 +01:00
Dmitry Osipenko
7ed50dd5dd ARM: tegra: Make outer_disable() open-coded
The outer_disable() of Tegra's suspend code is open-coded now since
that helper produces spurious warning message about secondary CPUs being
online when CPU enters into LP2 from cpuidle. The secondaries are actually
halted by the cpuidle driver on entering into LP2 idle-state, but the
online status is not touched by the cpuidle. This fixes a storm of
warnings once LP2 idling state is enabled on Tegra30. The outer_disable()
helper has sanity checks for interrupts and secondary CPUs being disabled
and we are pretty confident about the interrupts state during of CPU
idling / system suspend. The rail-off status check is added in this patch
as equivalent for the "num_online_cpus() > 1".

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:23:08 +01:00
Dmitry Osipenko
1f3e18ec95 ARM: tegra: Rename some of the newly exposed PM functions
Rename some of the recently exposed PM functions, prefixing them with
"tegra_pm_" in order to make the naming of the PM functions consistent.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:23:08 +01:00
Dmitry Osipenko
7741868f38 ARM: tegra: Expose PM functions required for new cpuidle driver
The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/
directory and it will require all these exposed Tegra PM-core functions.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: fixup missing include rename]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 11:22:41 +01:00
Thierry Reding
4825f5354e soc/tegra: pmc: Cleanup whitespace usage
Avoid using a mixture of tabs and spaces within tables to make them
easier to read and more consistently formatted.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 10:53:10 +01:00
Venkat Reddy Talla
04fac2412b soc/tegra: pmc: Add pins for Tegra194
Extend the Tegra194 IO pad table with additional information such as pin
names and 1.8/3.3 V settings to allow a table of voltage control pins to
generated from it. This is similar to what's done for older chips and is
needed to support high-speed modes for SDHCI where switching the pins to
1.8V or 3.3V is necessary.

Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 10:53:10 +01:00
Sowjanya Komatineni
03e917b2a0 soc/tegra: Add support for 32 kHz blink clock
Tegra PMC has blink control to output 32 kHz clock out to Tegra blink
pin. Blink pad DPD state and enable controls are part of Tegra PMC
register space.

Currently Tegra clock driver registers blink control by passing PMC
address and register offset to clk_register_gate which performs direct
PMC access during clk_ops and with this when PMC is in secure mode, any
access from non-secure world does not go through.

This patch adds blink control registration to the Tegra PMC driver using
PMC specific clock gate operations that use tegra_pmc_readl() and
tegra_pmc_writel() to support both secure mode and non-secure
mode PMC register access.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 10:53:06 +01:00
Sowjanya Komatineni
bd9638ed8e soc/tegra: Add Tegra PMC clocks registration into PMC driver
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.

With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.

This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.

clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 10:52:53 +01:00
Thierry Reding
c66a455f05 Merge branch 'for-5.7/dt-bindings' into for-5.7/soc 2020-03-13 10:52:41 +01:00
Nagarjuna Kristam
eba512375e dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding
Add device-tree binding documentation for the XUSB device mode controller
present on Tegra210 and Tegra186 SoC. This controller supports the USB 3.0
specification.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 09:15:11 +01:00
Nagarjuna Kristam
02cd06f2cc dt-bindings: phy: tegra-xusb: Add usb-role-switch
Add usb-role-switch property for Tegra210 and Tegra186 platforms. This
entry is used by XUSB pad controller driver to register for role changes
for OTG/Peripheral capable USB 2 ports.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 09:14:21 +01:00
JC Kuo
c336357085 dt-bindings: phy: tegra: Add Tegra194 support
Extend the bindings to cover the set of features found in Tegra194.
Note that, technically, there are four more supplies connected to the
XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
, but the power sequencing requirements of Tegra194 require these to be
under the control of the PMIC.

Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
is possible for some platforms have long signal trace that could not
provide sufficient electrical environment for Gen 2 speed. This patch
adds a "maximum-speed" property to usb3 ports which can be used to
specify the maximum supported speed for any particular USB 3.1 port.
For a port that is not capable of SuperSpeedPlus, "maximum-speed"
property should carry "super-speed".

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13 09:12:40 +01:00
Dmitry Osipenko
891e1286c1 ARM: tegra: Propagate error from tegra_idle_lp2_last()
Technically cpu_suspend() may fail and it's never good to lose information
about failure. For example things like cpuidle core could correctly sample
idling time in the case of failure.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12 10:54:05 +01:00
Dmitry Osipenko
f5619492c8 ARM: tegra: Change tegra_set_cpu_in_lp2() type to void
The Tegra30 CPUIDLE driver has intention to check whether primary CPU was
the last CPU that entered LP2 (CC6) idle-state, but that functionality
never got utilized because driver never supported the CC6 state for the
case where any secondary CPU is online. The new cpuidle driver will
properly support CC6 on Tegra30, including the case where secondary CPUs
are online, and that knowledge about what CPUs entered into CC6 won't be
needed at all because new driver will use different approach by making use
of the coupled idle-state and explicitly parking secondary CPUs before
entering into CC6. Thus this patch is just a minor cleanup change.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12 10:53:52 +01:00
Dmitry Osipenko
d90bdb72bb ARM: tegra: Remove pen-locking from cpuidle-tegra20
Pen-locking is meant to block CPU0 if CPU1 wakes up during of entering
into LP2 because of some interrupt firing up, preventing unnecessary LP2
enter that will be resumed immediately. Apparently this case doesn't
happen often in practice, I checked how often it takes place and found
that after ~20 hours of browsing web, managing email, watching videos and
idling (15+ hours) there is only a dozen of early LP2 entering abortions
and they all happened while device was idling. Thus let's remove the
pen-locking and make LP2 entering uninterruptible, simplifying code quite
a lot. This will also become very handy for the upcoming unified cpuidle
driver, allowing to have a common LP2 code-path across of different
hardware generations.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12 10:53:37 +01:00
Dmitry Osipenko
859a6f6ee1 ARM: tegra: Add tegra_pm_park_secondary_cpu()
This function resembles tegra_cpu_die() of the hotplug code, but
this variant is more suitable to be used for CPU PM because it's made
specifically to be used by cpu_suspend(). In short this function puts
secondary CPU offline, it will be used by the new CPUIDLE driver.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12 10:53:18 +01:00
Dmitry Osipenko
df25e55488 ARM: tegra: Compile sleep-tegra20/30.S unconditionally
The sleep-tegra*.S provides functionality required for suspend/resume
and CPU hotplugging. The new unified CPUIDLE driver will support multiple
hardware generations starting from Terga20 and ending with Tegra124, the
driver will utilize functions that are provided by the assembly and thus
it is cleaner to compile that code without any build-dependencies in order
to avoid churning with #ifdef's.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12 10:53:04 +01:00
Geert Uytterhoeven
824ca3a2cc ARM: bcm: Drop unneeded select of PCI_DOMAINS_GENERIC, HAVE_SMP, TIMER_OF
Support for Broadcom SoCs depends on ARCH_MULTI_V6_V7, and thus on
ARCH_MULTIPLATFORM, which selects PCI_DOMAINS_GENERIC and TIMER_OF.
Support for the various Broadcom IPROC architected SoCs depends on
ARCH_MULTI_V7, which selects HAVE_SMP.
Hence there is no need for the Broadcom-specific symbols to select any
of them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-03-10 10:58:26 -07:00
Geert Uytterhoeven
feefd39ab6 arm64: bcm2835: Drop select of nonexistent HAVE_ARM_ARCH_TIMER
Unlike on arm32, the HAVE_ARM_ARCH_TIMER config symbol does not exist on
arm64.

Note that the toplevel ARM64 symbol always selects ARM_ARCH_TIMER, so
support for it is always included.

Fixes: 628d30d1cc ("arm64: Add platform selection for BCM2835.")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-03-10 10:57:58 -07:00
Xu Wang
cf8dcf2725 ARM: orion5x: ts78xx: Remove unneeded variable ret
Remove unneeded variable ret used to store return value,just return 0.

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-08 12:42:07 +01:00
Geert Uytterhoeven
49d5b5683a ARM: orion5x: Drop unneeded select of PCI_DOMAINS_GENERIC
Support for Marvell Orion SoCs depends on ARCH_MULTI_V5, and thus on
ARCH_MULTIPLATFORM.
As the latter selects GENERIC_CLOCKEVENTS and USE_OF, there is no need
for ARCH_ORION5X and ARCH_ORION5X_DT to select any of them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-03-08 12:25:43 +01:00
Tony Lindgren
0d53cc8b33 Merge branch 'omap-for-v5.7/omap1' into omap-for-v5.7/soc 2020-03-06 07:17:10 -08:00
afzal mohammed
b75ca52177 ARM: OMAP: replace setup_irq() by request_irq()
request_irq() is preferred over setup_irq(). Invocations of setup_irq()
occur after memory allocators are ready.

Per tglx[1], setup_irq() existed in olden days when allocators were not
ready by the time early interrupts were initialized.

Hence replace setup_irq() by request_irq().

[1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos

Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-03-04 08:30:30 -08:00
Linus Torvalds
98d54f81e3 Linux 5.6-rc4 2020-03-01 16:38:46 -06:00
Linus Torvalds
e70869821a Two more bug fixes (including a regression) for 5.6
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Merge tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4

Pull ext4 fixes from Ted Ts'o:
 "Two more bug fixes (including a regression) for 5.6"

* tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
  ext4: potential crash on allocation error in ext4_alloc_flex_bg_array()
  jbd2: fix data races at struct journal_head
2020-03-01 16:35:08 -06:00
Linus Torvalds
f853ed90e2 More bugfixes, including a few remaining "make W=1" issues such
as too large frame sizes on some configurations.  On the
 ARM side, the compiler was messing up shadow stacks between
 EL1 and EL2 code, which is easily fixed with __always_inline.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
 "More bugfixes, including a few remaining "make W=1" issues such as too
  large frame sizes on some configurations.

  On the ARM side, the compiler was messing up shadow stacks between EL1
  and EL2 code, which is easily fixed with __always_inline"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: VMX: check descriptor table exits on instruction emulation
  kvm: x86: Limit the number of "kvm: disabled by bios" messages
  KVM: x86: avoid useless copy of cpufreq policy
  KVM: allow disabling -Werror
  KVM: x86: allow compiling as non-module with W=1
  KVM: Pre-allocate 1 cpumask variable per cpu for both pv tlb and pv ipis
  KVM: Introduce pv check helpers
  KVM: let declaration of kvm_get_running_vcpus match implementation
  KVM: SVM: allocate AVIC data structures based on kvm_amd module parameter
  arm64: Ask the compiler to __always_inline functions used by KVM at HYP
  KVM: arm64: Define our own swab32() to avoid a uapi static inline
  KVM: arm64: Ask the compiler to __always_inline functions used at HYP
  kvm: arm/arm64: Fold VHE entry/exit work into kvm_vcpu_run_vhe()
  KVM: arm/arm64: Fix up includes for trace.h
2020-03-01 15:16:35 -06:00
Oliver Upton
86f7e90ce8 KVM: VMX: check descriptor table exits on instruction emulation
KVM emulates UMIP on hardware that doesn't support it by setting the
'descriptor table exiting' VM-execution control and performing
instruction emulation. When running nested, this emulation is broken as
KVM refuses to emulate L2 instructions by default.

Correct this regression by allowing the emulation of descriptor table
instructions if L1 hasn't requested 'descriptor table exiting'.

Fixes: 07721feee4 ("KVM: nVMX: Don't emulate instructions in guest mode")
Reported-by: Jan Kiszka <jan.kiszka@web.de>
Cc: stable@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Oliver Upton <oupton@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-01 19:26:31 +01:00
Linus Torvalds
fb279f4e23 Merge branch 'i2c/for-current-fixed' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
 "I2C has three driver bugfixes for you. We agreed on the Mac regression
  to go in via I2C"

* 'i2c/for-current-fixed' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  macintosh: therm_windtunnel: fix regression when instantiating devices
  i2c: altera: Fix potential integer overflow
  i2c: jz4780: silence log flood on txabrt
2020-02-29 19:16:46 -06:00
Dan Carpenter
37b0b6b8b9 ext4: potential crash on allocation error in ext4_alloc_flex_bg_array()
If sbi->s_flex_groups_allocated is zero and the first allocation fails
then this code will crash.  The problem is that "i--" will set "i" to
-1 but when we compare "i >= sbi->s_flex_groups_allocated" then the -1
is type promoted to unsigned and becomes UINT_MAX.  Since UINT_MAX
is more than zero, the condition is true so we call kvfree(new_groups[-1]).
The loop will carry on freeing invalid memory until it crashes.

Fixes: 7c990728b9 ("ext4: fix potential race between s_flex_groups online resizing and access")
Reviewed-by: Suraj Jitindar Singh <surajjs@amazon.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: stable@kernel.org
Link: https://lore.kernel.org/r/20200228092142.7irbc44yaz3by7nb@kili.mountain
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2020-02-29 17:48:08 -05:00
Wolfram Sang
38b17afb0e macintosh: therm_windtunnel: fix regression when instantiating devices
Removing attach_adapter from this driver caused a regression for at
least some machines. Those machines had the sensors described in their
DT, too, so they didn't need manual creation of the sensor devices. The
old code worked, though, because manual creation came first. Creation of
DT devices then failed later and caused error logs, but the sensors
worked nonetheless because of the manually created devices.

When removing attach_adaper, manual creation now comes later and loses
the race. The sensor devices were already registered via DT, yet with
another binding, so the driver could not be bound to it.

This fix refactors the code to remove the race and only manually creates
devices if there are no DT nodes present. Also, the DT binding is updated
to match both, the DT and manually created devices. Because we don't
know which device creation will be used at runtime, the code to start
the kthread is moved to do_probe() which will be called by both methods.

Fixes: 3e7bed5271 ("macintosh: therm_windtunnel: drop using attach_adapter")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=201723
Reported-by: Erhard Furtner <erhard_f@mailbox.org>
Tested-by: Erhard Furtner <erhard_f@mailbox.org>
Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org # v4.19+
2020-02-29 21:13:22 +01:00
Qian Cai
6c5d911249 jbd2: fix data races at struct journal_head
journal_head::b_transaction and journal_head::b_next_transaction could
be accessed concurrently as noticed by KCSAN,

 LTP: starting fsync04
 /dev/zero: Can't open blockdev
 EXT4-fs (loop0): mounting ext3 file system using the ext4 subsystem
 EXT4-fs (loop0): mounted filesystem with ordered data mode. Opts: (null)
 ==================================================================
 BUG: KCSAN: data-race in __jbd2_journal_refile_buffer [jbd2] / jbd2_write_access_granted [jbd2]

 write to 0xffff99f9b1bd0e30 of 8 bytes by task 25721 on cpu 70:
  __jbd2_journal_refile_buffer+0xdd/0x210 [jbd2]
  __jbd2_journal_refile_buffer at fs/jbd2/transaction.c:2569
  jbd2_journal_commit_transaction+0x2d15/0x3f20 [jbd2]
  (inlined by) jbd2_journal_commit_transaction at fs/jbd2/commit.c:1034
  kjournald2+0x13b/0x450 [jbd2]
  kthread+0x1cd/0x1f0
  ret_from_fork+0x27/0x50

 read to 0xffff99f9b1bd0e30 of 8 bytes by task 25724 on cpu 68:
  jbd2_write_access_granted+0x1b2/0x250 [jbd2]
  jbd2_write_access_granted at fs/jbd2/transaction.c:1155
  jbd2_journal_get_write_access+0x2c/0x60 [jbd2]
  __ext4_journal_get_write_access+0x50/0x90 [ext4]
  ext4_mb_mark_diskspace_used+0x158/0x620 [ext4]
  ext4_mb_new_blocks+0x54f/0xca0 [ext4]
  ext4_ind_map_blocks+0xc79/0x1b40 [ext4]
  ext4_map_blocks+0x3b4/0x950 [ext4]
  _ext4_get_block+0xfc/0x270 [ext4]
  ext4_get_block+0x3b/0x50 [ext4]
  __block_write_begin_int+0x22e/0xae0
  __block_write_begin+0x39/0x50
  ext4_write_begin+0x388/0xb50 [ext4]
  generic_perform_write+0x15d/0x290
  ext4_buffered_write_iter+0x11f/0x210 [ext4]
  ext4_file_write_iter+0xce/0x9e0 [ext4]
  new_sync_write+0x29c/0x3b0
  __vfs_write+0x92/0xa0
  vfs_write+0x103/0x260
  ksys_write+0x9d/0x130
  __x64_sys_write+0x4c/0x60
  do_syscall_64+0x91/0xb05
  entry_SYSCALL_64_after_hwframe+0x49/0xbe

 5 locks held by fsync04/25724:
  #0: ffff99f9911093f8 (sb_writers#13){.+.+}, at: vfs_write+0x21c/0x260
  #1: ffff99f9db4c0348 (&sb->s_type->i_mutex_key#15){+.+.}, at: ext4_buffered_write_iter+0x65/0x210 [ext4]
  #2: ffff99f5e7dfcf58 (jbd2_handle){++++}, at: start_this_handle+0x1c1/0x9d0 [jbd2]
  #3: ffff99f9db4c0168 (&ei->i_data_sem){++++}, at: ext4_map_blocks+0x176/0x950 [ext4]
  #4: ffffffff99086b40 (rcu_read_lock){....}, at: jbd2_write_access_granted+0x4e/0x250 [jbd2]
 irq event stamp: 1407125
 hardirqs last  enabled at (1407125): [<ffffffff980da9b7>] __find_get_block+0x107/0x790
 hardirqs last disabled at (1407124): [<ffffffff980da8f9>] __find_get_block+0x49/0x790
 softirqs last  enabled at (1405528): [<ffffffff98a0034c>] __do_softirq+0x34c/0x57c
 softirqs last disabled at (1405521): [<ffffffff97cc67a2>] irq_exit+0xa2/0xc0

 Reported by Kernel Concurrency Sanitizer on:
 CPU: 68 PID: 25724 Comm: fsync04 Tainted: G L 5.6.0-rc2-next-20200221+ #7
 Hardware name: HPE ProLiant DL385 Gen10/ProLiant DL385 Gen10, BIOS A40 07/10/2019

The plain reads are outside of jh->b_state_lock critical section which result
in data races. Fix them by adding pairs of READ|WRITE_ONCE().

Reviewed-by: Jan Kara <jack@suse.cz>
Signed-off-by: Qian Cai <cai@lca.pw>
Link: https://lore.kernel.org/r/20200222043111.2227-1-cai@lca.pw
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2020-02-29 13:40:02 -05:00
Linus Torvalds
7557c1b3f7 SCSI fixes on 20200229
Four small fixes.  Three are in drivers for fairly obvious bugs.  The
 fourth is a set of regressions introduced by the compat_ioctl changes
 because some of the compat updates wrongly replaced .ioctl instead of
 .compat_ioctl.
 
 Signed-off-by: James E.J. Bottomley <jejb@linux.ibm.com>
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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi

Pull SCSI fixes from James Bottomley:
 "Four small fixes.

  Three are in drivers for fairly obvious bugs. The fourth is a set of
  regressions introduced by the compat_ioctl changes because some of the
  compat updates wrongly replaced .ioctl instead of .compat_ioctl"

* tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
  scsi: compat_ioctl: cdrom: Replace .ioctl with .compat_ioctl in four appropriate places
  scsi: zfcp: fix wrong data and display format of SFP+ temperature
  scsi: sd_sbc: Fix sd_zbc_report_zones()
  scsi: libfc: free response frame from GPN_ID
2020-02-29 09:58:47 -06:00