The different port@ entries of the adv7482 nodes shall be encapsulated
in a ports node, add one. This change does not change how the driver
parses the DT and no driver change is needed.
The change however makes it possible to validate the source files with a
correct json-schema.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20211012183431.718691-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The V3U have 32 VIN, 4 CSI-2 and 4 ISP nodes that interact with each
other for video capture. Add all nodes and record how they are
interconnected.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20211012100038.375289-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RZ/G2L SoM has both 64 GB eMMC and microSD connected to SDHI0.
Both these interfaces are mutually exclusive and the SD0 device
selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2]
switch position.
This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch
setting logic for device selection between eMMC and microSD slot
connected to SDHI0.
Set SW1[2] to position 2/OFF for selecting eMMC
Set SW1[2] to position 3/ON for selecting microSD
This patch enables eMMC on RZ/G2L SMARC platform by default.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211010142520.21976-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add compatible values to Ethernet PHY subnodes representing Realtek
RTL8211E PHYs on RZ/G2 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/3b366e3dddd4d3cd7e89b92d3a8f78f6dc18e244.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 boards. This allows software to identify the
PHY model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/07bd7e04dda9e84cde0664980f0b1a6d69e03109.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Atheros
AR8031 PHYs on RZ/G2 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/3f1b58756f149f0c634c66abaecc88e699f4c3cc.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Renesas
uPD60610 or uPD60611 PHYs on RZ/A1 boards. This allows software to
identify the PHY model at any time, regardless of the state of the PHY
reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/335a1dfea905369da683e122e41e08ca1c5f90f7.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Realtek
RTL8201FL PHYs on RZ/A2 boards. This allows software to identify the
PHY model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/a23eca16869457684b0300379233e335b4e2047e.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing SMSC
LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to
identify the PHY model at any time, regardless of the state of the PHY
reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on RZ/G1 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/ce8ae6b199fa244315a008ae31891a808ca1948d.1631174218.git.geert+renesas@glider.be
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ8041 PHYs on RZ/G1 and R-Car Gen2 boards. This allows software to
identify the PHY model at any time, regardless of the state of the PHY
reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/f9e26625924f90eff34fe6f6f02b15fa272c5d80.1631174218.git.geert+renesas@glider.be
While networking works fine in RGMII mode when using the Linux generic
PHY driver, it fails when using the Atheros PHY driver.
Fix this by correcting the Ethernet PHY mode to RGMII-RXID, which works
fine with both drivers.
Fixes: a5200e63af ("arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling")
Reported-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2a4c15b2df23bb63f15abf9dfb88860477f4f523.1632465965.git.geert+renesas@glider.be
According to schematics, and confirmed by ID_REV register contents, the
Ethernet controllers on various development board are not SMSC LAN9220,
but different variants:
- KZM-A9-Dual and KZM-A9-GT: LAN9221,
- Bock-W and Marzen: LAN89218AQ.
Update the compatible values accordingly.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/59c142176f795b3541c935df43ab11cecd77cc61.1631173813.git.geert+renesas@glider.be
Add audio routing for Mic with bias to reduce noise when doing
audio capture.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210921084605.16250-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add IPMMU nodes for r8a779a0. Note that this patch sets the power
domain of IPMMU-VC0 is Always-On tentatively because the SoC doesn't
have A3VC power domain.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210901111305.570206-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI.
The external audio clocks are configured as 0 Hz fixed frequency clocks by
default. Boards that provide audio clocks should override them.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210814135526.15561-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
