Maxime Ripard fa4d0ca104 clk: sunxi: Add PLL3 clock ... The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2016-04-22 00:29:23 +02:00
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bindings	clk: sunxi: Add PLL3 clock	2016-04-22 00:29:23 +02:00
00-INDEX
booting-without-of.txt	sh: add device tree support and generic board using device tree	2016-03-17 19:46:11 +00:00
changesets.txt	of: Transactional DT support.	2014-07-23 17:29:15 -06:00
dynamic-resolution-notes.txt	of: Introduce Device Tree resolve support.	2014-10-04 21:24:26 +01:00
of_unittest.txt	Documentation: rename of_selftest.txt to of_unittest.txt	2015-03-25 00:50:53 -05:00
overlay-notes.txt	Documentation: devicetree: Fix double words in Doumentation/devicetree	2015-01-28 15:13:11 -07:00
todo.txt	of: Eliminate of_allnodes list	2014-11-04 13:29:38 +00:00
usage-model.txt