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linux-xiaomi-chiron/drivers/gpu/drm/pl111
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Linus Walleij eedd6033b4 drm/pl111: Support variants with broken clock divider 
The early Integrator CLCD synthesized in the Integrator CP and
IM-PD1 FPGAs are broken: their clock dividers do not work
properly. Support disabling the clock divider and drive the
clock directly from the parent under these circumstances.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-3-linus.walleij@linaro.org
2018-02-07 09:08:40 +01:00
..
Kconfig drm/pl111: Support handling bridge timings 2018-01-12 14:14:50 +05:30
Makefile main drm pull request for v4.15 2017-11-15 20:42:10 -08:00
pl111_debugfs.c drm/pl111: Add all registers to debugfs 2017-09-10 23:57:57 +02:00
pl111_display.c drm/pl111: Support variants with broken clock divider 2018-02-07 09:08:40 +01:00
pl111_drm.h drm/pl111: Support variants with broken clock divider 2018-02-07 09:08:40 +01:00
pl111_drv.c drm/pl111: Properly detect the ARM PL110 variants 2018-02-07 09:08:23 +01:00
pl111_versatile.c drm/pl111: Support variants with broken clock divider 2018-02-07 09:08:40 +01:00
pl111_versatile.h drm/pl111: Add handling of Versatile platforms 2017-09-10 23:58:42 +02:00