Yu-ting Shen cab5dec425 drm/amd/display: limit display clock to 100MHz to avoid FIFO error ... [Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:10:08 -05:00
..
drm	drm/amd/display: limit display clock to 100MHz to avoid FIFO error	2020-02-25 11:10:08 -05:00
host1x	drm/tegra: Changes for v5.6-rc1	2020-01-15 16:21:28 +10:00
ipu-v3	gpu: ipu-v3: image-convert: only sample into the next tile if necessary	2019-08-19 16:25:30 +02:00
vga	vga: Fix Kconfig indentation	2019-11-20 17:40:32 +01:00
Makefile