2b79c56fb4
Some SGPIO PICs don't follow the standard very well and expect a certain number of clock cycles or port frames in each SGPIO pattern. Add two optional parameters in the DTB that can provide the number of extra clock cycles to be sent before and after SGPIO pattern. Read those parameters from the DTB and send the extra clock cycles. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Tejun Heo <tj@kernel.org> |
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| .. | ||
| ahci-platform.txt | ||
| atmel-at91_cf.txt | ||
| cavium-compact-flash.txt | ||
| exynos-sata-phy.txt | ||
| exynos-sata.txt | ||
| fsl-sata.txt | ||
| imx-pata.txt | ||
| marvell.txt | ||
| pata-arasan.txt | ||
| sata_highbank.txt | ||