694977006a
asm/pgtable-bits.h has grown to become an unreadable mess of #ifdef directives defining bits conditionally upon other bits all at the preprocessing stage, for no good reason. Instead of having quite so many #ifdef's, simply use enums to provide sequential numbering for bit shifts, without having to keep track manually of what the last bit defined was. Masks are defined separately, after the shifts, which allows for most of their definitions to be reused for all systems rather than duplicated. This patch is not intended to make any behavioural change to the code - all bits should be used in the same way they were before this patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13115/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
254 lines
7.4 KiB
C
254 lines
7.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2002 by Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2002 Maciej W. Rozycki
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*/
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#ifndef _ASM_PGTABLE_BITS_H
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#define _ASM_PGTABLE_BITS_H
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/*
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* Note that we shift the lower 32bits of each EntryLo[01] entry
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* 6 bits to the left. That way we can convert the PFN into the
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* physical address by a single 'and' operation and gain 6 additional
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* bits for storing information which isn't present in a normal
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* MIPS page table.
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*
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* Similar to the Alpha port, we need to keep track of the ref
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* and mod bits in software. We have a software "yeah you can read
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* from this page" bit, and a hardware one which actually lets the
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* process read from the page. On the same token we have a software
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* writable bit and the real hardware one which actually lets the
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* process write to the page, this keeps a mod bit via the hardware
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* dirty bit.
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*
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* Certain revisions of the R4000 and R5000 have a bug where if a
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* certain sequence occurs in the last 3 instructions of an executable
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* page, and the following page is not mapped, the cpu can do
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* unpredictable things. The code (when it is written) to deal with
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* this problem will be in the update_mmu_cache() code for the r4k.
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*/
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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/*
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* Page table bit offsets used for 64 bit physical addressing on MIPS32,
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* for example with Alchemy, Netlogic XLP/XLR or XPA.
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*/
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enum pgtable_bits {
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/* Used by TLB hardware (placed in EntryLo*) */
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_PAGE_NO_EXEC_SHIFT,
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_PAGE_NO_READ_SHIFT,
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_PAGE_GLOBAL_SHIFT,
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_PAGE_VALID_SHIFT,
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_PAGE_DIRTY_SHIFT,
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_CACHE_SHIFT,
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/* Used only by software (masked out before writing EntryLo*) */
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_PAGE_PRESENT_SHIFT = 24,
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_PAGE_READ_SHIFT,
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_PAGE_WRITE_SHIFT,
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_PAGE_ACCESSED_SHIFT,
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_PAGE_MODIFIED_SHIFT,
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};
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/*
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* Bits for extended EntryLo0/EntryLo1 registers
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*/
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#define _PFNX_MASK 0xffffff
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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/* Page table bits used for r3k systems */
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enum pgtable_bits {
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/* Used only by software (writes to EntryLo ignored) */
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_PAGE_PRESENT_SHIFT,
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_PAGE_READ_SHIFT,
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_PAGE_WRITE_SHIFT,
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_PAGE_ACCESSED_SHIFT,
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_PAGE_MODIFIED_SHIFT,
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/* Used by TLB hardware (placed in EntryLo) */
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_PAGE_GLOBAL_SHIFT = 8,
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_PAGE_VALID_SHIFT,
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_PAGE_DIRTY_SHIFT,
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_CACHE_UNCACHED_SHIFT,
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};
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#else
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/* Page table bits used for r4k systems */
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enum pgtable_bits {
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/* Used only by software (masked out before writing EntryLo*) */
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_PAGE_PRESENT_SHIFT,
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#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6)
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_PAGE_READ_SHIFT,
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#endif
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_PAGE_WRITE_SHIFT,
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_PAGE_ACCESSED_SHIFT,
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_PAGE_MODIFIED_SHIFT,
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#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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_PAGE_HUGE_SHIFT,
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#endif
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/* Used by TLB hardware (placed in EntryLo*) */
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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_PAGE_NO_EXEC_SHIFT,
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_PAGE_NO_READ_SHIFT,
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_PAGE_READ_SHIFT = _PAGE_NO_READ_SHIFT,
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#endif
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_PAGE_GLOBAL_SHIFT,
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_PAGE_VALID_SHIFT,
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_PAGE_DIRTY_SHIFT,
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_CACHE_SHIFT,
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};
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#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
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/* Used only by software */
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#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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# define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
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#else
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# define _PAGE_READ (1 << _PAGE_READ_SHIFT)
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#endif
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#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
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#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
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#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
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#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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# define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
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#endif
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/* Used by TLB hardware (placed in EntryLo*) */
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#if (defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32))
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# define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
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# define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
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#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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# define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
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# define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_NO_READ_SHIFT) : 0)
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#endif
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#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
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#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
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#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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# define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
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# define _CACHE_MASK _CACHE_UNCACHED
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# define _PFN_SHIFT PAGE_SHIFT
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#else
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# define _CACHE_MASK (7 << _CACHE_SHIFT)
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# define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
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#endif
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#ifndef _PAGE_NO_EXEC
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#define _PAGE_NO_EXEC 0
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#endif
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#ifndef _PAGE_NO_READ
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#define _PAGE_NO_READ 0
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#endif
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#define _PAGE_SILENT_READ _PAGE_VALID
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#define _PAGE_SILENT_WRITE _PAGE_DIRTY
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#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
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/*
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* The final layouts of the PTE bits are:
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*
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* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
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* 32-bit, R1 or earler: CCC D V G M A W R P
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* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
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* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
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*/
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/*
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* pte_to_entrylo converts a page table entry (PTE) into a Mips
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* entrylo0/1 value.
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*/
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static inline uint64_t pte_to_entrylo(unsigned long pte_val)
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{
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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if (cpu_has_rixi) {
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int sa;
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#ifdef CONFIG_32BIT
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sa = 31 - _PAGE_NO_READ_SHIFT;
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#else
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sa = 63 - _PAGE_NO_READ_SHIFT;
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#endif
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/*
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* C has no way to express that this is a DSRL
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* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
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* in the fast path this is done in assembly
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*/
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return (pte_val >> _PAGE_GLOBAL_SHIFT) |
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((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
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}
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#endif
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return pte_val >> _PAGE_GLOBAL_SHIFT;
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}
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/*
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* Cache attributes
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*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _CACHE_CACHABLE_NONCOHERENT 0
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#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
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#elif defined(CONFIG_CPU_SB1)
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/* No penalty for being coherent on the SB1, so just
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use it for "noncoherent" spaces, too. Shouldn't hurt. */
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#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
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#elif defined(CONFIG_CPU_LOONGSON3)
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/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
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#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
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#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
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#elif defined(CONFIG_MACH_INGENIC)
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/* Ingenic uses the WA bit to achieve write-combine memory writes */
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#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_NO_WA
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#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_WA
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#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_UNCACHED
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_NONCOHERENT
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#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_CE
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#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_COW
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_CACHABLE_CUW
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#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
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#endif
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#ifndef _CACHE_UNCACHED_ACCELERATED
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
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#endif
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#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
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#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
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#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
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_PFN_MASK | _CACHE_MASK)
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#endif /* _ASM_PGTABLE_BITS_H */
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