4591c760b7
Add CAN binding documentation for Renesas RZ/N1 SoC. The SJA1000 CAN controller on RZ/N1 SoC has some differences compared to others like it has no clock divider register (CDR) support and it has no HW loopback (HW doesn't see tx messages on rx), so introduced a new compatible 'renesas,rzn1-sja1000' to handle these differences. Link: https://lore.kernel.org/all/20220710115248.190280-3-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
132 lines
3.3 KiB
YAML
132 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/nxp,sja1000.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Memory mapped SJA1000 CAN controller from NXP (formerly Philips)
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maintainers:
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- Wolfgang Grandegger <wg@grandegger.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- nxp,sja1000
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- technologic,sja1000
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- items:
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- enum:
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- renesas,r9a06g032-sja1000 # RZ/N1D
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- renesas,r9a06g033-sja1000 # RZ/N1S
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- const: renesas,rzn1-sja1000 # RZ/N1
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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reg-io-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: I/O register width (in bytes) implemented by this device
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default: 1
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enum: [ 1, 2, 4 ]
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nxp,external-clock-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 16000000
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description: |
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Frequency of the external oscillator clock in Hz.
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The internal clock frequency used by the SJA1000 is half of that value.
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nxp,tx-output-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1, 2, 3 ]
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default: 1
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description: |
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operation mode of the TX output control logic. Valid values are:
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<0> : bi-phase output mode
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<1> : normal output mode (default)
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<2> : test output mode
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<3> : clock output mode
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nxp,tx-output-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0x02
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description: |
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TX output pin configuration. Valid values are any one of the below
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or combination of TX0 and TX1:
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<0x01> : TX0 invert
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<0x02> : TX0 pull-down (default)
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<0x04> : TX0 pull-up
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<0x06> : TX0 push-pull
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<0x08> : TX1 invert
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<0x10> : TX1 pull-down
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<0x20> : TX1 pull-up
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<0x30> : TX1 push-pull
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nxp,clock-out-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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clock frequency in Hz on the CLKOUT pin.
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If not specified or if the specified value is 0, the CLKOUT pin
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will be disabled.
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nxp,no-comparator-bypass:
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type: boolean
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description: Allows to disable the CAN input comparator.
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required:
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- compatible
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- reg
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- interrupts
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allOf:
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- $ref: can-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- technologic,sja1000
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- renesas,rzn1-sja1000
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then:
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required:
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- reg-io-width
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- if:
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properties:
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compatible:
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contains:
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const: renesas,rzn1-sja1000
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then:
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required:
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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can@1a000 {
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compatible = "technologic,sja1000";
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reg = <0x1a000 0x100>;
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interrupts = <1>;
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reg-io-width = <2>;
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nxp,tx-output-config = <0x06>;
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nxp,external-clock-frequency = <24000000>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a06g032-sysctrl.h>
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can@52104000 {
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compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
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reg = <0x52104000 0x800>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
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};
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