linux-xiaomi-chiron/arch/riscv/kernel
Anup Patel 6a1ce99dc4
RISC-V: Don't enable all interrupts in trap_init()
Historically, we have been enabling all interrupts for each
HART in trap_init(). Ideally, we should only enable M-mode
interrupts for M-mode kernel and S-mode interrupts for S-mode
kernel in trap_init().

Currently, we get suprious S-mode interrupts on Kendryte K210
board running M-mode NO-MMU kernel because we are enabling all
interrupts in trap_init(). To fix this, we only enable software
and external interrupt in trap_init(). In future, trap_init()
will only enable software interrupt and PLIC driver will enable
external interrupt using CPU notifiers.

Fixes: a4c3733d32 ("riscv: abstract out CSR names for supervisor vs machine mode")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Palmer Dabbelt <palmerdabbelt@google.com> [QMEU virt machine with SMP]
[Palmer: Move the Fixes up to a newer commit]
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-18 10:34:04 -08:00
..
vdso
.gitignore
asm-offsets.c
cacheinfo.c
clint.c
cpu.c
cpufeature.c
entry.S
fpu.S
ftrace.c
head.h
head.S
irq.c
Makefile
mcount-dyn.S
mcount.S
module-sections.c
module.c
module.lds
perf_callchain.c
perf_event.c
perf_regs.c
process.c
ptrace.c
reset.c
riscv_ksyms.c
sbi.c
setup.c
signal.c
smp.c
smpboot.c
stacktrace.c
sys_riscv.c
syscall_table.c
time.c
traps.c
vdso.c
vmlinux.lds.S