Max Filippov 839769c354 xtensa: fix a7 clobbering in coprocessor context load/store ... Fast coprocessor exception handler saves a3..a6, but coprocessor context load/store code uses a4..a7 as temporaries, potentially clobbering a7. 'Potentially' because coprocessor state load/store macros may not use all four temporary registers (and neither FPU nor HiFi macros do). Use a3..a6 as intended. Cc: stable@vger.kernel.org Fixes: c658eac628 ("[XTENSA] Add support for configurable registers and coprocessors") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2022-04-15 18:44:02 -07:00
..
syscalls
.gitignore
align.S
asm-offsets.c
coprocessor.S	xtensa: fix a7 clobbering in coprocessor context load/store	2022-04-15 18:44:02 -07:00
entry.S
head.S
hw_breakpoint.c
irq.c
jump_label.c	xtensa: patch_text: Fixup last cpu should be master	2022-04-13 03:36:34 -07:00
Makefile
mcount.S
module.c
mxhead.S
pci-dma.c
pci.c
perf_event.c
platform.c
process.c
ptrace.c
s32c1i_selftest.c
setup.c
signal.c
smp.c
stacktrace.c
syscall.c
time.c
traps.c
vectors.S
vmlinux.lds.S
xtensa_ksyms.c