From 0d15c66771bbdd00676361e58e98bc1c59e6f3d8 Mon Sep 17 00:00:00 2001 From: Tadeusz Struk Date: Sat, 15 Jan 2022 17:26:26 -0800 Subject: [PATCH 001/174] tpm: Fix error handling in async work commit 2e8e4c8f6673247e22efc7985ce5497accd16f88 upstream. When an invalid (non existing) handle is used in a TPM command, that uses the resource manager interface (/dev/tpmrm0) the resource manager tries to load it from its internal cache, but fails and the tpm_dev_transmit returns an -EINVAL error to the caller. The existing async handler doesn't handle these error cases currently and the condition in the poll handler never returns mask with EPOLLIN set. The result is that the poll call blocks and the application gets stuck until the user_read_timer wakes it up after 120 sec. Change the tpm_dev_async_work function to handle error conditions returned from tpm_dev_transmit they are also reflected in the poll mask and a correct error code could passed back to the caller. Cc: Jarkko Sakkinen Cc: Jason Gunthorpe Cc: Cc: Cc: Fixes: 9e1b74a63f77 ("tpm: add support for nonblocking operation") Tested-by: Jarkko Sakkinen Signed-off-by: Tadeusz Struk Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Cc: Tadeusz Struk Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm-dev-common.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/char/tpm/tpm-dev-common.c b/drivers/char/tpm/tpm-dev-common.c index c08cbb306636..dc4c0a0a5129 100644 --- a/drivers/char/tpm/tpm-dev-common.c +++ b/drivers/char/tpm/tpm-dev-common.c @@ -69,7 +69,13 @@ static void tpm_dev_async_work(struct work_struct *work) ret = tpm_dev_transmit(priv->chip, priv->space, priv->data_buffer, sizeof(priv->data_buffer)); tpm_put_ops(priv->chip); - if (ret > 0) { + + /* + * If ret is > 0 then tpm_dev_transmit returned the size of the + * response. If ret is < 0 then tpm_dev_transmit failed and + * returned an error code. + */ + if (ret != 0) { priv->response_length = ret; mod_timer(&priv->user_read_timer, jiffies + (120 * HZ)); } From 816a512233527c6e682710dd75348a3529490a61 Mon Sep 17 00:00:00 2001 From: Helmut Grohne Date: Sat, 26 Feb 2022 16:22:56 +0100 Subject: [PATCH 002/174] Bluetooth: btusb: Add another Realtek 8761BU commit 6dfbe29f45fb0bde29213dbd754a79e8bfc6ecef upstream. This device is sometimes wrapped with a label "EDUP". T: Bus=01 Lev=02 Prnt=02 Port=02 Cnt=03 Dev#=107 Spd=12 MxCh= 0 D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=2550 ProdID=8761 Rev= 2.00 S: Manufacturer=Realtek S: Product=Bluetooth Radio S: SerialNumber=00E04C239987 C:* #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=1ms E: Ad=02(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms E: Ad=82(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms Signed-off-by: Helmut Grohne Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1955351 Cc: Ismael Ferreras Morezuelas Signed-off-by: Marcel Holtmann Signed-off-by: Greg Kroah-Hartman --- drivers/bluetooth/btusb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index c30d131da784..5b82fcba7269 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -482,6 +482,8 @@ static const struct usb_device_id blacklist_table[] = { /* Additional Realtek 8761BU Bluetooth devices */ { USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK | BTUSB_WIDEBAND_SPEECH }, + { USB_DEVICE(0x2550, 0x8761), .driver_info = BTUSB_REALTEK | + BTUSB_WIDEBAND_SPEECH }, /* Additional Realtek 8821AE Bluetooth devices */ { USB_DEVICE(0x0b05, 0x17dc), .driver_info = BTUSB_REALTEK }, From ef1a6fe3563cf47ce4fd555727ca80085cf18884 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 22 Mar 2022 17:41:47 -0700 Subject: [PATCH 003/174] llc: fix netdevice reference leaks in llc_ui_bind() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 764f4eb6846f5475f1244767d24d25dd86528a4a upstream. Whenever llc_ui_bind() and/or llc_ui_autobind() took a reference on a netdevice but subsequently fail, they must properly release their reference or risk the infamous message from unregister_netdevice() at device dismantle. unregister_netdevice: waiting for eth0 to become free. Usage count = 3 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Eric Dumazet Reported-by: 赵子轩 Reported-by: Stoyan Manolov Link: https://lore.kernel.org/r/20220323004147.1990845-1-eric.dumazet@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/llc/af_llc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/net/llc/af_llc.c b/net/llc/af_llc.c index 26c00ebf4fba..c86256064743 100644 --- a/net/llc/af_llc.c +++ b/net/llc/af_llc.c @@ -311,6 +311,10 @@ static int llc_ui_autobind(struct socket *sock, struct sockaddr_llc *addr) sock_reset_flag(sk, SOCK_ZAPPED); rc = 0; out: + if (rc) { + dev_put_track(llc->dev, &llc->dev_tracker); + llc->dev = NULL; + } return rc; } @@ -408,6 +412,10 @@ static int llc_ui_bind(struct socket *sock, struct sockaddr *uaddr, int addrlen) out_put: llc_sap_put(sap); out: + if (rc) { + dev_put_track(llc->dev, &llc->dev_tracker); + llc->dev = NULL; + } release_sock(sk); return rc; } From 39504539ca3109cdec24ed54d7de43aa20fe7df8 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 15 Mar 2022 17:41:58 +0100 Subject: [PATCH 004/174] ASoC: sti: Fix deadlock via snd_pcm_stop_xrun() call commit 455c5653f50e10b4f460ef24e99f0044fbe3401c upstream. This is essentially a revert of the commit dc865fb9e7c2 ("ASoC: sti: Use snd_pcm_stop_xrun() helper"), which converted the manual snd_pcm_stop() calls with snd_pcm_stop_xrun(). The commit above introduced a deadlock as snd_pcm_stop_xrun() itself takes the PCM stream lock while the caller already holds it. Since the conversion was done only for consistency reason and the open-call with snd_pcm_stop() to the XRUN state is a correct usage, let's revert the commit back as the fix. Fixes: dc865fb9e7c2 ("ASoC: sti: Use snd_pcm_stop_xrun() helper") Reported-by: Daniel Palmer Cc: Arnaud POULIQUEN Cc: Link: https://lore.kernel.org/r/20220315091319.3351522-1-daniel@0x0f.com Signed-off-by: Takashi Iwai Reviewed-by: Arnaud Pouliquen Link: https://lore.kernel.org/r/20220315164158.19804-1-tiwai@suse.de Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- sound/soc/sti/uniperif_player.c | 6 +++--- sound/soc/sti/uniperif_reader.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sti/uniperif_player.c b/sound/soc/sti/uniperif_player.c index 2ed92c990b97..dd9013c47664 100644 --- a/sound/soc/sti/uniperif_player.c +++ b/sound/soc/sti/uniperif_player.c @@ -91,7 +91,7 @@ static irqreturn_t uni_player_irq_handler(int irq, void *dev_id) SET_UNIPERIF_ITM_BCLR_FIFO_ERROR(player); /* Stop the player */ - snd_pcm_stop_xrun(player->substream); + snd_pcm_stop(player->substream, SNDRV_PCM_STATE_XRUN); } ret = IRQ_HANDLED; @@ -105,7 +105,7 @@ static irqreturn_t uni_player_irq_handler(int irq, void *dev_id) SET_UNIPERIF_ITM_BCLR_DMA_ERROR(player); /* Stop the player */ - snd_pcm_stop_xrun(player->substream); + snd_pcm_stop(player->substream, SNDRV_PCM_STATE_XRUN); ret = IRQ_HANDLED; } @@ -138,7 +138,7 @@ static irqreturn_t uni_player_irq_handler(int irq, void *dev_id) dev_err(player->dev, "Underflow recovery failed\n"); /* Stop the player */ - snd_pcm_stop_xrun(player->substream); + snd_pcm_stop(player->substream, SNDRV_PCM_STATE_XRUN); ret = IRQ_HANDLED; } diff --git a/sound/soc/sti/uniperif_reader.c b/sound/soc/sti/uniperif_reader.c index 136059331211..065c5f0d1f5f 100644 --- a/sound/soc/sti/uniperif_reader.c +++ b/sound/soc/sti/uniperif_reader.c @@ -65,7 +65,7 @@ static irqreturn_t uni_reader_irq_handler(int irq, void *dev_id) if (unlikely(status & UNIPERIF_ITS_FIFO_ERROR_MASK(reader))) { dev_err(reader->dev, "FIFO error detected\n"); - snd_pcm_stop_xrun(reader->substream); + snd_pcm_stop(reader->substream, SNDRV_PCM_STATE_XRUN); ret = IRQ_HANDLED; } From e74a069c6a7bb505f3ade141dddf85f4b0b5145a Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 18 Mar 2022 09:20:36 +0100 Subject: [PATCH 005/174] ALSA: oss: Fix PCM OSS buffer allocation overflow commit efb6402c3c4a7c26d97c92d70186424097b6e366 upstream. We've got syzbot reports hitting INT_MAX overflow at vmalloc() allocation that is called from snd_pcm_plug_alloc(). Although we apply the restrictions to input parameters, it's based only on the hw_params of the underlying PCM device. Since the PCM OSS layer allocates a temporary buffer for the data conversion, the size may become unexpectedly large when more channels or higher rates is given; in the reported case, it went over INT_MAX, hence it hits WARN_ON(). This patch is an attempt to avoid such an overflow and an allocation for too large buffers. First off, it adds the limit of 1MB as the upper bound for period bytes. This must be large enough for all use cases, and we really don't want to handle a larger temporary buffer than this size. The size check is performed at two places, where the original period bytes is calculated and where the plugin buffer size is calculated. In addition, the driver uses array_size() and array3_size() for multiplications to catch overflows for the converted period size and buffer bytes. Reported-by: syzbot+72732c532ac1454eeee9@syzkaller.appspotmail.com Suggested-by: Linus Torvalds Cc: Link: https://lore.kernel.org/r/00000000000085b1b305da5a66f3@google.com Link: https://lore.kernel.org/r/20220318082036.29699-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/oss/pcm_oss.c | 12 ++++++++---- sound/core/oss/pcm_plugin.c | 5 ++++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/sound/core/oss/pcm_oss.c b/sound/core/oss/pcm_oss.c index 3ee9edf85815..f158f0abd25d 100644 --- a/sound/core/oss/pcm_oss.c +++ b/sound/core/oss/pcm_oss.c @@ -774,6 +774,11 @@ static int snd_pcm_oss_period_size(struct snd_pcm_substream *substream, if (oss_period_size < 16) return -EINVAL; + + /* don't allocate too large period; 1MB period must be enough */ + if (oss_period_size > 1024 * 1024) + return -ENOMEM; + runtime->oss.period_bytes = oss_period_size; runtime->oss.period_frames = 1; runtime->oss.periods = oss_periods; @@ -1043,10 +1048,9 @@ static int snd_pcm_oss_change_params_locked(struct snd_pcm_substream *substream) goto failure; } #endif - oss_period_size *= oss_frame_size; - - oss_buffer_size = oss_period_size * runtime->oss.periods; - if (oss_buffer_size < 0) { + oss_period_size = array_size(oss_period_size, oss_frame_size); + oss_buffer_size = array_size(oss_period_size, runtime->oss.periods); + if (oss_buffer_size <= 0) { err = -EINVAL; goto failure; } diff --git a/sound/core/oss/pcm_plugin.c b/sound/core/oss/pcm_plugin.c index 061ba06bc926..82e180c776ae 100644 --- a/sound/core/oss/pcm_plugin.c +++ b/sound/core/oss/pcm_plugin.c @@ -62,7 +62,10 @@ static int snd_pcm_plugin_alloc(struct snd_pcm_plugin *plugin, snd_pcm_uframes_t width = snd_pcm_format_physical_width(format->format); if (width < 0) return width; - size = frames * format->channels * width; + size = array3_size(frames, format->channels, width); + /* check for too large period size once again */ + if (size > 1024 * 1024) + return -ENOMEM; if (snd_BUG_ON(size % 8)) return -ENXIO; size /= 8; From 1e6c2681b520eda29b2e54d5b4ae814b247774d0 Mon Sep 17 00:00:00 2001 From: Reza Jahanbakhshi Date: Fri, 4 Mar 2022 22:23:02 +0100 Subject: [PATCH 006/174] ALSA: usb-audio: add mapping for new Corsair Virtuoso SE commit cd94df1795418056a19ff4cb44eadfc18ac99a57 upstream. New device id for Corsair Virtuoso SE RGB Wireless that currently is not in the mixer_map. This entry in the mixer_map is necessary in order to label its mixer appropriately and allow userspace to pick the correct volume controls. For instance, my own Corsair Virtuoso SE RGB Wireless headset has this new ID and consequently, the sidetone and volume are not working correctly without this change. > sudo lsusb -v | grep -i corsair Bus 007 Device 011: ID 1b1c:0a40 Corsair CORSAIR VIRTUOSO SE Wireless Gam idVendor 0x1b1c Corsair iManufacturer 1 Corsair iProduct 2 CORSAIR VIRTUOSO SE Wireless Gaming Headset Signed-off-by: Reza Jahanbakhshi Cc: Link: https://lore.kernel.org/r/20220304212303.195949-1-reza.jahanbakhshi@gmail.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/usb/mixer_maps.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c index 96991ddf5055..64f5544d0a0a 100644 --- a/sound/usb/mixer_maps.c +++ b/sound/usb/mixer_maps.c @@ -542,6 +542,16 @@ static const struct usbmix_ctl_map usbmix_ctl_maps[] = { .id = USB_ID(0x05a7, 0x40fa), .map = bose_soundlink_map, }, + { + /* Corsair Virtuoso SE Latest (wired mode) */ + .id = USB_ID(0x1b1c, 0x0a3f), + .map = corsair_virtuoso_map, + }, + { + /* Corsair Virtuoso SE Latest (wireless mode) */ + .id = USB_ID(0x1b1c, 0x0a40), + .map = corsair_virtuoso_map, + }, { /* Corsair Virtuoso SE (wired mode) */ .id = USB_ID(0x1b1c, 0x0a3d), From d5ec0858e78262d61d52931dd82e57f24a9fc073 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 4 Mar 2022 10:08:40 -0700 Subject: [PATCH 007/174] ALSA: hda/realtek: Add quirk for Clevo NP70PNJ commit 0c20fce13e6e111463e3a15ce3cf6713fe518388 upstream. Fixes headset detection on Clevo NP70PNJ. Signed-off-by: Tim Crawford Cc: Link: https://lore.kernel.org/r/20220304170840.3351-1-tcrawford@system76.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 3a42457984e9..bd926763fa47 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9103,6 +9103,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1558, 0x8561, "Clevo NH[57][0-9][ER][ACDH]Q", ALC269_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1558, 0x8562, "Clevo NH[57][0-9]RZ[Q]", ALC269_FIXUP_DMIC), SND_PCI_QUIRK(0x1558, 0x8668, "Clevo NP50B[BE]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), + SND_PCI_QUIRK(0x1558, 0x867d, "Clevo NP7[01]PN[HJK]", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1558, 0x8680, "Clevo NJ50LU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1558, 0x8686, "Clevo NH50[CZ]U", ALC256_FIXUP_MIC_NO_PRESENCE_AND_RESUME), SND_PCI_QUIRK(0x1558, 0x8a20, "Clevo NH55DCQ-Y", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), From e3a8cf32beefa998fb3a17e559137b05eda01834 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 7 Mar 2022 12:32:29 -0700 Subject: [PATCH 008/174] ALSA: hda/realtek: Add quirk for Clevo NP50PNJ commit 9cb727506704b5323998047789fc871e64a6aa14 upstream. Fixes headset detection on Clevo NP50PNJ. Signed-off-by: Tim Crawford Cc: Link: https://lore.kernel.org/r/20220307193229.5141-1-tcrawford@system76.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index bd926763fa47..4ddd464470fd 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9103,6 +9103,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1558, 0x8561, "Clevo NH[57][0-9][ER][ACDH]Q", ALC269_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1558, 0x8562, "Clevo NH[57][0-9]RZ[Q]", ALC269_FIXUP_DMIC), SND_PCI_QUIRK(0x1558, 0x8668, "Clevo NP50B[BE]", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), + SND_PCI_QUIRK(0x1558, 0x866d, "Clevo NP5[05]PN[HJK]", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1558, 0x867d, "Clevo NP7[01]PN[HJK]", ALC256_FIXUP_SYSTEM76_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1558, 0x8680, "Clevo NJ50LU", ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1558, 0x8686, "Clevo NH50[CZ]U", ALC256_FIXUP_MIC_NO_PRESENCE_AND_RESUME), From 5d2f019b7a679a02d67d4bda73f09761747363d3 Mon Sep 17 00:00:00 2001 From: huangwenhui Date: Fri, 11 Mar 2022 17:38:36 +0800 Subject: [PATCH 009/174] ALSA: hda/realtek - Fix headset mic problem for a HP machine with alc671 commit 882bd07f564f97fca6e42ce6ce627ce24ce1ef5a upstream. On a HP 288 Pro G8, the front mic could not be detected.In order to get it working, the pin configuration needs to be set correctly, and the ALC671_FIXUP_HP_HEADSET_MIC2 fixup needs to be applied. Signed-off-by: huangwenhui Cc: Link: https://lore.kernel.org/r/20220311093836.20754-1-huangwenhuia@uniontech.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 4ddd464470fd..ba86b09a61af 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -11069,6 +11069,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), + SND_PCI_QUIRK(0x103c, 0x885f, "HP 288 Pro G8", ALC671_FIXUP_HP_HEADSET_MIC2), SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE), SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_ASUS_Nx50), SND_PCI_QUIRK(0x1043, 0x129d, "Asus N750", ALC662_FIXUP_ASUS_Nx50), From 81b0e6aa90e9bacda0850239f00c2a7c76eaaefb Mon Sep 17 00:00:00 2001 From: Jason Zheng Date: Sun, 13 Mar 2022 04:22:16 -0500 Subject: [PATCH 010/174] ALSA: hda/realtek: Add quirk for ASUS GA402 commit b7557267c233b55d8e8d7ba4c68cf944fe2ec02c upstream. ASUS GA402 requires a workaround to manage the routing of its 4 speakers like the other ASUS models. Add a corresponding quirk entry to fix it. Signed-off-by: Jason Zheng Cc: Link: https://lore.kernel.org/r/20220313092216.29858-1-jasonzheng2004@gmail.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index ba86b09a61af..75ff7e8498b8 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9020,6 +9020,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x1e51, "ASUS Zephyrus M15", ALC294_FIXUP_ASUS_GU502_PINS), SND_PCI_QUIRK(0x1043, 0x1e8e, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA401), SND_PCI_QUIRK(0x1043, 0x1f11, "ASUS Zephyrus G14", ALC289_FIXUP_ASUS_GA401), + SND_PCI_QUIRK(0x1043, 0x1d42, "ASUS Zephyrus G14 2022", ALC289_FIXUP_ASUS_GA401), SND_PCI_QUIRK(0x1043, 0x16b2, "ASUS GU603", ALC289_FIXUP_ASUS_GA401), SND_PCI_QUIRK(0x1043, 0x3030, "ASUS ZN270IE", ALC256_FIXUP_ASUS_AIO_GPIO2), SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC), From 1bbf82d9f961414d6c76a08f7f843ea068e0ab7b Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 22 Mar 2022 18:07:17 +0100 Subject: [PATCH 011/174] ALSA: pcm: Fix races among concurrent hw_params and hw_free calls commit 92ee3c60ec9fe64404dc035e7c41277d74aa26cb upstream. Currently we have neither proper check nor protection against the concurrent calls of PCM hw_params and hw_free ioctls, which may result in a UAF. Since the existing PCM stream lock can't be used for protecting the whole ioctl operations, we need a new mutex to protect those racy calls. This patch introduced a new mutex, runtime->buffer_mutex, and applies it to both hw_params and hw_free ioctl code paths. Along with it, the both functions are slightly modified (the mmap_count check is moved into the state-check block) for code simplicity. Reported-by: Hu Jiahui Cc: Reviewed-by: Jaroslav Kysela Link: https://lore.kernel.org/r/20220322170720.3529-2-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- include/sound/pcm.h | 1 + sound/core/pcm.c | 2 ++ sound/core/pcm_native.c | 61 ++++++++++++++++++++++++++--------------- 3 files changed, 42 insertions(+), 22 deletions(-) diff --git a/include/sound/pcm.h b/include/sound/pcm.h index 36da42cd0774..314f2779cab5 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -401,6 +401,7 @@ struct snd_pcm_runtime { wait_queue_head_t tsleep; /* transfer sleep */ struct fasync_struct *fasync; bool stop_operating; /* sync_stop will be called */ + struct mutex buffer_mutex; /* protect for buffer changes */ /* -- private section -- */ void *private_data; diff --git a/sound/core/pcm.c b/sound/core/pcm.c index ba4a987ed1c6..edd9849210f2 100644 --- a/sound/core/pcm.c +++ b/sound/core/pcm.c @@ -969,6 +969,7 @@ int snd_pcm_attach_substream(struct snd_pcm *pcm, int stream, init_waitqueue_head(&runtime->tsleep); runtime->status->state = SNDRV_PCM_STATE_OPEN; + mutex_init(&runtime->buffer_mutex); substream->runtime = runtime; substream->private_data = pcm->private_data; @@ -1002,6 +1003,7 @@ void snd_pcm_detach_substream(struct snd_pcm_substream *substream) } else { substream->runtime = NULL; } + mutex_destroy(&runtime->buffer_mutex); kfree(runtime); put_pid(substream->pid); substream->pid = NULL; diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index a056b3ef3c84..266895374b83 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -685,33 +685,40 @@ static int snd_pcm_hw_params_choose(struct snd_pcm_substream *pcm, return 0; } +#if IS_ENABLED(CONFIG_SND_PCM_OSS) +#define is_oss_stream(substream) ((substream)->oss.oss) +#else +#define is_oss_stream(substream) false +#endif + static int snd_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_pcm_runtime *runtime; - int err, usecs; + int err = 0, usecs; unsigned int bits; snd_pcm_uframes_t frames; if (PCM_RUNTIME_CHECK(substream)) return -ENXIO; runtime = substream->runtime; + mutex_lock(&runtime->buffer_mutex); snd_pcm_stream_lock_irq(substream); switch (runtime->status->state) { case SNDRV_PCM_STATE_OPEN: case SNDRV_PCM_STATE_SETUP: case SNDRV_PCM_STATE_PREPARED: + if (!is_oss_stream(substream) && + atomic_read(&substream->mmap_count)) + err = -EBADFD; break; default: - snd_pcm_stream_unlock_irq(substream); - return -EBADFD; + err = -EBADFD; + break; } snd_pcm_stream_unlock_irq(substream); -#if IS_ENABLED(CONFIG_SND_PCM_OSS) - if (!substream->oss.oss) -#endif - if (atomic_read(&substream->mmap_count)) - return -EBADFD; + if (err) + goto unlock; snd_pcm_sync_stop(substream, true); @@ -799,16 +806,21 @@ static int snd_pcm_hw_params(struct snd_pcm_substream *substream, if (usecs >= 0) cpu_latency_qos_add_request(&substream->latency_pm_qos_req, usecs); - return 0; + err = 0; _error: - /* hardware might be unusable from this time, - so we force application to retry to set - the correct hardware parameter settings */ - snd_pcm_set_state(substream, SNDRV_PCM_STATE_OPEN); - if (substream->ops->hw_free != NULL) - substream->ops->hw_free(substream); - if (substream->managed_buffer_alloc) - snd_pcm_lib_free_pages(substream); + if (err) { + /* hardware might be unusable from this time, + * so we force application to retry to set + * the correct hardware parameter settings + */ + snd_pcm_set_state(substream, SNDRV_PCM_STATE_OPEN); + if (substream->ops->hw_free != NULL) + substream->ops->hw_free(substream); + if (substream->managed_buffer_alloc) + snd_pcm_lib_free_pages(substream); + } + unlock: + mutex_unlock(&runtime->buffer_mutex); return err; } @@ -848,26 +860,31 @@ static int do_hw_free(struct snd_pcm_substream *substream) static int snd_pcm_hw_free(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime; - int result; + int result = 0; if (PCM_RUNTIME_CHECK(substream)) return -ENXIO; runtime = substream->runtime; + mutex_lock(&runtime->buffer_mutex); snd_pcm_stream_lock_irq(substream); switch (runtime->status->state) { case SNDRV_PCM_STATE_SETUP: case SNDRV_PCM_STATE_PREPARED: + if (atomic_read(&substream->mmap_count)) + result = -EBADFD; break; default: - snd_pcm_stream_unlock_irq(substream); - return -EBADFD; + result = -EBADFD; + break; } snd_pcm_stream_unlock_irq(substream); - if (atomic_read(&substream->mmap_count)) - return -EBADFD; + if (result) + goto unlock; result = do_hw_free(substream); snd_pcm_set_state(substream, SNDRV_PCM_STATE_OPEN); cpu_latency_qos_remove_request(&substream->latency_pm_qos_req); + unlock: + mutex_unlock(&runtime->buffer_mutex); return result; } From dd2f8c684da3e226e5ec7a81c89ff5fd4a957a03 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 22 Mar 2022 18:07:18 +0100 Subject: [PATCH 012/174] ALSA: pcm: Fix races among concurrent read/write and buffer changes commit dca947d4d26dbf925a64a6cfb2ddbc035e831a3d upstream. In the current PCM design, the read/write syscalls (as well as the equivalent ioctls) are allowed before the PCM stream is running, that is, at PCM PREPARED state. Meanwhile, we also allow to re-issue hw_params and hw_free ioctl calls at the PREPARED state that may change or free the buffers, too. The problem is that there is no protection against those mix-ups. This patch applies the previously introduced runtime->buffer_mutex to the read/write operations so that the concurrent hw_params or hw_free call can no longer interfere during the operation. The mutex is unlocked before scheduling, so we don't take it too long. Cc: Reviewed-by: Jaroslav Kysela Link: https://lore.kernel.org/r/20220322170720.3529-3-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_lib.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c index f2090025236b..a40a35e51fad 100644 --- a/sound/core/pcm_lib.c +++ b/sound/core/pcm_lib.c @@ -1906,9 +1906,11 @@ static int wait_for_avail(struct snd_pcm_substream *substream, if (avail >= runtime->twake) break; snd_pcm_stream_unlock_irq(substream); + mutex_unlock(&runtime->buffer_mutex); tout = schedule_timeout(wait_time); + mutex_lock(&runtime->buffer_mutex); snd_pcm_stream_lock_irq(substream); set_current_state(TASK_INTERRUPTIBLE); switch (runtime->status->state) { @@ -2219,6 +2221,7 @@ snd_pcm_sframes_t __snd_pcm_lib_xfer(struct snd_pcm_substream *substream, nonblock = !!(substream->f_flags & O_NONBLOCK); + mutex_lock(&runtime->buffer_mutex); snd_pcm_stream_lock_irq(substream); err = pcm_accessible_state(runtime); if (err < 0) @@ -2310,6 +2313,7 @@ snd_pcm_sframes_t __snd_pcm_lib_xfer(struct snd_pcm_substream *substream, if (xfer > 0 && err >= 0) snd_pcm_update_state(substream, runtime); snd_pcm_stream_unlock_irq(substream); + mutex_unlock(&runtime->buffer_mutex); return xfer > 0 ? (snd_pcm_sframes_t)xfer : err; } EXPORT_SYMBOL(__snd_pcm_lib_xfer); From e9d05532252ec41d000021d3cf40f3a2084fd5f9 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 22 Mar 2022 18:07:19 +0100 Subject: [PATCH 013/174] ALSA: pcm: Fix races among concurrent prepare and hw_params/hw_free calls commit 3c3201f8c7bb77eb53b08a3ca8d9a4ddc500b4c0 upstream. Like the previous fixes to hw_params and hw_free ioctl races, we need to paper over the concurrent prepare ioctl calls against hw_params and hw_free, too. This patch implements the locking with the existing runtime->buffer_mutex for prepare ioctls. Unlike the previous case for snd_pcm_hw_hw_params() and snd_pcm_hw_free(), snd_pcm_prepare() is performed to the linked streams, hence the lock can't be applied simply on the top. For tracking the lock in each linked substream, we modify snd_pcm_action_group() slightly and apply the buffer_mutex for the case stream_lock=false (formerly there was no lock applied) there. Cc: Reviewed-by: Jaroslav Kysela Link: https://lore.kernel.org/r/20220322170720.3529-4-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_native.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 266895374b83..0e4fbf5fd87b 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -1190,15 +1190,17 @@ struct action_ops { static int snd_pcm_action_group(const struct action_ops *ops, struct snd_pcm_substream *substream, snd_pcm_state_t state, - bool do_lock) + bool stream_lock) { struct snd_pcm_substream *s = NULL; struct snd_pcm_substream *s1; int res = 0, depth = 1; snd_pcm_group_for_each_entry(s, substream) { - if (do_lock && s != substream) { - if (s->pcm->nonatomic) + if (s != substream) { + if (!stream_lock) + mutex_lock_nested(&s->runtime->buffer_mutex, depth); + else if (s->pcm->nonatomic) mutex_lock_nested(&s->self_group.mutex, depth); else spin_lock_nested(&s->self_group.lock, depth); @@ -1226,18 +1228,18 @@ static int snd_pcm_action_group(const struct action_ops *ops, ops->post_action(s, state); } _unlock: - if (do_lock) { - /* unlock streams */ - snd_pcm_group_for_each_entry(s1, substream) { - if (s1 != substream) { - if (s1->pcm->nonatomic) - mutex_unlock(&s1->self_group.mutex); - else - spin_unlock(&s1->self_group.lock); - } - if (s1 == s) /* end */ - break; + /* unlock streams */ + snd_pcm_group_for_each_entry(s1, substream) { + if (s1 != substream) { + if (!stream_lock) + mutex_unlock(&s1->runtime->buffer_mutex); + else if (s1->pcm->nonatomic) + mutex_unlock(&s1->self_group.mutex); + else + spin_unlock(&s1->self_group.lock); } + if (s1 == s) /* end */ + break; } return res; } @@ -1367,10 +1369,12 @@ static int snd_pcm_action_nonatomic(const struct action_ops *ops, /* Guarantee the group members won't change during non-atomic action */ down_read(&snd_pcm_link_rwsem); + mutex_lock(&substream->runtime->buffer_mutex); if (snd_pcm_stream_linked(substream)) res = snd_pcm_action_group(ops, substream, state, false); else res = snd_pcm_action_single(ops, substream, state); + mutex_unlock(&substream->runtime->buffer_mutex); up_read(&snd_pcm_link_rwsem); return res; } From 5ed8f8e3c4e59d0396b9ccf2e639711e24295bb6 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 22 Mar 2022 18:07:20 +0100 Subject: [PATCH 014/174] ALSA: pcm: Fix races among concurrent prealloc proc writes commit 69534c48ba8ce552ce383b3dfdb271ffe51820c3 upstream. We have no protection against concurrent PCM buffer preallocation changes via proc files, and it may potentially lead to UAF or some weird problem. This patch applies the PCM open_mutex to the proc write operation for avoiding the racy proc writes and the PCM stream open (and further operations). Cc: Reviewed-by: Jaroslav Kysela Link: https://lore.kernel.org/r/20220322170720.3529-5-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_memory.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/sound/core/pcm_memory.c b/sound/core/pcm_memory.c index b70ce3b69ab4..8848d2f3160d 100644 --- a/sound/core/pcm_memory.c +++ b/sound/core/pcm_memory.c @@ -163,19 +163,20 @@ static void snd_pcm_lib_preallocate_proc_write(struct snd_info_entry *entry, size_t size; struct snd_dma_buffer new_dmab; + mutex_lock(&substream->pcm->open_mutex); if (substream->runtime) { buffer->error = -EBUSY; - return; + goto unlock; } if (!snd_info_get_line(buffer, line, sizeof(line))) { snd_info_get_str(str, line, sizeof(str)); size = simple_strtoul(str, NULL, 10) * 1024; if ((size != 0 && size < 8192) || size > substream->dma_max) { buffer->error = -EINVAL; - return; + goto unlock; } if (substream->dma_buffer.bytes == size) - return; + goto unlock; memset(&new_dmab, 0, sizeof(new_dmab)); new_dmab.dev = substream->dma_buffer.dev; if (size > 0) { @@ -189,7 +190,7 @@ static void snd_pcm_lib_preallocate_proc_write(struct snd_info_entry *entry, substream->pcm->card->number, substream->pcm->device, substream->stream ? 'c' : 'p', substream->number, substream->pcm->name, size); - return; + goto unlock; } substream->buffer_bytes_max = size; } else { @@ -201,6 +202,8 @@ static void snd_pcm_lib_preallocate_proc_write(struct snd_info_entry *entry, } else { buffer->error = -EINVAL; } + unlock: + mutex_unlock(&substream->pcm->open_mutex); } static inline void preallocate_info_init(struct snd_pcm_substream *substream) From e7e04e25248372e024821327dbf2ac99077fea41 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 22 Mar 2022 18:13:25 +0100 Subject: [PATCH 015/174] ALSA: pcm: Add stream lock during PCM reset ioctl operations commit 1f68915b2efd0d6bfd6e124aa63c94b3c69f127c upstream. snd_pcm_reset() is a non-atomic operation, and it's allowed to run during the PCM stream running. It implies that the manipulation of hw_ptr and other parameters might be racy. This patch adds the PCM stream lock at appropriate places in snd_pcm_*_reset() actions for covering that. Cc: Reviewed-by: Jaroslav Kysela Link: https://lore.kernel.org/r/20220322171325.4355-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_native.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 0e4fbf5fd87b..704fdc9ebf91 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -1864,11 +1864,13 @@ static int snd_pcm_do_reset(struct snd_pcm_substream *substream, int err = snd_pcm_ops_ioctl(substream, SNDRV_PCM_IOCTL1_RESET, NULL); if (err < 0) return err; + snd_pcm_stream_lock_irq(substream); runtime->hw_ptr_base = 0; runtime->hw_ptr_interrupt = runtime->status->hw_ptr - runtime->status->hw_ptr % runtime->period_size; runtime->silence_start = runtime->status->hw_ptr; runtime->silence_filled = 0; + snd_pcm_stream_unlock_irq(substream); return 0; } @@ -1876,10 +1878,12 @@ static void snd_pcm_post_reset(struct snd_pcm_substream *substream, snd_pcm_state_t state) { struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_stream_lock_irq(substream); runtime->control->appl_ptr = runtime->status->hw_ptr; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && runtime->silence_size > 0) snd_pcm_playback_silence(substream, ULONG_MAX); + snd_pcm_stream_unlock_irq(substream); } static const struct action_ops snd_pcm_action_reset = { From 7188dd4d75f9dab66f51799dd9e0c3cd1c2a39b5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 11 Mar 2022 21:14:00 +0100 Subject: [PATCH 016/174] ALSA: usb-audio: Add mute TLV for playback volumes on RODE NT-USB commit 0f306cca42fe879694fb5e2382748c43dc9e0196 upstream. For the RODE NT-USB the lowest Playback mixer volume setting mutes the audio output. But it is not reported as such causing e.g. PulseAudio to accidentally mute the device when selecting a low volume. Fix this by applying the existing quirk for this kind of issue when the device is detected. Signed-off-by: Lars-Peter Clausen Cc: Link: https://lore.kernel.org/r/20220311201400.235892-1-lars@metafoo.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/usb/mixer_quirks.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c index e447ddd6854c..d35cf54cab33 100644 --- a/sound/usb/mixer_quirks.c +++ b/sound/usb/mixer_quirks.c @@ -3360,9 +3360,10 @@ void snd_usb_mixer_fu_apply_quirk(struct usb_mixer_interface *mixer, if (unitid == 7 && cval->control == UAC_FU_VOLUME) snd_dragonfly_quirk_db_scale(mixer, cval, kctl); break; - /* lowest playback value is muted on C-Media devices */ - case USB_ID(0x0d8c, 0x000c): - case USB_ID(0x0d8c, 0x0014): + /* lowest playback value is muted on some devices */ + case USB_ID(0x0d8c, 0x000c): /* C-Media */ + case USB_ID(0x0d8c, 0x0014): /* C-Media */ + case USB_ID(0x19f7, 0x0003): /* RODE NT-USB */ if (strstr(kctl->id.name, "Playback")) cval->min_mute = 1; break; From efeffb30291ce84f364c460e9312e1c774f359e0 Mon Sep 17 00:00:00 2001 From: Jonathan Teh Date: Sun, 13 Mar 2022 19:56:17 +0000 Subject: [PATCH 017/174] ALSA: cmipci: Restore aux vol on suspend/resume commit c14231cc04337c2c2a937db084af342ce704dbde upstream. Save and restore CM_REG_AUX_VOL instead of register 0x24 twice on suspend/resume. Tested on CMI8738LX. Fixes: cb60e5f5b2b1 ("[ALSA] cmipci - Add PM support") Signed-off-by: Jonathan Teh Cc: Link: https://lore.kernel.org/r/DBAPR04MB7366CB3EA9C8521C35C56E8B920E9@DBAPR04MB7366.eurprd04.prod.outlook.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/cmipci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/pci/cmipci.c b/sound/pci/cmipci.c index 9a678b5cf285..dab801d9d3b4 100644 --- a/sound/pci/cmipci.c +++ b/sound/pci/cmipci.c @@ -298,7 +298,6 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address."); #define CM_MICGAINZ 0x01 /* mic boost */ #define CM_MICGAINZ_SHIFT 0 -#define CM_REG_MIXER3 0x24 #define CM_REG_AUX_VOL 0x26 #define CM_VAUXL_MASK 0xf0 #define CM_VAUXR_MASK 0x0f @@ -3265,7 +3264,7 @@ static int snd_cmipci_probe(struct pci_dev *pci, */ static const unsigned char saved_regs[] = { CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, - CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, + CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL, CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, From 7a378016d63e09fdca5d0ac171bd1c3895599fdb Mon Sep 17 00:00:00 2001 From: Giacomo Guiduzzi Date: Tue, 22 Mar 2022 21:06:54 +0100 Subject: [PATCH 018/174] ALSA: pci: fix reading of swapped values from pcmreg in AC97 codec commit 17aaf0193392cb3451bf0ac75ba396ec4cbded6e upstream. Tests 72 and 78 for ALSA in kselftest fail due to reading inconsistent values from some devices on a VirtualBox Virtual Machine using the snd_intel8x0 driver for the AC'97 Audio Controller device. Taking for example test number 72, this is what the test reports: "Surround Playback Volume.0 expected 1 but read 0, is_volatile 0" "Surround Playback Volume.1 expected 0 but read 1, is_volatile 0" These errors repeat for each value from 0 to 31. Taking a look at these error messages it is possible to notice that the written values are read back swapped. When the write is performed, these values are initially stored in an array used to sanity-check them and write them in the pcmreg array. To write them, the two one-byte values are packed together in a two-byte variable through bitwise operations: the first value is shifted left by one byte and the second value is stored in the right byte through a bitwise OR. When reading the values back, right shifts are performed to retrieve the previously stored bytes. These shifts are executed in the wrong order, thus reporting the values swapped as shown above. This patch fixes this mistake by reversing the read operations' order. Signed-off-by: Giacomo Guiduzzi Signed-off-by: Paolo Valente Cc: Link: https://lore.kernel.org/r/20220322200653.15862-1-guiduzzi.giacomo@gmail.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/ac97/ac97_codec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index 01f296d524ce..cb60a07d39a8 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -938,8 +938,8 @@ static int snd_ac97_ad18xx_pcm_get_volume(struct snd_kcontrol *kcontrol, struct int codec = kcontrol->private_value & 3; mutex_lock(&ac97->page_mutex); - ucontrol->value.integer.value[0] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 0) & 31); - ucontrol->value.integer.value[1] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 8) & 31); + ucontrol->value.integer.value[0] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 8) & 31); + ucontrol->value.integer.value[1] = 31 - ((ac97->spec.ad18xx.pcmreg[codec] >> 0) & 31); mutex_unlock(&ac97->page_mutex); return 0; } From 8e8f66882b14e8806228ab5e9e83cafa3b3865c6 Mon Sep 17 00:00:00 2001 From: Stephane Graber Date: Tue, 22 Mar 2022 18:42:06 -0400 Subject: [PATCH 019/174] drivers: net: xgene: Fix regression in CRC stripping commit e9e6faeafaa00da1851bcf47912b0f1acae666b4 upstream. All packets on ingress (except for jumbo) are terminated with a 4-bytes CRC checksum. It's the responsability of the driver to strip those 4 bytes. Unfortunately a change dating back to March 2017 re-shuffled some code and made the CRC stripping code effectively dead. This change re-orders that part a bit such that the datalen is immediately altered if needed. Fixes: 4902a92270fb ("drivers: net: xgene: Add workaround for errata 10GE_8/ENET_11") Cc: stable@vger.kernel.org Signed-off-by: Stephane Graber Tested-by: Stephane Graber Link: https://lore.kernel.org/r/20220322224205.752795-1-stgraber@ubuntu.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/apm/xgene/xgene_enet_main.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c index ff2d099aab21..53dc8d5fede8 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c @@ -696,6 +696,12 @@ static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, buf_pool->rx_skb[skb_index] = NULL; datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1)); + + /* strip off CRC as HW isn't doing this */ + nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); + if (!nv) + datalen -= 4; + skb_put(skb, datalen); prefetch(skb->data - NET_IP_ALIGN); skb->protocol = eth_type_trans(skb, ndev); @@ -717,12 +723,8 @@ static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, } } - nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); - if (!nv) { - /* strip off CRC as HW isn't doing this */ - datalen -= 4; + if (!nv) goto skip_jumbo; - } slots = page_pool->slots - 1; head = page_pool->head; From dd03640529204ef4b8189fbdea08217d8d98271f Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Thu, 17 Mar 2022 12:04:42 +0100 Subject: [PATCH 020/174] netfilter: nf_tables: initialize registers in nft_do_chain() commit 4c905f6740a365464e91467aa50916555b28213d upstream. Initialize registers to avoid stack leak into userspace. Fixes: 96518518cc41 ("netfilter: add nftables") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_core.c b/net/netfilter/nf_tables_core.c index 36e73f9828c5..8af98239655d 100644 --- a/net/netfilter/nf_tables_core.c +++ b/net/netfilter/nf_tables_core.c @@ -201,7 +201,7 @@ nft_do_chain(struct nft_pktinfo *pkt, void *priv) const struct nft_rule_dp *rule, *last_rule; const struct net *net = nft_net(pkt); const struct nft_expr *expr, *last; - struct nft_regs regs; + struct nft_regs regs = {}; unsigned int stackptr = 0; struct nft_jumpstack jumpstack[NFT_JUMP_STACK_SIZE]; bool genbit = READ_ONCE(net->nft.gencursor); From afdc3f4b81f0ec9f97f0910476af4620a2481a6d Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Thu, 17 Mar 2022 11:59:26 +0100 Subject: [PATCH 021/174] netfilter: nf_tables: validate registers coming from userspace. commit 6e1acfa387b9ff82cfc7db8cc3b6959221a95851 upstream. Bail out in case userspace uses unsupported registers. Fixes: 49499c3e6e18 ("netfilter: nf_tables: switch registers to 32 bit addressing") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index d71a33ae39b3..1f5a0eece0d1 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -9275,17 +9275,23 @@ int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest) } EXPORT_SYMBOL_GPL(nft_parse_u32_check); -static unsigned int nft_parse_register(const struct nlattr *attr) +static unsigned int nft_parse_register(const struct nlattr *attr, u32 *preg) { unsigned int reg; reg = ntohl(nla_get_be32(attr)); switch (reg) { case NFT_REG_VERDICT...NFT_REG_4: - return reg * NFT_REG_SIZE / NFT_REG32_SIZE; + *preg = reg * NFT_REG_SIZE / NFT_REG32_SIZE; + break; + case NFT_REG32_00...NFT_REG32_15: + *preg = reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + break; default: - return reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + return -ERANGE; } + + return 0; } /** @@ -9327,7 +9333,10 @@ int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len) u32 reg; int err; - reg = nft_parse_register(attr); + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + err = nft_validate_register_load(reg, len); if (err < 0) return err; @@ -9382,7 +9391,10 @@ int nft_parse_register_store(const struct nft_ctx *ctx, int err; u32 reg; - reg = nft_parse_register(attr); + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + err = nft_validate_register_store(ctx, reg, data, type, len); if (err < 0) return err; From 4006144228a0529163d47925967af67a86df0add Mon Sep 17 00:00:00 2001 From: Mark Cilissen Date: Mon, 7 Mar 2022 04:16:58 +0100 Subject: [PATCH 022/174] ACPI / x86: Work around broken XSDT on Advantech DAC-BJ01 board commit e702196bf85778f2c5527ca47f33ef2e2fca8297 upstream. On this board the ACPI RSDP structure points to both a RSDT and an XSDT, but the XSDT points to a truncated FADT. This causes all sorts of trouble and usually a complete failure to boot after the following error occurs: ACPI Error: Unsupported address space: 0x20 (*/hwregs-*) ACPI Error: AE_SUPPORT, Unable to initialize fixed events (*/evevent-*) ACPI: Unable to start ACPI Interpreter This leaves the ACPI implementation in such a broken state that subsequent kernel subsystem initialisations go wrong, resulting in among others mismapped PCI memory, SATA and USB enumeration failures, and freezes. As this is an older embedded platform that will likely never see any BIOS updates to address this issue and its default shipping OS only complies to ACPI 1.0, work around this by forcing `acpi=rsdt`. This patch, applied on top of Linux 5.10.102, was confirmed on real hardware to fix the issue. Signed-off-by: Mark Cilissen Cc: All applicable Reviewed-by: Hans de Goede Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/acpi/boot.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 5b6d1a95776f..0d01e7f5078c 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1328,6 +1328,17 @@ static int __init disable_acpi_pci(const struct dmi_system_id *d) return 0; } +static int __init disable_acpi_xsdt(const struct dmi_system_id *d) +{ + if (!acpi_force) { + pr_notice("%s detected: force use of acpi=rsdt\n", d->ident); + acpi_gbl_do_not_use_xsdt = TRUE; + } else { + pr_notice("Warning: DMI blacklist says broken, but acpi XSDT forced\n"); + } + return 0; +} + static int __init dmi_disable_acpi(const struct dmi_system_id *d) { if (!acpi_force) { @@ -1451,6 +1462,19 @@ static const struct dmi_system_id acpi_dmi_table[] __initconst = { DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), }, }, + /* + * Boxes that need ACPI XSDT use disabled due to corrupted tables + */ + { + .callback = disable_acpi_xsdt, + .ident = "Advantech DAC-BJ01", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "NEC"), + DMI_MATCH(DMI_PRODUCT_NAME, "Bearlake CRB Board"), + DMI_MATCH(DMI_BIOS_VERSION, "V1.12"), + DMI_MATCH(DMI_BIOS_DATE, "02/01/2011"), + }, + }, {} }; From 9024419ced01c023889f63095638510f0cabd9aa Mon Sep 17 00:00:00 2001 From: Maximilian Luz Date: Sun, 13 Feb 2022 16:49:20 +0100 Subject: [PATCH 023/174] ACPI: battery: Add device HID and quirk for Microsoft Surface Go 3 commit 7dacee0b9efc8bd061f097b1a8d4daa6591af0c6 upstream. For some reason, the Microsoft Surface Go 3 uses the standard ACPI interface for battery information, but does not use the standard PNP0C0A HID. Instead it uses MSHW0146 as identifier. Add that ID to the driver as this seems to work well. Additionally, the power state is not updated immediately after the AC has been (un-)plugged, so add the respective quirk for that. Signed-off-by: Maximilian Luz Cc: All applicable Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/acpi/battery.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index ea31ae01458b..dc208f5f5a1f 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -59,6 +59,10 @@ MODULE_PARM_DESC(cache_time, "cache time in milliseconds"); static const struct acpi_device_id battery_device_ids[] = { {"PNP0C0A", 0}, + + /* Microsoft Surface Go 3 */ + {"MSHW0146", 0}, + {"", 0}, }; @@ -1148,6 +1152,14 @@ static const struct dmi_system_id bat_dmi_table[] __initconst = { DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad"), }, }, + { + /* Microsoft Surface Go 3 */ + .callback = battery_notification_delay_quirk, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"), + DMI_MATCH(DMI_PRODUCT_NAME, "Surface Go 3"), + }, + }, {}, }; From 0d73a21c488b5f08842a342937677c3fb14436a1 Mon Sep 17 00:00:00 2001 From: Werner Sembach Date: Tue, 15 Mar 2022 20:02:28 +0100 Subject: [PATCH 024/174] ACPI: video: Force backlight native for Clevo NL5xRU and NL5xNU commit c844d22fe0c0b37dc809adbdde6ceb6462c43acf upstream. Clevo NL5xRU and NL5xNU/TUXEDO Aura 15 Gen1 and Gen2 have both a working native and video interface. However the default detection mechanism first registers the video interface before unregistering it again and switching to the native interface during boot. This results in a dangling SBIOS request for backlight change for some reason, causing the backlight to switch to ~2% once per boot on the first power cord connect or disconnect event. Setting the native interface explicitly circumvents this buggy behaviour by avoiding the unregistering process. Signed-off-by: Werner Sembach Cc: All applicable Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/acpi/video_detect.c | 75 +++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 4f64713e9917..becc198e4c22 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -415,6 +415,81 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "GA503"), }, }, + /* + * Clevo NL5xRU and NL5xNU/TUXEDO Aura 15 Gen1 and Gen2 have both a + * working native and video interface. However the default detection + * mechanism first registers the video interface before unregistering + * it again and switching to the native interface during boot. This + * results in a dangling SBIOS request for backlight change for some + * reason, causing the backlight to switch to ~2% once per boot on the + * first power cord connect or disconnect event. Setting the native + * interface explicitly circumvents this buggy behaviour, by avoiding + * the unregistering process. + */ + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xRU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xRU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "SchenkerTechnologiesGmbH"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xRU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Notebook"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xRU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), + DMI_MATCH(DMI_BOARD_NAME, "AURA1501"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xRU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), + DMI_MATCH(DMI_BOARD_NAME, "EDUBOOK1502"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xNU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xNU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "SchenkerTechnologiesGmbH"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"), + }, + }, + { + .callback = video_detect_force_native, + .ident = "Clevo NL5xNU", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Notebook"), + DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"), + }, + }, /* * Desktops which falsely report a backlight and which our heuristics From 608d06085d15e3e8c5b63d66dc0c1e0af141ba18 Mon Sep 17 00:00:00 2001 From: Giovanni Cabiddu Date: Fri, 4 Mar 2022 17:54:47 +0000 Subject: [PATCH 025/174] crypto: qat - disable registration of algorithms commit 8893d27ffcaf6ec6267038a177cb87bcde4dd3de upstream. The implementations of aead and skcipher in the QAT driver do not support properly requests with the CRYPTO_TFM_REQ_MAY_BACKLOG flag set. If the HW queue is full, the driver returns -EBUSY but does not enqueue the request. This can result in applications like dm-crypt waiting indefinitely for a completion of a request that was never submitted to the hardware. To avoid this problem, disable the registration of all crypto algorithms in the QAT driver by setting the number of crypto instances to 0 at configuration time. Cc: stable@vger.kernel.org Signed-off-by: Giovanni Cabiddu Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- drivers/crypto/qat/qat_4xxx/adf_drv.c | 7 +++++++ drivers/crypto/qat/qat_common/qat_crypto.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/crypto/qat/qat_4xxx/adf_drv.c b/drivers/crypto/qat/qat_4xxx/adf_drv.c index a6c78b9c730b..fa4c350c1bf9 100644 --- a/drivers/crypto/qat/qat_4xxx/adf_drv.c +++ b/drivers/crypto/qat/qat_4xxx/adf_drv.c @@ -75,6 +75,13 @@ static int adf_crypto_dev_config(struct adf_accel_dev *accel_dev) if (ret) goto err; + /* Temporarily set the number of crypto instances to zero to avoid + * registering the crypto algorithms. + * This will be removed when the algorithms will support the + * CRYPTO_TFM_REQ_MAY_BACKLOG flag + */ + instances = 0; + for (i = 0; i < instances; i++) { val = i; bank = i * 2; diff --git a/drivers/crypto/qat/qat_common/qat_crypto.c b/drivers/crypto/qat/qat_common/qat_crypto.c index 7234c4940fae..67c9588e89df 100644 --- a/drivers/crypto/qat/qat_common/qat_crypto.c +++ b/drivers/crypto/qat/qat_common/qat_crypto.c @@ -161,6 +161,13 @@ int qat_crypto_dev_config(struct adf_accel_dev *accel_dev) if (ret) goto err; + /* Temporarily set the number of crypto instances to zero to avoid + * registering the crypto algorithms. + * This will be removed when the algorithms will support the + * CRYPTO_TFM_REQ_MAY_BACKLOG flag + */ + instances = 0; + for (i = 0; i < instances; i++) { val = i; snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i); From ef4d3dcd66ac0968f658db8cfacae25eabfd505c Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Wed, 19 Jan 2022 14:18:37 -0600 Subject: [PATCH 026/174] Bluetooth: btusb: Add one more Bluetooth part for the Realtek RTL8852AE commit 2e7b4a328ed6ea57d22853939e69bc86c560996d upstream. This Realtek device has both wifi and BT components. The latter reports a USB ID of 0bda:2852, which is not in the table. BT device description in /sys/kernel/debug/usb/devices contains the following entries: T: Bus=01 Lev=01 Prnt=01 Port=03 Cnt=02 Dev#= 3 Spd=12 MxCh= 0 D: Ver= 1.00 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=0bda ProdID=2852 Rev= 0.00 S: Manufacturer=Realtek S: Product=Bluetooth Radio S: SerialNumber=00e04c000001 C:* #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=1ms E: Ad=02(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms E: Ad=82(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms The missing USB_ID was reported by user trius65 at https://github.com/lwfinger/rtw89/issues/122 Signed-off-by: Larry Finger Cc: stable@vger.kernel.org Signed-off-by: Marcel Holtmann Signed-off-by: Greg Kroah-Hartman --- drivers/bluetooth/btusb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 5b82fcba7269..11e8e1b21d2f 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -405,6 +405,8 @@ static const struct usb_device_id blacklist_table[] = { BTUSB_WIDEBAND_SPEECH }, /* Realtek 8852AE Bluetooth devices */ + { USB_DEVICE(0x0bda, 0x2852), .driver_info = BTUSB_REALTEK | + BTUSB_WIDEBAND_SPEECH }, { USB_DEVICE(0x0bda, 0xc852), .driver_info = BTUSB_REALTEK | BTUSB_WIDEBAND_SPEECH }, { USB_DEVICE(0x0bda, 0x385a), .driver_info = BTUSB_REALTEK | From 72deda4b68bca9b4a6349a977cb83127ea1da391 Mon Sep 17 00:00:00 2001 From: Ismael Ferreras Morezuelas Date: Mon, 7 Mar 2022 21:04:44 +0100 Subject: [PATCH 027/174] Bluetooth: hci_sync: Add a new quirk to skip HCI_FLT_CLEAR_ALL commit 0eaecfb2e4814d51ab172df3823e35d7c488b6d2 upstream. Some controllers have problems with being sent a command to clear all filtering. While the HCI code does not unconditionally send a clear-all anymore at BR/EDR setup (after the state machine refactor), there might be more ways of hitting these codepaths in the future as the kernel develops. Cc: stable@vger.kernel.org Cc: Hans de Goede Signed-off-by: Ismael Ferreras Morezuelas Reviewed-by: Hans de Goede Signed-off-by: Marcel Holtmann Signed-off-by: Greg Kroah-Hartman --- include/net/bluetooth/hci.h | 10 ++++++++++ net/bluetooth/hci_sync.c | 16 ++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 35c073d44ec5..5cb095b09a94 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -255,6 +255,16 @@ enum { * during the hdev->setup vendor callback. */ HCI_QUIRK_BROKEN_READ_TRANSMIT_POWER, + + /* When this quirk is set, HCI_OP_SET_EVENT_FLT requests with + * HCI_FLT_CLEAR_ALL are ignored and event filtering is + * completely avoided. A subset of the CSR controller + * clones struggle with this and instantly lock up. + * + * Note that devices using this must (separately) disable + * runtime suspend, because event filtering takes place there. + */ + HCI_QUIRK_BROKEN_FILTER_CLEAR_ALL, }; /* HCI device flags */ diff --git a/net/bluetooth/hci_sync.c b/net/bluetooth/hci_sync.c index ab9aa700b6b3..5e93f37c2e04 100644 --- a/net/bluetooth/hci_sync.c +++ b/net/bluetooth/hci_sync.c @@ -2806,6 +2806,9 @@ static int hci_set_event_filter_sync(struct hci_dev *hdev, u8 flt_type, if (!hci_dev_test_flag(hdev, HCI_BREDR_ENABLED)) return 0; + if (test_bit(HCI_QUIRK_BROKEN_FILTER_CLEAR_ALL, &hdev->quirks)) + return 0; + memset(&cp, 0, sizeof(cp)); cp.flt_type = flt_type; @@ -2826,6 +2829,13 @@ static int hci_clear_event_filter_sync(struct hci_dev *hdev) if (!hci_dev_test_flag(hdev, HCI_EVENT_FILTER_CONFIGURED)) return 0; + /* In theory the state machine should not reach here unless + * a hci_set_event_filter_sync() call succeeds, but we do + * the check both for parity and as a future reminder. + */ + if (test_bit(HCI_QUIRK_BROKEN_FILTER_CLEAR_ALL, &hdev->quirks)) + return 0; + return hci_set_event_filter_sync(hdev, HCI_FLT_CLEAR_ALL, 0x00, BDADDR_ANY, 0x00); } @@ -4825,6 +4835,12 @@ static int hci_update_event_filter_sync(struct hci_dev *hdev) if (!hci_dev_test_flag(hdev, HCI_BREDR_ENABLED)) return 0; + /* Some fake CSR controllers lock up after setting this type of + * filter, so avoid sending the request altogether. + */ + if (test_bit(HCI_QUIRK_BROKEN_FILTER_CLEAR_ALL, &hdev->quirks)) + return 0; + /* Always clear event filter when starting */ hci_clear_event_filter_sync(hdev); From 5f32afca84d6dbf219d67be66b3f26826d510a0d Mon Sep 17 00:00:00 2001 From: Ismael Ferreras Morezuelas Date: Mon, 7 Mar 2022 21:04:45 +0100 Subject: [PATCH 028/174] Bluetooth: btusb: Use quirk to skip HCI_FLT_CLEAR_ALL on fake CSR controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit b3cf94c8b6b2f1a2b94825a025db291da2b151fd upstream. Another subset of the more recent batch of Chinese clones aren't specs-compliant and seem to lock up whenever they receive a HCI_OP_SET_EVENT_FLT with flt_type set to zero/HCI_FLT_CLEAR_ALL, which on Linux (until the recent HCI state-machine refactor) happened right at BR/EDR setup. As there are other less-straightforward ways of reaching those operations, this patch is still relevant. So, while all the previous efforts to wrangle the herd of fake CSRs seem to be paying off (and these also get detected as such) we still need to take care of this quirk; testers seem to agree that these dongles tend to work well enough afterwards. From some cursory USB packet capture on Windows it seems like that driver doesn't appear to use this clear-all functionality at all. This patch was tested on some really popular AliExpress-style dongles, in my case marked as "V5.0". Chip markings: UG8413, the backside of the PCB says "USB Dangel" (sic). Here is the `hciconfig -a` output; for completeness: hci0: Type: Primary Bus: USB BD Address: 00:1A:7D:DA:7X:XX ACL MTU: 679:8 SCO MTU: 48:16 UP RUNNING PSCAN ISCAN Features: 0xbf 0x3e 0x4d 0xfa 0xdb 0x3d 0x7b 0xc7 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT Name: 'CSR8510 A10.' Class: 0x7c0104 Service Classes: Rendering, Capturing, Object Transfer, Audio, Telephony Device Class: Computer, Desktop workstation HCI Version: 4.0 (0x6) Revision: 0x3120 LMP Version: 4.0 (0x6) Subversion: 0x22bb Manufacturer: Cambridge Silicon Radio (10) As well as the `lsusb -vv -d 0a12:0001`: ID 0a12:0001 Cambridge Silicon Radio, Ltd Bluetooth Dongle (HCI mode) Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 224 Wireless bDeviceSubClass 1 Radio Frequency bDeviceProtocol 1 Bluetooth bMaxPacketSize0 64 idVendor 0x0a12 Cambridge Silicon Radio, Ltd idProduct 0x0001 Bluetooth Dongle (HCI mode) bcdDevice 88.91 iManufacturer 0 iProduct 2 BT DONGLE10 iSerial 0 bNumConfigurations 1 Also, changed the benign dmesg print that shows up whenever the generic force-suspend fails from bt_dev_err to bt_dev_warn; it's okay and done on a best-effort basis, not a problem if that does not work. Also, swapped the HCI subver and LMP subver numbers for the Barrot in the comment, which I copied wrong the last time around. Fixes: 81cac64ba258a ("Bluetooth: Deal with USB devices that are faking CSR vendor") Fixes: cde1a8a992875 ("Bluetooth: btusb: Fix and detect most of the Chinese Bluetooth controllers") Fixes: d74e0ae7e0303 ("Bluetooth: btusb: Fix detection of some fake CSR controllers with a bcdDevice val of 0x0134") Fixes: 0671c0662383e ("Bluetooth: btusb: Add workaround for remote-wakeup issues with Barrot 8041a02 fake CSR controllers") Fixes: f4292e2faf522 ("Bluetooth: btusb: Make the CSR clone chip force-suspend workaround more generic") Link: https://bugzilla.kernel.org/show_bug.cgi?id=60824 Link: https://gist.github.com/nevack/6b36b82d715dc025163d9e9124840a07 Cc: stable@vger.kernel.org Cc: Hans de Goede Tested-by: Gonzalo Tornaría Tested-by: Mateus Lemos Tested-by: Ismael Ferreras Morezuelas Signed-off-by: Ismael Ferreras Morezuelas Reviewed-by: Hans de Goede Signed-off-by: Marcel Holtmann Signed-off-by: Greg Kroah-Hartman --- drivers/bluetooth/btusb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 11e8e1b21d2f..19d5686f8a2a 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -2045,6 +2045,8 @@ static int btusb_setup_csr(struct hci_dev *hdev) */ set_bit(HCI_QUIRK_BROKEN_STORED_LINK_KEY, &hdev->quirks); set_bit(HCI_QUIRK_BROKEN_ERR_DATA_REPORTING, &hdev->quirks); + set_bit(HCI_QUIRK_BROKEN_FILTER_CLEAR_ALL, &hdev->quirks); + set_bit(HCI_QUIRK_NO_SUSPEND_NOTIFIER, &hdev->quirks); /* Clear the reset quirk since this is not an actual * early Bluetooth 1.1 device from CSR. @@ -2055,7 +2057,7 @@ static int btusb_setup_csr(struct hci_dev *hdev) /* * Special workaround for these BT 4.0 chip clones, and potentially more: * - * - 0x0134: a Barrot 8041a02 (HCI rev: 0x1012 sub: 0x0810) + * - 0x0134: a Barrot 8041a02 (HCI rev: 0x0810 sub: 0x1012) * - 0x7558: IC markings FR3191AHAL 749H15143 (HCI rev/sub-version: 0x0709) * * These controllers are really messed-up. @@ -2084,7 +2086,7 @@ static int btusb_setup_csr(struct hci_dev *hdev) if (ret >= 0) msleep(200); else - bt_dev_err(hdev, "CSR: Failed to suspend the device for our Barrot 8041a02 receive-issue workaround"); + bt_dev_warn(hdev, "CSR: Couldn't suspend the device for our Barrot 8041a02 receive-issue workaround"); pm_runtime_forbid(&data->udev->dev); From ae0e10382c3489973df373e1ba076a03f75d37c6 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 25 Feb 2022 11:44:32 +0200 Subject: [PATCH 029/174] Revert "ath: add support for special 0x0 regulatory domain" commit 1ec7ed5163c70a0d040150d2279f932c7e7c143f upstream. This reverts commit 2dc016599cfa9672a147528ca26d70c3654a5423. Users are reporting regressions in regulatory domain detection and channel availability. The problem this was trying to resolve was fixed in firmware anyway: QCA6174 hw3.0: sdio-4.4.1: add firmware.bin_WLAN.RMH.4.4.1-00042 https://github.com/kvalo/ath10k-firmware/commit/4d382787f0efa77dba40394e0bc604f8eff82552 Link: https://bbs.archlinux.org/viewtopic.php?id=254535 Link: http://lists.infradead.org/pipermail/ath10k/2020-April/014871.html Link: http://lists.infradead.org/pipermail/ath10k/2020-May/015152.html Link: https://lore.kernel.org/all/1c160dfb-6ccc-b4d6-76f6-4364e0adb6dd@reox.at/ Fixes: 2dc016599cfa ("ath: add support for special 0x0 regulatory domain") Cc: Cc: Wen Gong Signed-off-by: Brian Norris Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200527165718.129307-1-briannorris@chromium.org Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/ath/regd.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c index b2400e2417a5..f15e7bd690b5 100644 --- a/drivers/net/wireless/ath/regd.c +++ b/drivers/net/wireless/ath/regd.c @@ -667,14 +667,14 @@ ath_regd_init_wiphy(struct ath_regulatory *reg, /* * Some users have reported their EEPROM programmed with - * 0x8000 or 0x0 set, this is not a supported regulatory - * domain but since we have more than one user with it we - * need a solution for them. We default to 0x64, which is - * the default Atheros world regulatory domain. + * 0x8000 set, this is not a supported regulatory domain + * but since we have more than one user with it we need + * a solution for them. We default to 0x64, which is the + * default Atheros world regulatory domain. */ static void ath_regd_sanitize(struct ath_regulatory *reg) { - if (reg->current_rd != COUNTRY_ERD_FLAG && reg->current_rd != 0) + if (reg->current_rd != COUNTRY_ERD_FLAG) return; printk(KERN_DEBUG "ath: EEPROM regdomain sanitized\n"); reg->current_rd = 0x64; From abc9ad36df16e27ac1c665085157f1a082d39bac Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Mon, 13 Dec 2021 19:31:22 +0100 Subject: [PATCH 030/174] drm/virtio: Ensure that objs is not NULL in virtio_gpu_array_put_free() commit 6b79f96f4a23846516e5e6e4dd37fc06f43a60dd upstream. If virtio_gpu_object_shmem_init() fails (e.g. due to fault injection, as it happened in the bug report by syzbot), virtio_gpu_array_put_free() could be called with objs equal to NULL. Ensure that objs is not NULL in virtio_gpu_array_put_free(), or otherwise return from the function. Cc: stable@vger.kernel.org # 5.13.x Signed-off-by: Roberto Sassu Reported-by: syzbot+e9072e90624a31dfa85f@syzkaller.appspotmail.com Fixes: 377f8331d0565 ("drm/virtio: fix possible leak/unlock virtio_gpu_object_array") Link: http://patchwork.freedesktop.org/patch/msgid/20211213183122.838119-1-roberto.sassu@huawei.com Signed-off-by: Gerd Hoffmann Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/virtio/virtgpu_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c index 2de61b63ef91..48d3c9955f0d 100644 --- a/drivers/gpu/drm/virtio/virtgpu_gem.c +++ b/drivers/gpu/drm/virtio/virtgpu_gem.c @@ -248,6 +248,9 @@ void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs) { u32 i; + if (!objs) + return; + for (i = 0; i < objs->nents; i++) drm_gem_object_put(objs->objs[i]); virtio_gpu_array_free(objs); From bff94c57bd130e3062afa94414c2294871314096 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Thu, 10 Feb 2022 21:07:11 +0530 Subject: [PATCH 031/174] jbd2: fix use-after-free of transaction_t race commit cc16eecae687912238ee6efbff71ad31e2bc414e upstream. jbd2_journal_wait_updates() is called with j_state_lock held. But if there is a commit in progress, then this transaction might get committed and freed via jbd2_journal_commit_transaction() -> jbd2_journal_free_transaction(), when we release j_state_lock. So check for journal->j_running_transaction everytime we release and acquire j_state_lock to avoid use-after-free issue. Link: https://lore.kernel.org/r/948c2fed518ae739db6a8f7f83f1d58b504f87d0.1644497105.git.ritesh.list@gmail.com Fixes: 4f98186848707f53 ("jbd2: refactor wait logic for transaction updates into a common function") Cc: stable@kernel.org Reported-and-tested-by: syzbot+afa2ca5171d93e44b348@syzkaller.appspotmail.com Reviewed-by: Jan Kara Signed-off-by: Ritesh Harjani Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/jbd2/transaction.c | 41 +++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c index 8e2f8275a253..259e00046a8b 100644 --- a/fs/jbd2/transaction.c +++ b/fs/jbd2/transaction.c @@ -842,27 +842,38 @@ EXPORT_SYMBOL(jbd2_journal_restart); */ void jbd2_journal_wait_updates(journal_t *journal) { - transaction_t *commit_transaction = journal->j_running_transaction; + DEFINE_WAIT(wait); - if (!commit_transaction) - return; + while (1) { + /* + * Note that the running transaction can get freed under us if + * this transaction is getting committed in + * jbd2_journal_commit_transaction() -> + * jbd2_journal_free_transaction(). This can only happen when we + * release j_state_lock -> schedule() -> acquire j_state_lock. + * Hence we should everytime retrieve new j_running_transaction + * value (after j_state_lock release acquire cycle), else it may + * lead to use-after-free of old freed transaction. + */ + transaction_t *transaction = journal->j_running_transaction; - spin_lock(&commit_transaction->t_handle_lock); - while (atomic_read(&commit_transaction->t_updates)) { - DEFINE_WAIT(wait); + if (!transaction) + break; + spin_lock(&transaction->t_handle_lock); prepare_to_wait(&journal->j_wait_updates, &wait, - TASK_UNINTERRUPTIBLE); - if (atomic_read(&commit_transaction->t_updates)) { - spin_unlock(&commit_transaction->t_handle_lock); - write_unlock(&journal->j_state_lock); - schedule(); - write_lock(&journal->j_state_lock); - spin_lock(&commit_transaction->t_handle_lock); + TASK_UNINTERRUPTIBLE); + if (!atomic_read(&transaction->t_updates)) { + spin_unlock(&transaction->t_handle_lock); + finish_wait(&journal->j_wait_updates, &wait); + break; } + spin_unlock(&transaction->t_handle_lock); + write_unlock(&journal->j_state_lock); + schedule(); finish_wait(&journal->j_wait_updates, &wait); + write_lock(&journal->j_state_lock); } - spin_unlock(&commit_transaction->t_handle_lock); } /** @@ -877,8 +888,6 @@ void jbd2_journal_wait_updates(journal_t *journal) */ void jbd2_journal_lock_updates(journal_t *journal) { - DEFINE_WAIT(wait); - jbd2_might_wait_for_commit(journal); write_lock(&journal->j_state_lock); From cfda62aaf813dd899d35c68abe64db1776ec8009 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 21 Jan 2022 12:40:08 -0800 Subject: [PATCH 032/174] rcu: Don't deboost before reporting expedited quiescent state commit 10c535787436d62ea28156a4b91365fd89b5a432 upstream. Currently rcu_preempt_deferred_qs_irqrestore() releases rnp->boost_mtx before reporting the expedited quiescent state. Under heavy real-time load, this can result in this function being preempted before the quiescent state is reported, which can in turn prevent the expedited grace period from completing. Tim Murray reports that the resulting expedited grace periods can take hundreds of milliseconds and even more than one second, when they should normally complete in less than a millisecond. This was fine given that there were no particular response-time constraints for synchronize_rcu_expedited(), as it was designed for throughput rather than latency. However, some users now need sub-100-millisecond response-time constratints. This patch therefore follows Neeraj's suggestion (seconded by Tim and by Uladzislau Rezki) of simply reversing the two operations. Reported-by: Tim Murray Reported-by: Joel Fernandes Reported-by: Neeraj Upadhyay Reviewed-by: Neeraj Upadhyay Reviewed-by: Uladzislau Rezki (Sony) Tested-by: Tim Murray Cc: Todd Kjos Cc: Sandeep Patil Cc: # 5.4.x Signed-off-by: Paul E. McKenney Signed-off-by: Greg Kroah-Hartman --- kernel/rcu/tree_plugin.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h index c5b45c2f68a1..5678bee7aefe 100644 --- a/kernel/rcu/tree_plugin.h +++ b/kernel/rcu/tree_plugin.h @@ -556,16 +556,16 @@ rcu_preempt_deferred_qs_irqrestore(struct task_struct *t, unsigned long flags) raw_spin_unlock_irqrestore_rcu_node(rnp, flags); } - /* Unboost if we were boosted. */ - if (IS_ENABLED(CONFIG_RCU_BOOST) && drop_boost_mutex) - rt_mutex_futex_unlock(&rnp->boost_mtx.rtmutex); - /* * If this was the last task on the expedited lists, * then we need to report up the rcu_node hierarchy. */ if (!empty_exp && empty_exp_now) rcu_report_exp_rnp(rnp, true); + + /* Unboost if we were boosted. */ + if (IS_ENABLED(CONFIG_RCU_BOOST) && drop_boost_mutex) + rt_mutex_futex_unlock(&rnp->boost_mtx.rtmutex); } else { local_irq_restore(flags); } From a1ad747fc1a0e06d1bf26b996ee8a56b5c8d02d8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 10 Feb 2022 16:24:30 +0100 Subject: [PATCH 033/174] uaccess: fix integer overflow on access_ok() commit 222ca305c9fd39e5ed8104da25c09b2b79a516a8 upstream. Three architectures check the end of a user access against the address limit without taking a possible overflow into account. Passing a negative length or another overflow in here returns success when it should not. Use the most common correct implementation here, which optimizes for a constant 'size' argument, and turns the common case into a single comparison. Cc: stable@vger.kernel.org Fixes: da551281947c ("csky: User access") Fixes: f663b60f5215 ("microblaze: Fix uaccess_ok macro") Fixes: 7567746e1c0d ("Hexagon: Add user access functions") Reported-by: David Laight Reviewed-by: Christoph Hellwig Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- arch/csky/include/asm/uaccess.h | 7 +++---- arch/hexagon/include/asm/uaccess.h | 18 +++++++++--------- arch/microblaze/include/asm/uaccess.h | 19 ++++--------------- 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h index c40f06ee8d3e..ac5a54f57d40 100644 --- a/arch/csky/include/asm/uaccess.h +++ b/arch/csky/include/asm/uaccess.h @@ -3,14 +3,13 @@ #ifndef __ASM_CSKY_UACCESS_H #define __ASM_CSKY_UACCESS_H -#define user_addr_max() \ - (uaccess_kernel() ? KERNEL_DS.seg : get_fs().seg) +#define user_addr_max() (current_thread_info()->addr_limit.seg) static inline int __access_ok(unsigned long addr, unsigned long size) { - unsigned long limit = current_thread_info()->addr_limit.seg; + unsigned long limit = user_addr_max(); - return ((addr < limit) && ((addr + size) < limit)); + return (size <= limit) && (addr <= (limit - size)); } #define __access_ok __access_ok diff --git a/arch/hexagon/include/asm/uaccess.h b/arch/hexagon/include/asm/uaccess.h index ef5bfef8d490..719ba3f3c45c 100644 --- a/arch/hexagon/include/asm/uaccess.h +++ b/arch/hexagon/include/asm/uaccess.h @@ -25,17 +25,17 @@ * Returns true (nonzero) if the memory block *may* be valid, false (zero) * if it is definitely invalid. * - * User address space in Hexagon, like x86, goes to 0xbfffffff, so the - * simple MSB-based tests used by MIPS won't work. Some further - * optimization is probably possible here, but for now, keep it - * reasonably simple and not *too* slow. After all, we've got the - * MMU for backup. */ +#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) +#define user_addr_max() (uaccess_kernel() ? ~0UL : TASK_SIZE) -#define __access_ok(addr, size) \ - ((get_fs().seg == KERNEL_DS.seg) || \ - (((unsigned long)addr < get_fs().seg) && \ - (unsigned long)size < (get_fs().seg - (unsigned long)addr))) +static inline int __access_ok(unsigned long addr, unsigned long size) +{ + unsigned long limit = TASK_SIZE; + + return (size <= limit) && (addr <= (limit - size)); +} +#define __access_ok __access_ok /* * When a kernel-mode page fault is taken, the faulting instruction diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index d2a8ef9f8978..5b6e0e7788f4 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h @@ -39,24 +39,13 @@ # define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) -static inline int access_ok(const void __user *addr, unsigned long size) +static inline int __access_ok(unsigned long addr, unsigned long size) { - if (!size) - goto ok; + unsigned long limit = user_addr_max(); - if ((get_fs().seg < ((unsigned long)addr)) || - (get_fs().seg < ((unsigned long)addr + size - 1))) { - pr_devel("ACCESS fail at 0x%08x (size 0x%x), seg 0x%08x\n", - (__force u32)addr, (u32)size, - (u32)get_fs().seg); - return 0; - } -ok: - pr_devel("ACCESS OK at 0x%08x (size 0x%x), seg 0x%08x\n", - (__force u32)addr, (u32)size, - (u32)get_fs().seg); - return 1; + return (size <= limit) && (addr <= (limit - size)); } +#define access_ok(addr, size) __access_ok((unsigned long)addr, size) # define __FIXUP_SECTION ".section .fixup,\"ax\"\n" # define __EX_TABLE_SECTION ".section __ex_table,\"a\"\n" From 46bb87d40683337757a2f902fcd4244b32bb4e86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Linus=20L=C3=BCssing?= Date: Thu, 10 Mar 2022 19:35:13 +0100 Subject: [PATCH 034/174] mac80211: fix potential double free on mesh join MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 4a2d4496e15ea5bb5c8e83b94ca8ca7fb045e7d3 upstream. While commit 6a01afcf8468 ("mac80211: mesh: Free ie data when leaving mesh") fixed a memory leak on mesh leave / teardown it introduced a potential memory corruption caused by a double free when rejoining the mesh: ieee80211_leave_mesh() -> kfree(sdata->u.mesh.ie); ... ieee80211_join_mesh() -> copy_mesh_setup() -> old_ie = ifmsh->ie; -> kfree(old_ie); This double free / kernel panics can be reproduced by using wpa_supplicant with an encrypted mesh (if set up without encryption via "iw" then ifmsh->ie is always NULL, which avoids this issue). And then calling: $ iw dev mesh0 mesh leave $ iw dev mesh0 mesh join my-mesh Note that typically these commands are not used / working when using wpa_supplicant. And it seems that wpa_supplicant or wpa_cli are going through a NETDEV_DOWN/NETDEV_UP cycle between a mesh leave and mesh join where the NETDEV_UP resets the mesh.ie to NULL via a memcpy of default_mesh_setup in cfg80211_netdev_notifier_call, which then avoids the memory corruption, too. The issue was first observed in an application which was not using wpa_supplicant but "Senf" instead, which implements its own calls to nl80211. Fixing the issue by removing the kfree()'ing of the mesh IE in the mesh join function and leaving it solely up to the mesh leave to free the mesh IE. Cc: stable@vger.kernel.org Fixes: 6a01afcf8468 ("mac80211: mesh: Free ie data when leaving mesh") Reported-by: Matthias Kretschmer Signed-off-by: Linus Lüssing Tested-by: Mathias Kretschmer Link: https://lore.kernel.org/r/20220310183513.28589-1-linus.luessing@c0d3.blue Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/mac80211/cfg.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c index 87a208089caf..58ff57dc669c 100644 --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c @@ -2148,14 +2148,12 @@ static int copy_mesh_setup(struct ieee80211_if_mesh *ifmsh, const struct mesh_setup *setup) { u8 *new_ie; - const u8 *old_ie; struct ieee80211_sub_if_data *sdata = container_of(ifmsh, struct ieee80211_sub_if_data, u.mesh); int i; /* allocate information elements */ new_ie = NULL; - old_ie = ifmsh->ie; if (setup->ie_len) { new_ie = kmemdup(setup->ie, setup->ie_len, @@ -2165,7 +2163,6 @@ static int copy_mesh_setup(struct ieee80211_if_mesh *ifmsh, } ifmsh->ie_len = setup->ie_len; ifmsh->ie = new_ie; - kfree(old_ie); /* now copy the rest of the setup parameters */ ifmsh->mesh_id_len = setup->mesh_id_len; From 6e7baf84149fb43950631415de231b3a41915aa3 Mon Sep 17 00:00:00 2001 From: Lino Sanfilippo Date: Wed, 2 Mar 2022 10:43:53 +0100 Subject: [PATCH 035/174] tpm: fix reference counting for struct tpm_chip commit 7e0438f83dc769465ee663bb5dcf8cc154940712 upstream. The following sequence of operations results in a refcount warning: 1. Open device /dev/tpmrm. 2. Remove module tpm_tis_spi. 3. Write a TPM command to the file descriptor opened at step 1. ------------[ cut here ]------------ WARNING: CPU: 3 PID: 1161 at lib/refcount.c:25 kobject_get+0xa0/0xa4 refcount_t: addition on 0; use-after-free. Modules linked in: tpm_tis_spi tpm_tis_core tpm mdio_bcm_unimac brcmfmac sha256_generic libsha256 sha256_arm hci_uart btbcm bluetooth cfg80211 vc4 brcmutil ecdh_generic ecc snd_soc_core crc32_arm_ce libaes raspberrypi_hwmon ac97_bus snd_pcm_dmaengine bcm2711_thermal snd_pcm snd_timer genet snd phy_generic soundcore [last unloaded: spi_bcm2835] CPU: 3 PID: 1161 Comm: hold_open Not tainted 5.10.0ls-main-dirty #2 Hardware name: BCM2711 [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0xc4/0xd8) [] (dump_stack) from [] (__warn+0x104/0x108) [] (__warn) from [] (warn_slowpath_fmt+0x74/0xb8) [] (warn_slowpath_fmt) from [] (kobject_get+0xa0/0xa4) [] (kobject_get) from [] (tpm_try_get_ops+0x14/0x54 [tpm]) [] (tpm_try_get_ops [tpm]) from [] (tpm_common_write+0x38/0x60 [tpm]) [] (tpm_common_write [tpm]) from [] (vfs_write+0xc4/0x3c0) [] (vfs_write) from [] (ksys_write+0x58/0xcc) [] (ksys_write) from [] (ret_fast_syscall+0x0/0x4c) Exception stack(0xc226bfa8 to 0xc226bff0) bfa0: 00000000 000105b4 00000003 beafe664 00000014 00000000 bfc0: 00000000 000105b4 000103f8 00000004 00000000 00000000 b6f9c000 beafe684 bfe0: 0000006c beafe648 0001056c b6eb6944 ---[ end trace d4b8409def9b8b1f ]--- The reason for this warning is the attempt to get the chip->dev reference in tpm_common_write() although the reference counter is already zero. Since commit 8979b02aaf1d ("tpm: Fix reference count to main device") the extra reference used to prevent a premature zero counter is never taken, because the required TPM_CHIP_FLAG_TPM2 flag is never set. Fix this by moving the TPM 2 character device handling from tpm_chip_alloc() to tpm_add_char_device() which is called at a later point in time when the flag has been set in case of TPM2. Commit fdc915f7f719 ("tpm: expose spaces via a device link /dev/tpmrm") already introduced function tpm_devs_release() to release the extra reference but did not implement the required put on chip->devs that results in the call of this function. Fix this by putting chip->devs in tpm_chip_unregister(). Finally move the new implementation for the TPM 2 handling into a new function to avoid multiple checks for the TPM_CHIP_FLAG_TPM2 flag in the good case and error cases. Cc: stable@vger.kernel.org Fixes: fdc915f7f719 ("tpm: expose spaces via a device link /dev/tpmrm") Fixes: 8979b02aaf1d ("tpm: Fix reference count to main device") Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Lino Sanfilippo Tested-by: Stefan Berger Reviewed-by: Jason Gunthorpe Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm-chip.c | 46 +++++-------------------- drivers/char/tpm/tpm.h | 2 ++ drivers/char/tpm/tpm2-space.c | 65 +++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 38 deletions(-) diff --git a/drivers/char/tpm/tpm-chip.c b/drivers/char/tpm/tpm-chip.c index b009e7479b70..783d65fc71f0 100644 --- a/drivers/char/tpm/tpm-chip.c +++ b/drivers/char/tpm/tpm-chip.c @@ -274,14 +274,6 @@ static void tpm_dev_release(struct device *dev) kfree(chip); } -static void tpm_devs_release(struct device *dev) -{ - struct tpm_chip *chip = container_of(dev, struct tpm_chip, devs); - - /* release the master device reference */ - put_device(&chip->dev); -} - /** * tpm_class_shutdown() - prepare the TPM device for loss of power. * @dev: device to which the chip is associated. @@ -344,7 +336,6 @@ struct tpm_chip *tpm_chip_alloc(struct device *pdev, chip->dev_num = rc; device_initialize(&chip->dev); - device_initialize(&chip->devs); chip->dev.class = tpm_class; chip->dev.class->shutdown_pre = tpm_class_shutdown; @@ -352,29 +343,12 @@ struct tpm_chip *tpm_chip_alloc(struct device *pdev, chip->dev.parent = pdev; chip->dev.groups = chip->groups; - chip->devs.parent = pdev; - chip->devs.class = tpmrm_class; - chip->devs.release = tpm_devs_release; - /* get extra reference on main device to hold on - * behalf of devs. This holds the chip structure - * while cdevs is in use. The corresponding put - * is in the tpm_devs_release (TPM2 only) - */ - if (chip->flags & TPM_CHIP_FLAG_TPM2) - get_device(&chip->dev); - if (chip->dev_num == 0) chip->dev.devt = MKDEV(MISC_MAJOR, TPM_MINOR); else chip->dev.devt = MKDEV(MAJOR(tpm_devt), chip->dev_num); - chip->devs.devt = - MKDEV(MAJOR(tpm_devt), chip->dev_num + TPM_NUM_DEVICES); - rc = dev_set_name(&chip->dev, "tpm%d", chip->dev_num); - if (rc) - goto out; - rc = dev_set_name(&chip->devs, "tpmrm%d", chip->dev_num); if (rc) goto out; @@ -382,9 +356,7 @@ struct tpm_chip *tpm_chip_alloc(struct device *pdev, chip->flags |= TPM_CHIP_FLAG_VIRTUAL; cdev_init(&chip->cdev, &tpm_fops); - cdev_init(&chip->cdevs, &tpmrm_fops); chip->cdev.owner = THIS_MODULE; - chip->cdevs.owner = THIS_MODULE; rc = tpm2_init_space(&chip->work_space, TPM2_SPACE_BUFFER_SIZE); if (rc) { @@ -396,7 +368,6 @@ struct tpm_chip *tpm_chip_alloc(struct device *pdev, return chip; out: - put_device(&chip->devs); put_device(&chip->dev); return ERR_PTR(rc); } @@ -445,14 +416,9 @@ static int tpm_add_char_device(struct tpm_chip *chip) } if (chip->flags & TPM_CHIP_FLAG_TPM2 && !tpm_is_firmware_upgrade(chip)) { - rc = cdev_device_add(&chip->cdevs, &chip->devs); - if (rc) { - dev_err(&chip->devs, - "unable to cdev_device_add() %s, major %d, minor %d, err=%d\n", - dev_name(&chip->devs), MAJOR(chip->devs.devt), - MINOR(chip->devs.devt), rc); - return rc; - } + rc = tpm_devs_add(chip); + if (rc) + goto err_del_cdev; } /* Make the chip available. */ @@ -460,6 +426,10 @@ static int tpm_add_char_device(struct tpm_chip *chip) idr_replace(&dev_nums_idr, chip, chip->dev_num); mutex_unlock(&idr_lock); + return 0; + +err_del_cdev: + cdev_device_del(&chip->cdev, &chip->dev); return rc; } @@ -654,7 +624,7 @@ void tpm_chip_unregister(struct tpm_chip *chip) hwrng_unregister(&chip->hwrng); tpm_bios_log_teardown(chip); if (chip->flags & TPM_CHIP_FLAG_TPM2 && !tpm_is_firmware_upgrade(chip)) - cdev_device_del(&chip->cdevs, &chip->devs); + tpm_devs_remove(chip); tpm_del_char_device(chip); } EXPORT_SYMBOL_GPL(tpm_chip_unregister); diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 283f78211c3a..2163c6ee0d36 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -234,6 +234,8 @@ int tpm2_prepare_space(struct tpm_chip *chip, struct tpm_space *space, u8 *cmd, size_t cmdsiz); int tpm2_commit_space(struct tpm_chip *chip, struct tpm_space *space, void *buf, size_t *bufsiz); +int tpm_devs_add(struct tpm_chip *chip); +void tpm_devs_remove(struct tpm_chip *chip); void tpm_bios_log_setup(struct tpm_chip *chip); void tpm_bios_log_teardown(struct tpm_chip *chip); diff --git a/drivers/char/tpm/tpm2-space.c b/drivers/char/tpm/tpm2-space.c index 97e916856cf3..265ec72b1d81 100644 --- a/drivers/char/tpm/tpm2-space.c +++ b/drivers/char/tpm/tpm2-space.c @@ -574,3 +574,68 @@ out: dev_err(&chip->dev, "%s: error %d\n", __func__, rc); return rc; } + +/* + * Put the reference to the main device. + */ +static void tpm_devs_release(struct device *dev) +{ + struct tpm_chip *chip = container_of(dev, struct tpm_chip, devs); + + /* release the master device reference */ + put_device(&chip->dev); +} + +/* + * Remove the device file for exposed TPM spaces and release the device + * reference. This may also release the reference to the master device. + */ +void tpm_devs_remove(struct tpm_chip *chip) +{ + cdev_device_del(&chip->cdevs, &chip->devs); + put_device(&chip->devs); +} + +/* + * Add a device file to expose TPM spaces. Also take a reference to the + * main device. + */ +int tpm_devs_add(struct tpm_chip *chip) +{ + int rc; + + device_initialize(&chip->devs); + chip->devs.parent = chip->dev.parent; + chip->devs.class = tpmrm_class; + + /* + * Get extra reference on main device to hold on behalf of devs. + * This holds the chip structure while cdevs is in use. The + * corresponding put is in the tpm_devs_release. + */ + get_device(&chip->dev); + chip->devs.release = tpm_devs_release; + chip->devs.devt = MKDEV(MAJOR(tpm_devt), chip->dev_num + TPM_NUM_DEVICES); + cdev_init(&chip->cdevs, &tpmrm_fops); + chip->cdevs.owner = THIS_MODULE; + + rc = dev_set_name(&chip->devs, "tpmrm%d", chip->dev_num); + if (rc) + goto err_put_devs; + + rc = cdev_device_add(&chip->cdevs, &chip->devs); + if (rc) { + dev_err(&chip->devs, + "unable to cdev_device_add() %s, major %d, minor %d, err=%d\n", + dev_name(&chip->devs), MAJOR(chip->devs.devt), + MINOR(chip->devs.devt), rc); + goto err_put_devs; + } + + return 0; + +err_put_devs: + put_device(&chip->devs); + + return rc; +} From ba84f9a48366dcc3cdef978599433efe101dd5bd Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 7 Mar 2022 15:58:03 -0500 Subject: [PATCH 036/174] tpm: use try_get_ops() in tpm-space.c commit fb5abce6b2bb5cb3d628aaa63fa821da8c4600f9 upstream. As part of the series conversion to remove nested TPM operations: https://lore.kernel.org/all/20190205224723.19671-1-jarkko.sakkinen@linux.intel.com/ exposure of the chip->tpm_mutex was removed from much of the upper level code. In this conversion, tpm2_del_space() was missed. This didn't matter much because it's usually called closely after a converted operation, so there's only a very tiny race window where the chip can be removed before the space flushing is done which causes a NULL deref on the mutex. However, there are reports of this window being hit in practice, so fix this by converting tpm2_del_space() to use tpm_try_get_ops(), which performs all the teardown checks before acquring the mutex. Cc: stable@vger.kernel.org # 5.4.x Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm2-space.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/char/tpm/tpm2-space.c b/drivers/char/tpm/tpm2-space.c index 265ec72b1d81..ffb35f0154c1 100644 --- a/drivers/char/tpm/tpm2-space.c +++ b/drivers/char/tpm/tpm2-space.c @@ -58,12 +58,12 @@ int tpm2_init_space(struct tpm_space *space, unsigned int buf_size) void tpm2_del_space(struct tpm_chip *chip, struct tpm_space *space) { - mutex_lock(&chip->tpm_mutex); - if (!tpm_chip_start(chip)) { + + if (tpm_try_get_ops(chip) == 0) { tpm2_flush_sessions(chip, space); - tpm_chip_stop(chip); + tpm_put_ops(chip); } - mutex_unlock(&chip->tpm_mutex); + kfree(space->context_buf); kfree(space->session_buf); } From bed07e7ecc73f5c043a8bc1f519e46d650ff9e22 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 25 Jan 2022 00:40:46 +0000 Subject: [PATCH 037/174] wcn36xx: Differentiate wcn3660 from wcn3620 commit 98d504a82cc75840bec8e3c6ae0e4f411921962b upstream. The spread of capability between the three WiFi silicon parts wcn36xx supports is: wcn3620 - 802.11 a/b/g wcn3660 - 802.11 a/b/g/n wcn3680 - 802.11 a/b/g/n/ac We currently treat wcn3660 as wcn3620 thus limiting it to 2GHz channels. Fix this regression by ensuring we differentiate between all three parts. Fixes: 8490987bdb9a ("wcn36xx: Hook and identify RF_IRIS_WCN3680") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Reviewed-by: Loic Poulain Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220125004046.4058284-1-bryan.odonoghue@linaro.org Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/ath/wcn36xx/main.c | 3 +++ drivers/net/wireless/ath/wcn36xx/wcn36xx.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/net/wireless/ath/wcn36xx/main.c b/drivers/net/wireless/ath/wcn36xx/main.c index 9575d7373bf2..ac2813ed851c 100644 --- a/drivers/net/wireless/ath/wcn36xx/main.c +++ b/drivers/net/wireless/ath/wcn36xx/main.c @@ -1513,6 +1513,9 @@ static int wcn36xx_platform_get_resources(struct wcn36xx *wcn, if (iris_node) { if (of_device_is_compatible(iris_node, "qcom,wcn3620")) wcn->rf_id = RF_IRIS_WCN3620; + if (of_device_is_compatible(iris_node, "qcom,wcn3660") || + of_device_is_compatible(iris_node, "qcom,wcn3660b")) + wcn->rf_id = RF_IRIS_WCN3660; if (of_device_is_compatible(iris_node, "qcom,wcn3680")) wcn->rf_id = RF_IRIS_WCN3680; of_node_put(iris_node); diff --git a/drivers/net/wireless/ath/wcn36xx/wcn36xx.h b/drivers/net/wireless/ath/wcn36xx/wcn36xx.h index fbd0558c2c19..5d3f8f56e568 100644 --- a/drivers/net/wireless/ath/wcn36xx/wcn36xx.h +++ b/drivers/net/wireless/ath/wcn36xx/wcn36xx.h @@ -97,6 +97,7 @@ enum wcn36xx_ampdu_state { #define RF_UNKNOWN 0x0000 #define RF_IRIS_WCN3620 0x3620 +#define RF_IRIS_WCN3660 0x3660 #define RF_IRIS_WCN3680 0x3680 static inline void buff_to_be(u32 *buf, size_t len) From b7509a4e81b516493cf601294268db07cad7659b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 15 Feb 2022 17:59:41 +0100 Subject: [PATCH 038/174] m68k: fix access_ok for coldfire commit 26509034bef198525d5936c116cbd0c3fa491c0b upstream. While most m68k platforms use separate address spaces for user and kernel space, at least coldfire does not, and the other ones have a TASK_SIZE that is less than the entire 4GB address range. Using the default implementation of __access_ok() stops coldfire user space from trivially accessing kernel memory. Reviewed-by: Christoph Hellwig Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- arch/m68k/include/asm/uaccess.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h index ba670523885c..60b786eb2254 100644 --- a/arch/m68k/include/asm/uaccess.h +++ b/arch/m68k/include/asm/uaccess.h @@ -12,14 +12,17 @@ #include /* We let the MMU do all checking */ -static inline int access_ok(const void __user *addr, +static inline int access_ok(const void __user *ptr, unsigned long size) { - /* - * XXX: for !CONFIG_CPU_HAS_ADDRESS_SPACES this really needs to check - * for TASK_SIZE! - */ - return 1; + unsigned long limit = TASK_SIZE; + unsigned long addr = (unsigned long)ptr; + + if (IS_ENABLED(CONFIG_CPU_HAS_ADDRESS_SPACES) || + !IS_ENABLED(CONFIG_MMU)) + return 1; + + return (size <= limit) && (addr <= (limit - size)); } /* From 8f8a8f3ab3a64752b97182f696a0094accd8b2d9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 14 Feb 2022 15:48:14 +0100 Subject: [PATCH 039/174] nds32: fix access_ok() checks in get/put_user commit 8926d88ced46700bf6117ceaf391480b943ea9f4 upstream. The get_user()/put_user() functions are meant to check for access_ok(), while the __get_user()/__put_user() functions don't. This broke in 4.19 for nds32, when it gained an extraneous check in __get_user(), but lost the check it needs in __put_user(). Fixes: 487913ab18c2 ("nds32: Extract the checking and getting pointer to a macro") Cc: stable@vger.kernel.org @ v4.19+ Reviewed-by: Christoph Hellwig Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- arch/nds32/include/asm/uaccess.h | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h index d4cbf069dc22..37a40981deb3 100644 --- a/arch/nds32/include/asm/uaccess.h +++ b/arch/nds32/include/asm/uaccess.h @@ -70,9 +70,7 @@ static inline void set_fs(mm_segment_t fs) * versions are void (ie, don't return a value as such). */ -#define get_user __get_user \ - -#define __get_user(x, ptr) \ +#define get_user(x, ptr) \ ({ \ long __gu_err = 0; \ __get_user_check((x), (ptr), __gu_err); \ @@ -85,6 +83,14 @@ static inline void set_fs(mm_segment_t fs) (void)0; \ }) +#define __get_user(x, ptr) \ +({ \ + long __gu_err = 0; \ + const __typeof__(*(ptr)) __user *__p = (ptr); \ + __get_user_err((x), __p, (__gu_err)); \ + __gu_err; \ +}) + #define __get_user_check(x, ptr, err) \ ({ \ const __typeof__(*(ptr)) __user *__p = (ptr); \ @@ -165,12 +171,18 @@ do { \ : "r"(addr), "i"(-EFAULT) \ : "cc") -#define put_user __put_user \ +#define put_user(x, ptr) \ +({ \ + long __pu_err = 0; \ + __put_user_check((x), (ptr), __pu_err); \ + __pu_err; \ +}) #define __put_user(x, ptr) \ ({ \ long __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + __put_user_err((x), __p, __pu_err); \ __pu_err; \ }) From dc9363ece2048e64df4bd8dc7c71734cc47dcecb Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 8 Mar 2022 10:48:44 -0800 Subject: [PATCH 040/174] drm/msm/gpu: Fix crash on devices without devfreq support (v2) commit 05afd57f4d34602a652fdaf58e0a2756b3c20fd4 upstream. Avoid going down devfreq paths on devices where devfreq is not initialized. v2: Change has_devfreq() logic [Dmitry] Reported-by: Linux Kernel Functional Testing Reported-by: Anders Roxell Signed-off-by: Rob Clark Fixes: 6aa89ae1fb04 ("drm/msm/gpu: Cancel idle/boost work on suspend") Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220308184844.1121029-1-robdclark@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 ++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 9bf319be11f6..12641616acd3 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -83,6 +83,12 @@ static struct devfreq_dev_profile msm_devfreq_profile = { static void msm_devfreq_boost_work(struct kthread_work *work); static void msm_devfreq_idle_work(struct kthread_work *work); +static bool has_devfreq(struct msm_gpu *gpu) +{ + struct msm_gpu_devfreq *df = &gpu->devfreq; + return !!df->devfreq; +} + void msm_devfreq_init(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; @@ -149,6 +155,9 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; + if (!has_devfreq(gpu)) + return; + devfreq_cooling_unregister(gpu->cooling); dev_pm_qos_remove_request(&df->boost_freq); dev_pm_qos_remove_request(&df->idle_freq); @@ -156,16 +165,24 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu) void msm_devfreq_resume(struct msm_gpu *gpu) { - gpu->devfreq.busy_cycles = 0; - gpu->devfreq.time = ktime_get(); + struct msm_gpu_devfreq *df = &gpu->devfreq; - devfreq_resume_device(gpu->devfreq.devfreq); + if (!has_devfreq(gpu)) + return; + + df->busy_cycles = 0; + df->time = ktime_get(); + + devfreq_resume_device(df->devfreq); } void msm_devfreq_suspend(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; + if (!has_devfreq(gpu)) + return; + devfreq_suspend_device(df->devfreq); cancel_idle_work(df); @@ -185,6 +202,9 @@ void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) struct msm_gpu_devfreq *df = &gpu->devfreq; uint64_t freq; + if (!has_devfreq(gpu)) + return; + freq = get_freq(gpu); freq *= factor; @@ -207,7 +227,7 @@ void msm_devfreq_active(struct msm_gpu *gpu) struct devfreq_dev_status status; unsigned int idle_time; - if (!df->devfreq) + if (!has_devfreq(gpu)) return; /* @@ -253,7 +273,7 @@ void msm_devfreq_idle(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; - if (!df->devfreq) + if (!has_devfreq(gpu)) return; msm_hrtimer_queue_work(&df->idle_work, ms_to_ktime(1), From d5ac598705e1eb40e952cf7c8fe8b48c8dea897e Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 24 Mar 2022 20:58:27 -0700 Subject: [PATCH 041/174] llc: only change llc->dev when bind() succeeds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 2d327a79ee176930dc72c131a970c891d367c1dc upstream. My latest patch, attempting to fix the refcount leak in a minimal way turned out to add a new bug. Whenever the bind operation fails before we attempt to grab a reference count on a device, we might release the device refcount of a prior successful bind() operation. syzbot was not happy about this [1]. Note to stable teams: Make sure commit b37a46683739 ("netdevice: add the case if dev is NULL") is already present in your trees. [1] general protection fault, probably for non-canonical address 0xdffffc0000000070: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000380-0x0000000000000387] CPU: 1 PID: 3590 Comm: syz-executor361 Tainted: G W 5.17.0-syzkaller-04796-g169e77764adc #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:llc_ui_connect+0x400/0xcb0 net/llc/af_llc.c:500 Code: 80 3c 02 00 0f 85 fc 07 00 00 4c 8b a5 38 05 00 00 48 b8 00 00 00 00 00 fc ff df 49 8d bc 24 80 03 00 00 48 89 fa 48 c1 ea 03 <80> 3c 02 00 0f 85 a9 07 00 00 49 8b b4 24 80 03 00 00 4c 89 f2 48 RSP: 0018:ffffc900038cfcc0 EFLAGS: 00010202 RAX: dffffc0000000000 RBX: ffff8880756eb600 RCX: 0000000000000000 RDX: 0000000000000070 RSI: ffffc900038cfe3e RDI: 0000000000000380 RBP: ffff888015ee5000 R08: 0000000000000001 R09: ffff888015ee5535 R10: ffffed1002bdcaa6 R11: 0000000000000000 R12: 0000000000000000 R13: ffffc900038cfe37 R14: ffffc900038cfe38 R15: ffff888015ee5012 FS: 0000555555acd300(0000) GS:ffff8880b9d00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000020000280 CR3: 0000000077db6000 CR4: 00000000003506e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __sys_connect_file+0x155/0x1a0 net/socket.c:1900 __sys_connect+0x161/0x190 net/socket.c:1917 __do_sys_connect net/socket.c:1927 [inline] __se_sys_connect net/socket.c:1924 [inline] __x64_sys_connect+0x6f/0xb0 net/socket.c:1924 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f016acb90b9 Code: 28 c3 e8 2a 14 00 00 66 2e 0f 1f 84 00 00 00 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007ffd417947f8 EFLAGS: 00000246 ORIG_RAX: 000000000000002a RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f016acb90b9 RDX: 0000000000000010 RSI: 0000000020000140 RDI: 0000000000000003 RBP: 00007f016ac7d0a0 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f016ac7d130 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 Modules linked in: ---[ end trace 0000000000000000 ]--- RIP: 0010:llc_ui_connect+0x400/0xcb0 net/llc/af_llc.c:500 Fixes: 764f4eb6846f ("llc: fix netdevice reference leaks in llc_ui_bind()") Signed-off-by: Eric Dumazet Reported-by: syzbot Cc: 赵子轩 Cc: Stoyan Manolov Link: https://lore.kernel.org/r/20220325035827.360418-1-eric.dumazet@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/llc/af_llc.c | 59 ++++++++++++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/net/llc/af_llc.c b/net/llc/af_llc.c index c86256064743..7f555d2e5357 100644 --- a/net/llc/af_llc.c +++ b/net/llc/af_llc.c @@ -275,6 +275,7 @@ static int llc_ui_autobind(struct socket *sock, struct sockaddr_llc *addr) { struct sock *sk = sock->sk; struct llc_sock *llc = llc_sk(sk); + struct net_device *dev = NULL; struct llc_sap *sap; int rc = -EINVAL; @@ -286,16 +287,15 @@ static int llc_ui_autobind(struct socket *sock, struct sockaddr_llc *addr) goto out; rc = -ENODEV; if (sk->sk_bound_dev_if) { - llc->dev = dev_get_by_index(&init_net, sk->sk_bound_dev_if); - if (llc->dev && addr->sllc_arphrd != llc->dev->type) { - dev_put(llc->dev); - llc->dev = NULL; + dev = dev_get_by_index(&init_net, sk->sk_bound_dev_if); + if (dev && addr->sllc_arphrd != dev->type) { + dev_put(dev); + dev = NULL; } } else - llc->dev = dev_getfirstbyhwtype(&init_net, addr->sllc_arphrd); - if (!llc->dev) + dev = dev_getfirstbyhwtype(&init_net, addr->sllc_arphrd); + if (!dev) goto out; - netdev_tracker_alloc(llc->dev, &llc->dev_tracker, GFP_KERNEL); rc = -EUSERS; llc->laddr.lsap = llc_ui_autoport(); if (!llc->laddr.lsap) @@ -304,6 +304,12 @@ static int llc_ui_autobind(struct socket *sock, struct sockaddr_llc *addr) sap = llc_sap_open(llc->laddr.lsap, NULL); if (!sap) goto out; + + /* Note: We do not expect errors from this point. */ + llc->dev = dev; + netdev_tracker_alloc(llc->dev, &llc->dev_tracker, GFP_KERNEL); + dev = NULL; + memcpy(llc->laddr.mac, llc->dev->dev_addr, IFHWADDRLEN); memcpy(&llc->addr, addr, sizeof(llc->addr)); /* assign new connection to its SAP */ @@ -311,10 +317,7 @@ static int llc_ui_autobind(struct socket *sock, struct sockaddr_llc *addr) sock_reset_flag(sk, SOCK_ZAPPED); rc = 0; out: - if (rc) { - dev_put_track(llc->dev, &llc->dev_tracker); - llc->dev = NULL; - } + dev_put(dev); return rc; } @@ -337,6 +340,7 @@ static int llc_ui_bind(struct socket *sock, struct sockaddr *uaddr, int addrlen) struct sockaddr_llc *addr = (struct sockaddr_llc *)uaddr; struct sock *sk = sock->sk; struct llc_sock *llc = llc_sk(sk); + struct net_device *dev = NULL; struct llc_sap *sap; int rc = -EINVAL; @@ -352,25 +356,27 @@ static int llc_ui_bind(struct socket *sock, struct sockaddr *uaddr, int addrlen) rc = -ENODEV; rcu_read_lock(); if (sk->sk_bound_dev_if) { - llc->dev = dev_get_by_index_rcu(&init_net, sk->sk_bound_dev_if); - if (llc->dev) { + dev = dev_get_by_index_rcu(&init_net, sk->sk_bound_dev_if); + if (dev) { if (is_zero_ether_addr(addr->sllc_mac)) - memcpy(addr->sllc_mac, llc->dev->dev_addr, + memcpy(addr->sllc_mac, dev->dev_addr, IFHWADDRLEN); - if (addr->sllc_arphrd != llc->dev->type || + if (addr->sllc_arphrd != dev->type || !ether_addr_equal(addr->sllc_mac, - llc->dev->dev_addr)) { + dev->dev_addr)) { rc = -EINVAL; - llc->dev = NULL; + dev = NULL; } } - } else - llc->dev = dev_getbyhwaddr_rcu(&init_net, addr->sllc_arphrd, + } else { + dev = dev_getbyhwaddr_rcu(&init_net, addr->sllc_arphrd, addr->sllc_mac); - dev_hold_track(llc->dev, &llc->dev_tracker, GFP_ATOMIC); + } + dev_hold(dev); rcu_read_unlock(); - if (!llc->dev) + if (!dev) goto out; + if (!addr->sllc_sap) { rc = -EUSERS; addr->sllc_sap = llc_ui_autoport(); @@ -402,6 +408,12 @@ static int llc_ui_bind(struct socket *sock, struct sockaddr *uaddr, int addrlen) goto out_put; } } + + /* Note: We do not expect errors from this point. */ + llc->dev = dev; + netdev_tracker_alloc(llc->dev, &llc->dev_tracker, GFP_KERNEL); + dev = NULL; + llc->laddr.lsap = addr->sllc_sap; memcpy(llc->laddr.mac, addr->sllc_mac, IFHWADDRLEN); memcpy(&llc->addr, addr, sizeof(llc->addr)); @@ -412,10 +424,7 @@ static int llc_ui_bind(struct socket *sock, struct sockaddr *uaddr, int addrlen) out_put: llc_sap_put(sap); out: - if (rc) { - dev_put_track(llc->dev, &llc->dev_tracker); - llc->dev = NULL; - } + dev_put(dev); release_sock(sk); return rc; } From 59db887d13b3a4df2713c2a866fa2767e0dea569 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 28 Mar 2022 10:03:22 +0200 Subject: [PATCH 042/174] Linux 5.17.1 Link: https://lore.kernel.org/r/20220325150420.245733653@linuxfoundation.org Tested-by: Ronald Warsow Tested-by: Shuah Khan Tested-by: Fox Chen Tested-by: Rudi Heitbaum Tested-by: Florian Fainelli Reviewed-by: Dmitry Baryshkov Tested-by: Bagas Sanjaya Tested-by: Fenil Jain Tested-by: Ron Economos Tested-by: Guenter Roeck Tested-by: Justin M. Forbes Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7214f075e1f0..34f9f5a9457a 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 17 -SUBLEVEL = 0 +SUBLEVEL = 1 EXTRAVERSION = NAME = Superb Owl From da4fc9a4019e9a25b028a372f2bffa434276aa50 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 11 Apr 2021 23:04:31 +0200 Subject: [PATCH 043/174] leds: ledtrig-pattern: Use last_repeat when applying hw pattern `last_repeat` holds the actual value requested by the user whereas `repeat` is a software iteration variable that is unused in hardware patterns. Furthermore `last_repeat` is the field returned to the user when reading the `repeat` sysfs property. This field is initialized to `-1` which is - together with `1` - the only valid value in the upcoming Qualcomm LPG driver. It is thus unexpected when `repeat` with an initialization value of `0` is passed into the the driver, when the sysfs property clearly presents a value of `-1`. Signed-off-by: Marijn Suijten --- drivers/leds/trigger/ledtrig-pattern.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/leds/trigger/ledtrig-pattern.c b/drivers/leds/trigger/ledtrig-pattern.c index 43a265dc4696..a11d68143757 100644 --- a/drivers/leds/trigger/ledtrig-pattern.c +++ b/drivers/leds/trigger/ledtrig-pattern.c @@ -126,7 +126,8 @@ static int pattern_trig_start_pattern(struct led_classdev *led_cdev) if (data->is_hw_pattern) { return led_cdev->pattern_set(led_cdev, data->patterns, - data->npatterns, data->repeat); + data->npatterns, + data->last_repeat); } /* At least 2 tuples for software pattern. */ From 8f64838ebbf7c79fec7ab20ce584dcbd4e88c5ce Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:12 -0700 Subject: [PATCH 044/174] dt-bindings: leds: Add Qualcomm Light Pulse Generator binding This adds the binding document describing the three hardware blocks related to the Light Pulse Generator found in a wide range of Qualcomm PMICs. Signed-off-by: Bjorn Andersson --- .../bindings/leds/leds-qcom-lpg.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml diff --git a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml new file mode 100644 index 000000000000..2998598e8785 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Light Pulse Generator + +maintainers: + - Bjorn Andersson + +description: > + The Qualcomm Light Pulse Generator consists of three different hardware blocks; + a ramp generator with lookup table, the light pulse generator and a three + channel current sink. These blocks are found in a wide range of Qualcomm PMICs. + +properties: + compatible: + enum: + - qcom,pm8150b-lpg + - qcom,pm8150l-lpg + - qcom,pm8916-pwm + - qcom,pm8941-lpg + - qcom,pm8994-lpg + - qcom,pmi8994-lpg + - qcom,pmi8998-lpg + + "#pwm-cells": + const: 2 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + power-source used to drive the output, as defined in the datasheet. + Should be specified if the TRILED block is present + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + A list of integer pairs, where each pair represent the dtest line the + particular channel should be connected to and the flags denoting how the + value should be outputed, as defined in the datasheet. The number of + pairs should be the same as the number of channels. + + multi-led: + type: object + $ref: leds-class-multicolor.yaml# + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + +patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + + properties: + reg: true + + required: + - reg + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + qcom,dtest = <0 0 + 0 0 + 0 0 + 4 1>; + + led@1 { + reg = <1>; + label = "green:user1"; + }; + + led@2 { + reg = <2>; + label = "green:user0"; + default-state = "on"; + }; + + led@3 { + reg = <3>; + label = "green:user2"; + }; + + led@4 { + reg = <4>; + label = "green:user3"; + }; + }; + - | + #include + + lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + multi-led { + color = ; + label = "rgb:notification"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; + }; + - | + lpg { + compatible = "qcom,pm8916-pwm"; + #pwm-cells = <2>; + }; +... From c1c2f1d8429704f230c5b1c96af1e24eae72dca9 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:13 -0700 Subject: [PATCH 045/174] leds: Add driver for Qualcomm LPG The Light Pulse Generator (LPG) is a PWM-block found in a wide range of PMICs from Qualcomm. It can operate on fixed parameters or based on a lookup-table, altering the duty cycle over time - which provides the means for e.g. hardware assisted transitions of LED brightness. Signed-off-by: Bjorn Andersson --- drivers/leds/Kconfig | 3 + drivers/leds/Makefile | 3 + drivers/leds/rgb/leds-qcom-lpg.c | 1286 ++++++++++++++++++++++++++++++ 3 files changed, 1292 insertions(+) create mode 100644 drivers/leds/rgb/leds-qcom-lpg.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 6090e647daee..a49979f41eee 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -869,6 +869,9 @@ source "drivers/leds/blink/Kconfig" comment "Flash and Torch LED drivers" source "drivers/leds/flash/Kconfig" +comment "RGB LED drivers" +source "drivers/leds/rgb/Kconfig" + comment "LED Triggers" source "drivers/leds/trigger/Kconfig" diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index e58ecb36360f..4fd2f92cd198 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -99,6 +99,9 @@ obj-$(CONFIG_LEDS_USER) += uleds.o # Flash and Torch LED Drivers obj-$(CONFIG_LEDS_CLASS_FLASH) += flash/ +# RGB LED Drivers +obj-$(CONFIG_LEDS_CLASS_MULTICOLOR) += rgb/ + # LED Triggers obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c new file mode 100644 index 000000000000..c68233b43c2c --- /dev/null +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -0,0 +1,1286 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021 Linaro Ltd + * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPG_PATTERN_CONFIG_REG 0x40 +#define LPG_SIZE_CLK_REG 0x41 +#define LPG_PREDIV_CLK_REG 0x42 +#define PWM_TYPE_CONFIG_REG 0x43 +#define PWM_VALUE_REG 0x44 +#define PWM_ENABLE_CONTROL_REG 0x46 +#define PWM_SYNC_REG 0x47 +#define LPG_RAMP_DURATION_REG 0x50 +#define LPG_HI_PAUSE_REG 0x52 +#define LPG_LO_PAUSE_REG 0x54 +#define LPG_HI_IDX_REG 0x56 +#define LPG_LO_IDX_REG 0x57 +#define PWM_SEC_ACCESS_REG 0xd0 +#define PWM_DTEST_REG(x) (0xe2 + (x) - 1) + +#define TRI_LED_SRC_SEL 0x45 +#define TRI_LED_EN_CTL 0x46 +#define TRI_LED_ATC_CTL 0x47 + +#define LPG_LUT_REG(x) (0x40 + (x) * 2) +#define RAMP_CONTROL_REG 0xc8 + +struct lpg_channel; +struct lpg_data; + +/** + * struct lpg - LPG device context + * @dev: struct device for LPG device + * @map: regmap for register access + * @pwm: PWM-chip object, if operating in PWM mode + * @lut_base: base address of the LUT block (optional) + * @lut_size: number of entries in the LUT block + * @lut_bitmap: allocation bitmap for LUT entries + * @triled_base: base address of the TRILED block (optional) + * @triled_src: power-source for the TRILED + * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register + * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register + * @channels: list of PWM channels + * @num_channels: number of @channels + */ +struct lpg { + struct device *dev; + struct regmap *map; + + struct pwm_chip pwm; + + const struct lpg_data *data; + + u32 lut_base; + u32 lut_size; + unsigned long *lut_bitmap; + + u32 triled_base; + u32 triled_src; + bool triled_has_atc_ctl; + bool triled_has_src_sel; + + struct lpg_channel *channels; + unsigned int num_channels; +}; + +/** + * struct lpg_channel - per channel data + * @lpg: reference to parent lpg + * @base: base address of the PWM channel + * @triled_mask: mask in TRILED to enable this channel + * @lut_mask: mask in LUT to start pattern generator for this channel + * @in_use: channel is exposed to LED framework + * @color: color of the LED attached to this channel + * @dtest_line: DTEST line for output, or 0 if disabled + * @dtest_value: DTEST line configuration + * @pwm_value: duty (in microseconds) of the generated pulses, overridden by LUT + * @enabled: output enabled? + * @period_us: period (in microseconds) of the generated pulses + * @pwm_size: resolution of the @pwm_value, 6 or 9 bits + * @clk: base frequency of the clock generator + * @pre_div: divider of @clk + * @pre_div_exp: exponential divider of @clk + * @ramp_enabled: duty cycle is driven by iterating over lookup table + * @ramp_ping_pong: reverse through pattern, rather than wrapping to start + * @ramp_oneshot: perform only a single pass over the pattern + * @ramp_reverse: iterate over pattern backwards + * @ramp_tick_ms: length (in milliseconds) of one step in the pattern + * @ramp_lo_pause_ms: pause (in milliseconds) before iterating over pattern + * @ramp_hi_pause_ms: pause (in milliseconds) after iterating over pattern + * @pattern_lo_idx: start index of associated pattern + * @pattern_hi_idx: last index of associated pattern + */ +struct lpg_channel { + struct lpg *lpg; + + u32 base; + unsigned int triled_mask; + unsigned int lut_mask; + + bool in_use; + + int color; + + u32 dtest_line; + u32 dtest_value; + + u16 pwm_value; + bool enabled; + + unsigned int period_us; + unsigned int pwm_size; + unsigned int clk; + unsigned int pre_div; + unsigned int pre_div_exp; + + bool ramp_enabled; + bool ramp_ping_pong; + bool ramp_oneshot; + bool ramp_reverse; + unsigned long ramp_tick_ms; + unsigned long ramp_lo_pause_ms; + unsigned long ramp_hi_pause_ms; + + unsigned int pattern_lo_idx; + unsigned int pattern_hi_idx; +}; + +/** + * struct lpg_led - logical LED object + * @lpg: lpg context reference + * @cdev: LED class device + * @mcdev: Multicolor LED class device + * @num_channels: number of @channels + * @channels: list of channels associated with the LED + */ +struct lpg_led { + struct lpg *lpg; + + struct led_classdev cdev; + struct led_classdev_mc mcdev; + + unsigned int num_channels; + struct lpg_channel *channels[]; +}; + +/** + * struct lpg_channel_data - per channel initialization data + * @base: base address for PWM channel registers + * @triled_mask: bitmask for controlling this channel in TRILED + */ +struct lpg_channel_data { + unsigned int base; + u8 triled_mask; +}; + +/** + * struct lpg_data - initialization data + * @lut_base: base address of LUT block + * @lut_size: number of entries in LUT + * @triled_base: base address of TRILED + * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register + * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register + * @pwm_9bit_mask: bitmask for switching from 6bit to 9bit pwm + * @num_channels: number of channels in LPG + * @channels: list of channel initialization data + */ +struct lpg_data { + unsigned int lut_base; + unsigned int lut_size; + unsigned int triled_base; + bool triled_has_atc_ctl; + bool triled_has_src_sel; + unsigned int pwm_9bit_mask; + int num_channels; + struct lpg_channel_data *channels; +}; + +static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable) +{ + /* Skip if we don't have a triled block */ + if (!lpg->triled_base) + return 0; + + return regmap_update_bits(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, + mask, enable); +} + +static int lpg_lut_store(struct lpg *lpg, struct led_pattern *pattern, + size_t len, unsigned int *lo_idx, unsigned int *hi_idx) +{ + unsigned int idx; + u16 val; + int i; + + /* Hardware does not behave when LO_IDX == HI_IDX */ + if (len == 1) + return -EINVAL; + + idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, + 0, len, 0); + if (idx >= lpg->lut_size) + return -ENOMEM; + + for (i = 0; i < len; i++) { + val = pattern[i].brightness; + + regmap_bulk_write(lpg->map, lpg->lut_base + LPG_LUT_REG(idx + i), &val, 1); + } + + bitmap_set(lpg->lut_bitmap, idx, len); + + *lo_idx = idx; + *hi_idx = idx + len - 1; + + return 0; +} + +static void lpg_lut_free(struct lpg *lpg, unsigned int lo_idx, unsigned int hi_idx) +{ + int len; + + if (lo_idx == hi_idx) + return; + + len = hi_idx - lo_idx + 1; + bitmap_clear(lpg->lut_bitmap, lo_idx, len); +} + +static int lpg_lut_sync(struct lpg *lpg, unsigned int mask) +{ + return regmap_write(lpg->map, lpg->lut_base + RAMP_CONTROL_REG, mask); +} + +#define NUM_PWM_PREDIV 4 +#define NUM_PWM_CLK 3 +#define NUM_EXP 7 + +static const unsigned int lpg_clk_table[NUM_PWM_PREDIV][NUM_PWM_CLK] = { + { + 1 * (NSEC_PER_SEC / 1024), + 1 * (NSEC_PER_SEC / 32768), + 1 * (NSEC_PER_SEC / 19200000), + }, + { + 3 * (NSEC_PER_SEC / 1024), + 3 * (NSEC_PER_SEC / 32768), + 3 * (NSEC_PER_SEC / 19200000), + }, + { + 5 * (NSEC_PER_SEC / 1024), + 5 * (NSEC_PER_SEC / 32768), + 5 * (NSEC_PER_SEC / 19200000), + }, + { + 6 * (NSEC_PER_SEC / 1024), + 6 * (NSEC_PER_SEC / 32768), + 6 * (NSEC_PER_SEC / 19200000), + }, +}; + +/* + * PWM Frequency = Clock Frequency / (N * T) + * or + * PWM Period = Clock Period * (N * T) + * where + * N = 2^9 or 2^6 for 9-bit or 6-bit PWM size + * T = Pre-divide * 2^m, where m = 0..7 (exponent) + * + * This is the formula to figure out m for the best pre-divide and clock: + * (PWM Period / N) = (Pre-divide * Clock Period) * 2^m + */ +static void lpg_calc_freq(struct lpg_channel *chan, unsigned int period_us) +{ + int n, m, clk, div; + int best_m, best_div, best_clk; + unsigned int last_err, cur_err, min_err; + unsigned int tmp_p, period_n; + + if (period_us == chan->period_us) + return; + + /* PWM Period / N */ + if (period_us < UINT_MAX / NSEC_PER_USEC) + n = 6; + else + n = 9; + + period_n = ((u64)period_us * NSEC_PER_USEC) >> n; + + min_err = UINT_MAX; + last_err = UINT_MAX; + best_m = 0; + best_clk = 0; + best_div = 0; + for (clk = 0; clk < NUM_PWM_CLK; clk++) { + for (div = 0; div < NUM_PWM_PREDIV; div++) { + /* period_n = (PWM Period / N) */ + /* tmp_p = (Pre-divide * Clock Period) * 2^m */ + tmp_p = lpg_clk_table[div][clk]; + for (m = 0; m <= NUM_EXP; m++) { + cur_err = abs(period_n - tmp_p); + if (cur_err < min_err) { + min_err = cur_err; + best_m = m; + best_clk = clk; + best_div = div; + } + + if (m && cur_err > last_err) + /* Break for bigger cur_err */ + break; + + last_err = cur_err; + tmp_p <<= 1; + } + } + } + + /* Use higher resolution */ + if (best_m >= 3 && n == 6) { + n += 3; + best_m -= 3; + } + + chan->clk = best_clk; + chan->pre_div = best_div; + chan->pre_div_exp = best_m; + chan->pwm_size = n; + + chan->period_us = period_us; +} + +static void lpg_calc_duty(struct lpg_channel *chan, unsigned int duty_us) +{ + unsigned int max = (1 << chan->pwm_size) - 1; + unsigned int val = div_u64((u64)duty_us << chan->pwm_size, chan->period_us); + + chan->pwm_value = min(val, max); +} + +static void lpg_apply_freq(struct lpg_channel *chan) +{ + unsigned long val; + struct lpg *lpg = chan->lpg; + + if (!chan->enabled) + return; + + /* Clock register values are off-by-one from lpg_clk_table */ + val = chan->clk + 1; + + if (chan->pwm_size == 9) + val |= lpg->data->pwm_9bit_mask; + + regmap_write(lpg->map, chan->base + LPG_SIZE_CLK_REG, val); + + val = chan->pre_div << 5 | chan->pre_div_exp; + regmap_write(lpg->map, chan->base + LPG_PREDIV_CLK_REG, val); +} + +#define LPG_ENABLE_GLITCH_REMOVAL BIT(5) + +static void lpg_enable_glitch(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG, + LPG_ENABLE_GLITCH_REMOVAL, 0); +} + +static void lpg_disable_glitch(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG, + LPG_ENABLE_GLITCH_REMOVAL, + LPG_ENABLE_GLITCH_REMOVAL); +} + +static void lpg_apply_pwm_value(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + u16 val = chan->pwm_value; + + if (!chan->enabled) + return; + + regmap_bulk_write(lpg->map, chan->base + PWM_VALUE_REG, &val, 1); +} + +#define LPG_PATTERN_CONFIG_LO_TO_HI BIT(4) +#define LPG_PATTERN_CONFIG_REPEAT BIT(3) +#define LPG_PATTERN_CONFIG_TOGGLE BIT(2) +#define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1) +#define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0) + +static void lpg_apply_lut_control(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + unsigned int hi_pause; + unsigned int lo_pause; + unsigned int step; + unsigned int conf = 0; + unsigned int lo_idx = chan->pattern_lo_idx; + unsigned int hi_idx = chan->pattern_hi_idx; + int pattern_len; + + if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx) + return; + + pattern_len = hi_idx - lo_idx + 1; + + step = chan->ramp_tick_ms; + hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step); + lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step); + + if (!chan->ramp_reverse) + conf |= LPG_PATTERN_CONFIG_LO_TO_HI; + if (!chan->ramp_oneshot) + conf |= LPG_PATTERN_CONFIG_REPEAT; + if (chan->ramp_ping_pong) + conf |= LPG_PATTERN_CONFIG_TOGGLE; + if (chan->ramp_hi_pause_ms) + conf |= LPG_PATTERN_CONFIG_PAUSE_HI; + if (chan->ramp_lo_pause_ms) + conf |= LPG_PATTERN_CONFIG_PAUSE_LO; + + regmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf); + regmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx); + regmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx); + + regmap_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, step); + regmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause); + regmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause); +} + +#define LPG_ENABLE_CONTROL_OUTPUT BIT(7) +#define LPG_ENABLE_CONTROL_BUFFER_TRISTATE BIT(5) +#define LPG_ENABLE_CONTROL_SRC_PWM BIT(2) +#define LPG_ENABLE_CONTROL_RAMP_GEN BIT(1) + +static void lpg_apply_control(struct lpg_channel *chan) +{ + unsigned int ctrl; + struct lpg *lpg = chan->lpg; + + ctrl = LPG_ENABLE_CONTROL_BUFFER_TRISTATE; + + if (chan->enabled) + ctrl |= LPG_ENABLE_CONTROL_OUTPUT; + + if (chan->pattern_lo_idx != chan->pattern_hi_idx) + ctrl |= LPG_ENABLE_CONTROL_RAMP_GEN; + else + ctrl |= LPG_ENABLE_CONTROL_SRC_PWM; + + regmap_write(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, ctrl); + + /* + * Due to LPG hardware bug, in the PWM mode, having enabled PWM, + * We have to write PWM values one more time. + */ + if (chan->enabled) + lpg_apply_pwm_value(chan); +} + +#define LPG_SYNC_PWM BIT(0) + +static void lpg_apply_sync(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_write(lpg->map, chan->base + PWM_SYNC_REG, LPG_SYNC_PWM); +} + +static int lpg_parse_dtest(struct lpg *lpg) +{ + struct lpg_channel *chan; + struct device_node *np = lpg->dev->of_node; + int count; + int ret; + int i; + + count = of_property_count_u32_elems(np, "qcom,dtest"); + if (count == -EINVAL) { + return 0; + } else if (count < 0) { + ret = count; + goto err_malformed; + } else if (count != lpg->data->num_channels * 2) { + dev_err(lpg->dev, "qcom,dtest needs to be %d items\n", + lpg->data->num_channels * 2); + return -EINVAL; + } + + for (i = 0; i < lpg->data->num_channels; i++) { + chan = &lpg->channels[i]; + + ret = of_property_read_u32_index(np, "qcom,dtest", i * 2, + &chan->dtest_line); + if (ret) + goto err_malformed; + + ret = of_property_read_u32_index(np, "qcom,dtest", i * 2 + 1, + &chan->dtest_value); + if (ret) + goto err_malformed; + } + + return 0; + +err_malformed: + dev_err(lpg->dev, "malformed qcom,dtest\n"); + return ret; +} + +static void lpg_apply_dtest(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + if (!chan->dtest_line) + return; + + regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5); + regmap_write(lpg->map, chan->base + PWM_DTEST_REG(chan->dtest_line), + chan->dtest_value); +} + +static void lpg_apply(struct lpg_channel *chan) +{ + lpg_disable_glitch(chan); + lpg_apply_freq(chan); + lpg_apply_pwm_value(chan); + lpg_apply_control(chan); + lpg_apply_sync(chan); + lpg_apply_lut_control(chan); + lpg_enable_glitch(chan); +} + +static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev, + struct mc_subled *subleds) +{ + enum led_brightness brightness; + struct lpg_channel *chan; + unsigned int triled_enabled = 0; + unsigned int triled_mask = 0; + unsigned int lut_mask = 0; + unsigned int duty_us; + struct lpg *lpg = led->lpg; + int i; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + brightness = subleds[i].brightness; + + if (brightness == LED_OFF) { + chan->enabled = false; + chan->ramp_enabled = false; + } else if (chan->pattern_lo_idx != chan->pattern_hi_idx) { + lpg_calc_freq(chan, NSEC_PER_USEC); + + chan->enabled = true; + chan->ramp_enabled = true; + + lut_mask |= chan->lut_mask; + triled_enabled |= chan->triled_mask; + } else { + lpg_calc_freq(chan, NSEC_PER_USEC); + + duty_us = brightness * chan->period_us / cdev->max_brightness; + lpg_calc_duty(chan, duty_us); + chan->enabled = true; + chan->ramp_enabled = false; + + triled_enabled |= chan->triled_mask; + } + + triled_mask |= chan->triled_mask; + + lpg_apply(chan); + } + + /* Toggle triled lines */ + if (triled_mask) + triled_set(lpg, triled_mask, triled_enabled); + + /* Trigger start of ramp generator(s) */ + if (lut_mask) + lpg_lut_sync(lpg, lut_mask); +} + +static void lpg_brightness_single_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + struct mc_subled info; + + info.brightness = value; + lpg_brightness_set(led, cdev, &info); +} + +static void lpg_brightness_mc_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + led_mc_calc_color_components(mc, value); + lpg_brightness_set(led, cdev, mc->subled_info); +} + +static int lpg_blink_set(struct lpg_led *led, + unsigned long *delay_on, unsigned long *delay_off) +{ + struct lpg_channel *chan; + unsigned int period_us; + unsigned int duty_us; + int i; + + if (!*delay_on && !*delay_off) { + *delay_on = 500; + *delay_off = 500; + } + + duty_us = *delay_on * USEC_PER_MSEC; + period_us = (*delay_on + *delay_off) * USEC_PER_MSEC; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + + lpg_calc_freq(chan, period_us); + lpg_calc_duty(chan, duty_us); + + chan->enabled = true; + chan->ramp_enabled = false; + + lpg_apply(chan); + } + + return 0; +} + +static int lpg_blink_single_set(struct led_classdev *cdev, + unsigned long *delay_on, unsigned long *delay_off) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + + return lpg_blink_set(led, delay_on, delay_off); +} + +static int lpg_blink_mc_set(struct led_classdev *cdev, + unsigned long *delay_on, unsigned long *delay_off) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + return lpg_blink_set(led, delay_on, delay_off); +} + +static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *pattern, + u32 len, int repeat) +{ + struct lpg_channel *chan; + struct lpg *lpg = led->lpg; + unsigned int hi_pause; + unsigned int lo_pause; + unsigned int lo_idx; + unsigned int hi_idx; + bool ping_pong = true; + int brightness_a; + int brightness_b; + int ret; + int i; + + /* Only support oneshot or indefinite loops, due to limited pattern space */ + if (repeat != -1 && repeat != 1) + return -EINVAL; + + /* + * The LPG plays patterns with at a fixed pace, a "low pause" can be + * performed before the pattern and a "high pause" after. In order to + * save space the pattern can be played in "ping pong" mode, in which + * the pattern is first played forward, then "high pause" is applied, + * then the pattern is played backwards and finally the "low pause" is + * applied. + * + * The delta_t of the first entry is used to determine the pace of the + * pattern. + * + * If the specified pattern is a palindrome the ping pong mode is + * enabled. In this scenario the delta_t of the last entry determines + * the "low pause" time and the delta_t of the middle entry (i.e. the + * last in the programmed pattern) determines the "high pause". If the + * pattern consists of an odd number of values, no "high pause" is + * used. + * + * When ping pong mode is not selected, the delta_t of the last entry + * is used as "high pause". No "low pause" is used. + * + * delta_t of any other members of the pattern is ignored. + */ + + /* Detect palindromes and use "ping pong" to reduce LUT usage */ + for (i = 0; i < len / 2; i++) { + brightness_a = pattern[i].brightness; + brightness_b = pattern[len - i - 1].brightness; + + if (brightness_a != brightness_b) { + ping_pong = false; + break; + } + } + + if (ping_pong) { + if (len % 2) + hi_pause = 0; + else + hi_pause = pattern[(len + 1) / 2].delta_t; + lo_pause = pattern[len - 1].delta_t; + + len = (len + 1) / 2; + } else { + hi_pause = pattern[len - 1].delta_t; + lo_pause = 0; + } + + ret = lpg_lut_store(lpg, pattern, len, &lo_idx, &hi_idx); + if (ret < 0) + return ret; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + + chan->ramp_tick_ms = pattern[0].delta_t; + chan->ramp_ping_pong = ping_pong; + chan->ramp_oneshot = repeat != -1; + + chan->ramp_lo_pause_ms = lo_pause; + chan->ramp_hi_pause_ms = hi_pause; + + chan->pattern_lo_idx = lo_idx; + chan->pattern_hi_idx = hi_idx; + } + + return 0; +} + +static int lpg_pattern_single_set(struct led_classdev *cdev, + struct led_pattern *pattern, u32 len, + int repeat) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + int ret; + + ret = lpg_pattern_set(led, pattern, len, repeat); + if (ret < 0) + return ret; + + lpg_brightness_single_set(cdev, LED_FULL); + + return 0; +} + +static int lpg_pattern_mc_set(struct led_classdev *cdev, + struct led_pattern *pattern, u32 len, + int repeat) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + int ret; + + ret = lpg_pattern_set(led, pattern, len, repeat); + if (ret < 0) + return ret; + + led_mc_calc_color_components(mc, LED_FULL); + lpg_brightness_set(led, cdev, mc->subled_info); + + return 0; +} + +static int lpg_pattern_clear(struct lpg_led *led) +{ + struct lpg_channel *chan; + struct lpg *lpg = led->lpg; + int i; + + chan = led->channels[0]; + lpg_lut_free(lpg, chan->pattern_lo_idx, chan->pattern_hi_idx); + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + chan->pattern_lo_idx = 0; + chan->pattern_hi_idx = 0; + } + + return 0; +} + +static int lpg_pattern_single_clear(struct led_classdev *cdev) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + + return lpg_pattern_clear(led); +} + +static int lpg_pattern_mc_clear(struct led_classdev *cdev) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + return lpg_pattern_clear(led); +} + +static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpg *lpg = container_of(chip, struct lpg, pwm); + struct lpg_channel *chan = &lpg->channels[pwm->hwpwm]; + + return chan->in_use ? -EBUSY : 0; +} + +static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct lpg *lpg = container_of(chip, struct lpg, pwm); + struct lpg_channel *chan = &lpg->channels[pwm->hwpwm]; + + lpg_calc_freq(chan, div_u64(state->period, NSEC_PER_USEC)); + lpg_calc_duty(chan, div_u64(state->duty_cycle, NSEC_PER_USEC)); + chan->enabled = state->enabled; + + lpg_apply(chan); + + triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0); + + return 0; +} + +static const struct pwm_ops lpg_pwm_ops = { + .request = lpg_pwm_request, + .apply = lpg_pwm_apply, + .owner = THIS_MODULE, +}; + +static int lpg_add_pwm(struct lpg *lpg) +{ + int ret; + + lpg->pwm.base = -1; + lpg->pwm.dev = lpg->dev; + lpg->pwm.npwm = lpg->num_channels; + lpg->pwm.ops = &lpg_pwm_ops; + + ret = pwmchip_add(&lpg->pwm); + if (ret) + dev_err(lpg->dev, "failed to add PWM chip: ret %d\n", ret); + + return ret; +} + +static int lpg_parse_channel(struct lpg *lpg, struct device_node *np, + struct lpg_channel **channel) +{ + struct lpg_channel *chan; + u32 color = LED_COLOR_ID_GREEN; + u32 reg; + int ret; + + ret = of_property_read_u32(np, "reg", ®); + if (ret || !reg || reg > lpg->num_channels) { + dev_err(lpg->dev, "invalid reg of %pOFn\n", np); + return -EINVAL; + } + + chan = &lpg->channels[reg - 1]; + chan->in_use = true; + + ret = of_property_read_u32(np, "color", &color); + if (ret < 0 && ret != -EINVAL) { + dev_err(lpg->dev, "failed to parse \"color\" of %pOF\n", np); + return ret; + } + + chan->color = color; + + *channel = chan; + + return 0; +} + +static int lpg_add_led(struct lpg *lpg, struct device_node *np) +{ + struct led_classdev *cdev; + struct device_node *child; + struct mc_subled *info; + struct lpg_led *led; + const char *state; + int num_channels; + u32 color = 0; + int ret; + int i; + + ret = of_property_read_u32(np, "color", &color); + if (ret < 0 && ret != -EINVAL) { + dev_err(lpg->dev, "failed to parse \"color\" of %pOF\n", np); + return ret; + } + + if (color == LED_COLOR_ID_MULTI) + num_channels = of_get_available_child_count(np); + else + num_channels = 1; + + led = devm_kzalloc(lpg->dev, struct_size(led, channels, num_channels), GFP_KERNEL); + if (!led) + return -ENOMEM; + + led->lpg = lpg; + led->num_channels = num_channels; + + if (color == LED_COLOR_ID_MULTI) { + info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + i = 0; + for_each_available_child_of_node(np, child) { + ret = lpg_parse_channel(lpg, child, &led->channels[i]); + if (ret < 0) + return ret; + + info[i].color_index = led->channels[i]->color; + info[i].intensity = LED_FULL; + i++; + } + + led->mcdev.subled_info = info; + led->mcdev.num_colors = num_channels; + + cdev = &led->mcdev.led_cdev; + cdev->brightness_set = lpg_brightness_mc_set; + cdev->blink_set = lpg_blink_mc_set; + + /* Register pattern accessors only if we have a LUT block */ + if (lpg->lut_base) { + cdev->pattern_set = lpg_pattern_mc_set; + cdev->pattern_clear = lpg_pattern_mc_clear; + } + } else { + ret = lpg_parse_channel(lpg, np, &led->channels[0]); + if (ret < 0) + return ret; + + cdev = &led->cdev; + cdev->brightness_set = lpg_brightness_single_set; + cdev->blink_set = lpg_blink_single_set; + + /* Register pattern accessors only if we have a LUT block */ + if (lpg->lut_base) { + cdev->pattern_set = lpg_pattern_single_set; + cdev->pattern_clear = lpg_pattern_single_clear; + } + } + + /* Use label else node name */ + cdev->name = of_get_property(np, "label", NULL) ? : np->name; + cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL); + cdev->max_brightness = 255; + + if (!of_property_read_string(np, "default-state", &state) && + !strcmp(state, "on")) + cdev->brightness = LED_FULL; + else + cdev->brightness = LED_OFF; + + cdev->brightness_set(cdev, cdev->brightness); + + if (color == LED_COLOR_ID_MULTI) + ret = devm_led_classdev_multicolor_register(lpg->dev, &led->mcdev); + else + ret = devm_led_classdev_register(lpg->dev, &led->cdev); + if (ret) + dev_err(lpg->dev, "unable to register %s\n", cdev->name); + + return ret; +} + +static int lpg_init_channels(struct lpg *lpg) +{ + const struct lpg_data *data = lpg->data; + int i; + + lpg->num_channels = data->num_channels; + lpg->channels = devm_kcalloc(lpg->dev, data->num_channels, + sizeof(struct lpg_channel), GFP_KERNEL); + if (!lpg->channels) + return -ENOMEM; + + for (i = 0; i < data->num_channels; i++) { + lpg->channels[i].lpg = lpg; + lpg->channels[i].base = data->channels[i].base; + lpg->channels[i].triled_mask = data->channels[i].triled_mask; + lpg->channels[i].lut_mask = BIT(i); + } + + return 0; +} + +static int lpg_init_triled(struct lpg *lpg) +{ + struct device_node *np = lpg->dev->of_node; + int ret; + + /* Skip initialization if we don't have a triled block */ + if (!lpg->data->triled_base) + return 0; + + lpg->triled_base = lpg->data->triled_base; + lpg->triled_has_atc_ctl = lpg->data->triled_has_atc_ctl; + lpg->triled_has_src_sel = lpg->data->triled_has_src_sel; + + if (lpg->triled_has_src_sel) { + ret = of_property_read_u32(np, "qcom,power-source", &lpg->triled_src); + if (ret || lpg->triled_src == 2 || lpg->triled_src > 3) { + dev_err(lpg->dev, "invalid power source\n"); + return -EINVAL; + } + } + + /* Disable automatic trickle charge LED */ + if (lpg->triled_has_atc_ctl) + regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0); + + /* Configure power source */ + if (lpg->triled_has_src_sel) + regmap_write(lpg->map, lpg->triled_base + TRI_LED_SRC_SEL, lpg->triled_src); + + /* Default all outputs to off */ + regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0); + + return 0; +} + +static int lpg_init_lut(struct lpg *lpg) +{ + const struct lpg_data *data = lpg->data; + size_t bitmap_size; + + if (!data->lut_base) + return 0; + + lpg->lut_base = data->lut_base; + lpg->lut_size = data->lut_size; + + bitmap_size = BITS_TO_BYTES(lpg->lut_size); + lpg->lut_bitmap = devm_kzalloc(lpg->dev, bitmap_size, GFP_KERNEL); + if (!lpg->lut_bitmap) + return -ENOMEM; + + bitmap_clear(lpg->lut_bitmap, 0, lpg->lut_size); + + return 0; +} + +static int lpg_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct lpg *lpg; + int ret; + int i; + + lpg = devm_kzalloc(&pdev->dev, sizeof(*lpg), GFP_KERNEL); + if (!lpg) + return -ENOMEM; + + lpg->data = of_device_get_match_data(&pdev->dev); + if (!lpg->data) + return -EINVAL; + + lpg->dev = &pdev->dev; + + lpg->map = dev_get_regmap(pdev->dev.parent, NULL); + if (!lpg->map) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + ret = lpg_init_channels(lpg); + if (ret < 0) + return ret; + + ret = lpg_parse_dtest(lpg); + if (ret < 0) + return ret; + + ret = lpg_init_triled(lpg); + if (ret < 0) + return ret; + + ret = lpg_init_lut(lpg); + if (ret < 0) + return ret; + + for_each_available_child_of_node(pdev->dev.of_node, np) { + ret = lpg_add_led(lpg, np); + if (ret) + return ret; + } + + for (i = 0; i < lpg->num_channels; i++) + lpg_apply_dtest(&lpg->channels[i]); + + ret = lpg_add_pwm(lpg); + if (ret) + return ret; + + platform_set_drvdata(pdev, lpg); + + return 0; +} + +static int lpg_remove(struct platform_device *pdev) +{ + struct lpg *lpg = platform_get_drvdata(pdev); + + pwmchip_remove(&lpg->pwm); + + return 0; +} + +static const struct lpg_data pm8916_pwm_data = { + .pwm_9bit_mask = BIT(2), + + .num_channels = 1, + .channels = (struct lpg_channel_data[]) { + { .base = 0xbc00 }, + }, +}; + +static const struct lpg_data pm8941_lpg_data = { + .lut_base = 0xb000, + .lut_size = 64, + + .triled_base = 0xd000, + .triled_has_atc_ctl = true, + .triled_has_src_sel = true, + + .pwm_9bit_mask = 3 << 4, + + .num_channels = 8, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300 }, + { .base = 0xb400 }, + { .base = 0xb500, .triled_mask = BIT(5) }, + { .base = 0xb600, .triled_mask = BIT(6) }, + { .base = 0xb700, .triled_mask = BIT(7) }, + { .base = 0xb800 }, + }, +}; + +static const struct lpg_data pm8994_lpg_data = { + .lut_base = 0xb000, + .lut_size = 64, + + .pwm_9bit_mask = 3 << 4, + + .num_channels = 6, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300 }, + { .base = 0xb400 }, + { .base = 0xb500 }, + { .base = 0xb600 }, + }, +}; + +static const struct lpg_data pmi8994_lpg_data = { + .lut_base = 0xb000, + .lut_size = 24, + + .triled_base = 0xd000, + .triled_has_atc_ctl = true, + .triled_has_src_sel = true, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 4, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100, .triled_mask = BIT(5) }, + { .base = 0xb200, .triled_mask = BIT(6) }, + { .base = 0xb300, .triled_mask = BIT(7) }, + { .base = 0xb400 }, + }, +}; + +static const struct lpg_data pmi8998_lpg_data = { + .lut_base = 0xb000, + .lut_size = 49, + + .triled_base = 0xd000, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 6, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300, .triled_mask = BIT(5) }, + { .base = 0xb400, .triled_mask = BIT(6) }, + { .base = 0xb500, .triled_mask = BIT(7) }, + { .base = 0xb600 }, + }, +}; + +static const struct lpg_data pm8150b_lpg_data = { + .lut_base = 0xb000, + .lut_size = 49, + + .triled_base = 0xd000, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 2, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100, .triled_mask = BIT(7) }, + { .base = 0xb200, .triled_mask = BIT(6) }, + }, +}; + +static const struct lpg_data pm8150l_lpg_data = { + .lut_base = 0xb000, + .lut_size = 49, + + .triled_base = 0xd000, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 5, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100, .triled_mask = BIT(7) }, + { .base = 0xb200, .triled_mask = BIT(6) }, + { .base = 0xb300, .triled_mask = BIT(5) }, + { .base = 0xbc00 }, + { .base = 0xbd00 }, + + }, +}; + +static const struct of_device_id lpg_of_table[] = { + { .compatible = "qcom,pm8150b-lpg", .data = &pm8150b_lpg_data }, + { .compatible = "qcom,pm8150l-lpg", .data = &pm8150l_lpg_data }, + { .compatible = "qcom,pm8916-pwm", .data = &pm8916_pwm_data }, + { .compatible = "qcom,pm8941-lpg", .data = &pm8941_lpg_data }, + { .compatible = "qcom,pm8994-lpg", .data = &pm8994_lpg_data }, + { .compatible = "qcom,pmi8994-lpg", .data = &pmi8994_lpg_data }, + { .compatible = "qcom,pmi8998-lpg", .data = &pmi8998_lpg_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpg_of_table); + +static struct platform_driver lpg_driver = { + .probe = lpg_probe, + .remove = lpg_remove, + .driver = { + .name = "qcom-spmi-lpg", + .of_match_table = lpg_of_table, + }, +}; +module_platform_driver(lpg_driver); + +MODULE_DESCRIPTION("Qualcomm LPG LED driver"); +MODULE_LICENSE("GPL v2"); From 562c27df433283f60c779b8e69e5ee0a1b4d4584 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:14 -0700 Subject: [PATCH 046/174] arm64: dts: qcom: Add LPG to pm8916, pm8994, pmi8994 and pmi8998 Add PWM/LPG nodes to the PMICs currently supported by the binding. Signed-off-by: Bjorn Andersson (JAMI: fixed up for v5.16-rc1) --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/pm8994.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pmi8994.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pmi8998.dtsi | 9 +++++++++ 4 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index d58902432812..99bf8387bfb6 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -125,6 +125,14 @@ #address-cells = <1>; #size-cells = <0>; + pm8916_pwm: pwm { + compatible = "qcom,pm8916-pwm"; + + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8916_vib: vibrator@c000 { compatible = "qcom,pm8916-vib"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 5ab46117d737..ab342397fcd8 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -135,6 +135,16 @@ #address-cells = <1>; #size-cells = <0>; + pm8994_lpg: lpg { + compatible = "qcom,pm8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8994_spmi_regulators: regulators { compatible = "qcom,pm8994-regulators"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 6e7c252568e6..b1b50c99ada2 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -27,6 +27,16 @@ #address-cells = <1>; #size-cells = <0>; + pmi8994_lpg: lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 0fef5f113f05..a5d50d7156cc 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -53,5 +53,14 @@ status = "disabled"; }; + pmi8998_lpg: lpg { + compatible = "qcom,pmi8998-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; From 262f1c68a42120edb91106d4291526db0876f843 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:15 -0700 Subject: [PATCH 047/174] arm64: dts: qcom: sdm845: Enable user LEDs on DB845c The DB845c has 4 "user LEDs", the last one is already supported as it's just wired to a gpio. Now that the LPG binding is in place we can wire up the other 3 LEDs as well. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 13f80a0b6faa..84b822328566 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -595,6 +595,30 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + qcom,power-source = <1>; + + led@3 { + reg = <3>; + label = "green:user3"; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@4 { + reg = <4>; + label = "green:user2"; + }; + + led@5 { + reg = <5>; + label = "green:user1"; + }; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { From 1d5f57a7c3550c7240a16d891613301fb5d4750a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:16 -0700 Subject: [PATCH 048/174] arm64: dts: qcom: pmi8994: Define MPP block The pmi8994 has 4 multi-purpose-pins, add these to the definition. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index b1b50c99ada2..97e76f196723 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -19,6 +19,18 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pmi8994_mpps: mpps@a000 { + compatible = "qcom,pmi8994-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pmi8994_mpps 0 0 4>; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + }; }; pmic@3 { From 75b4a4747705eb18cd004fd8f1e2d211ee0cb30d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Apr 2021 14:15:17 -0700 Subject: [PATCH 049/174] arm64: dts: qcom: db820c: Add user LEDs The db820c has 4 "user LEDs", all connected to the PMI8994. The first three are connected to the three current sinks provided by the TRILED and the fourth is connected to MPP2. By utilizing the DTEST bus the MPP is fed the control signal from the fourth LPG block, providing a consistent interface to the user. Signed-off-by: Bjorn Andersson (JAMI: fixed up for v5.16-rc1) --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 49 +++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index f623db8451f1..5b857697c443 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -10,6 +10,7 @@ #include "pmi8994.dtsi" #include #include +#include #include #include #include @@ -677,6 +678,54 @@ }; }; +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + qcom,dtest = <0 0 + 0 0 + 0 0 + 4 1>; + + status = "okay"; + + led@1 { + reg = <1>; + label = "green:user1"; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + label = "green:user0"; + default-state = "on"; + }; + + led@3 { + reg = <3>; + label = "green:user2"; + }; + + led@4 { + reg = <4>; + label = "green:user3"; + }; +}; + +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4-state { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + &pmi8994_spmi_regulators { vdd_s2-supply = <&vph_pwr>; From 24aa91f32bc63cf108b262fa93bd84784faf0106 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 14:27:11 +0200 Subject: [PATCH 050/174] leds: qcom-lpg: Review fixups! --- drivers/leds/Kconfig | 13 +++++++++++-- drivers/leds/Makefile | 4 +++- drivers/leds/rgb/leds-qcom-lpg.c | 6 +++--- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index a49979f41eee..c893e7a70310 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -869,8 +869,17 @@ source "drivers/leds/blink/Kconfig" comment "Flash and Torch LED drivers" source "drivers/leds/flash/Kconfig" -comment "RGB LED drivers" -source "drivers/leds/rgb/Kconfig" +#comment "RGB LED drivers" +#source "drivers/leds/rgb/Kconfig" + +config LEDS_QCOM_LPG + tristate "LED support for Qualcomm LPG" + depends on LEDS_CLASS_MULTICOLOR + depends on OF + depends on SPMI + help + This option enables support for the Light Pulse Generator found in a + wide variety of Qualcomm PMICs. comment "LED Triggers" source "drivers/leds/trigger/Kconfig" diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 4fd2f92cd198..be8ab449ba32 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -100,7 +100,9 @@ obj-$(CONFIG_LEDS_USER) += uleds.o obj-$(CONFIG_LEDS_CLASS_FLASH) += flash/ # RGB LED Drivers -obj-$(CONFIG_LEDS_CLASS_MULTICOLOR) += rgb/ +# obj-$(CONFIG_LEDS_CLASS_MULTICOLOR) += rgb/ + +obj-$(CONFIG_LEDS_QCOM_LPG) += rgb/leds-qcom-lpg.o # LED Triggers obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c index c68233b43c2c..647f20fa59c1 100644 --- a/drivers/leds/rgb/leds-qcom-lpg.c +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -918,7 +918,7 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np) return ret; } - if (color == LED_COLOR_ID_MULTI) + if (color == LED_COLOR_ID_RGB) num_channels = of_get_available_child_count(np); else num_channels = 1; @@ -930,7 +930,7 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np) led->lpg = lpg; led->num_channels = num_channels; - if (color == LED_COLOR_ID_MULTI) { + if (color == LED_COLOR_ID_RGB) { info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; @@ -986,7 +986,7 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np) cdev->brightness_set(cdev, cdev->brightness); - if (color == LED_COLOR_ID_MULTI) + if (color == LED_COLOR_ID_RGB) ret = devm_led_classdev_multicolor_register(lpg->dev, &led->mcdev); else ret = devm_led_classdev_register(lpg->dev, &led->cdev); From ed5f3ba9c0af7336c042341b7acf075bbd234336 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 4 Aug 2021 16:39:35 +0200 Subject: [PATCH 051/174] iommu/arm-smmu-qcom: Allow choosing a custom bypass emulation context It cannot be taken for granted that the last IOMMU context is free and available for us to use it to emulate bypass streams and, at least on MSM8998's lpass iommu, using the last one will produce a crash; please note that this may not be only dependant on the SoC, but also on the firmware version. To overcome to this issue, allow specifying a different context for bypass emulation with the optional DT property "qcom,bypass-cbndx": if this property is not found this means that we are either booting with ACPI instead or that we don't want to specify a custom cb because the default one (the last context bank) is fine. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index ba6298c7140e..843418d0e0d9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -267,7 +267,8 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) reg = arm_smmu_gr0_read(smmu, last_s2cr); if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { qsmmu->bypass_quirk = true; - qsmmu->bypass_cbndx = smmu->num_context_banks - 1; + if (qsmmu->bypass_cbndx == 0xff) + qsmmu->bypass_cbndx = smmu->num_context_banks - 1; set_bit(qsmmu->bypass_cbndx, smmu->context_map); @@ -387,6 +388,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = { static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, const struct arm_smmu_impl *impl) { + const struct device_node *np = smmu->dev->of_node; struct qcom_smmu *qsmmu; /* Check to make sure qcom_scm has finished probing */ @@ -398,6 +400,16 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, return ERR_PTR(-ENOMEM); qsmmu->smmu.impl = impl; + qsmmu->bypass_cbndx = 0xff; + + if (np != NULL) { + /* + * This property is optional and we expect to fail finding it if: + * - Using the default bypass_cbndx (in the .cfg_probe cb) is fine; or + * - We are booting on ACPI + */ + of_property_read_u8(np, "qcom,bypass-cbndx", &qsmmu->bypass_cbndx); + } return &qsmmu->smmu; } From ed38aa4ac2acc877a51c4dc7acfbff49cfd8d131 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 13:14:41 +0200 Subject: [PATCH 052/174] iommu/arm-smmu: Allow skipping context bank disable at reset time On some SoCs some IOMMU context banks are actively used from TZ during system boot, or some hypervisor configurations will trigger a system reset upon disabling some protected/secured CBs. Allow skipping the disablement of such contexts at IOMMU reset time during initialization with a new implementation detail to work around this quirk. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 10 ++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 4bc75c4ce402..2c75ef23deec 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1622,6 +1622,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Make sure all context banks are disabled and clear CB_FSR */ for (i = 0; i < smmu->num_context_banks; ++i) { + /* + * Some context banks cannot be disabled due to hypervisor + * configuration on some systems; if this is the case, + * skip disabling and writing FAULT on the CB FSR in order + * to avoid a system crash. + */ + if (smmu->impl && smmu->impl->reset_cb_nodisable && + smmu->impl->reset_cb_nodisable(smmu, i)) { + continue; + } arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 432de2f742c3..43051ed940e5 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -430,6 +430,7 @@ struct arm_smmu_impl { u64 val); int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); + bool (*reset_cb_nodisable)(struct arm_smmu_device *smmu, int cbndx); int (*init_context)(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *cfg, struct device *dev); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, From 2dba96237ac429734d529bb77e19e73b3ef9795d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 13:19:14 +0200 Subject: [PATCH 053/174] iommu/arm-smmu-qcom: Avoid disabling secured context banks Some Qualcomm SoCs' TZ/hypervisor configuration is disallowing the disablement of some context banks, being them used for tzapps and/or remote processors; any attempt to disable such CBs will result in triggering a fault and the system will freeze and/or reset. For this reason, get a list of context banks that should never get disabled during smmu initialization through a DT array property `qcom,reset-nodisable-cbs`. It was chosen to not hardcode the CBs as this is dependant on the SoC's firmware, which may vary on different boards. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 843418d0e0d9..408eee87b71c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -12,6 +13,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; + DECLARE_BITMAP(reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS); bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; @@ -369,11 +371,20 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) return 0; } +static bool qcom_smmu500_reset_cb_nodisable(struct arm_smmu_device *smmu, + int cbndx) +{ + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + + return test_bit(cbndx, qsmmu->reset_cb_nodisable_mask); +} + static const struct arm_smmu_impl qcom_smmu_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, + .reset_cb_nodisable = qcom_smmu500_reset_cb_nodisable, .write_s2cr = qcom_smmu_write_s2cr, }; @@ -381,6 +392,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, + .reset_cb_nodisable = qcom_smmu500_reset_cb_nodisable, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, }; @@ -390,6 +402,8 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, { const struct device_node *np = smmu->dev->of_node; struct qcom_smmu *qsmmu; + u8 reset_nodisable_cbs[ARM_SMMU_MAX_CBS]; + int i, sz; /* Check to make sure qcom_scm has finished probing */ if (!qcom_scm_is_available()) @@ -401,6 +415,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->bypass_cbndx = 0xff; + bitmap_zero(qsmmu->reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS); if (np != NULL) { /* @@ -409,6 +424,23 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, * - We are booting on ACPI */ of_property_read_u8(np, "qcom,bypass-cbndx", &qsmmu->bypass_cbndx); + + /* + * Some context banks may not be disabled because they are + * secured: read from DT a list of secured contexts that cannot + * be disabled without crashing the system. + * This list is optional, as not all firmware configurations do + * require us skipping disablement of context banks. + */ + sz = of_property_read_variable_u8_array(np, "qcom,reset-nodisable-cbs", + reset_nodisable_cbs, + 1, ARM_SMMU_MAX_CBS); + if (sz > 0) { + for (i = 0; i < sz; i++) { + __set_bit(reset_nodisable_cbs[i], + qsmmu->reset_cb_nodisable_mask); + } + } } return &qsmmu->smmu; From bc5d106fe5eae0a1fab56276ac8ae4dba4279ee9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 15:15:33 +0200 Subject: [PATCH 054/174] iommu/arm-smmu-qcom: Don't modify sACR on hypervisor secured iommus Avoid modifying the contents of the secure Auxiliary Control Register on some Qualcomm SoCs: due to a hypervisor configuration on some firmware versions, this would result in a system crash. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 408eee87b71c..d32fe3e267d8 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -362,8 +362,15 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) static int qcom_smmu500_reset(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); - arm_mmu500_reset(smmu); + /* + * Execute the mmu-500 reset implementation detail only if there + * are no secured untouchable contexts in this iommu, otherwise + * the system will crash. + */ + if (bitmap_empty(qsmmu->reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS)) + arm_mmu500_reset(smmu); if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) return qcom_sdm845_smmu500_reset(smmu); From 8fa5063793623d1d43336cb45fedd43cf29e819b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 15 Dec 2020 01:06:27 +0100 Subject: [PATCH 055/174] cpufreq: Add MSM8998 to cpufreq-dt-platdev blocklist Add the MSM8998 to the blocklist since the CPU scaling is handled out of this. Signed-off-by: AngeloGioacchino Del Regno --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index ca1d103ec449..d9a0b683ff97 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -136,6 +136,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,apq8096", }, { .compatible = "qcom,msm8996", }, + { .compatible = "qcom,msm8998", }, { .compatible = "qcom,qcs404", }, { .compatible = "qcom,sa8155p" }, { .compatible = "qcom,sc7180", }, From 0c034c5ea7094a09eb3fb5318974a393d881f7d1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 20 Oct 2020 21:09:43 +0530 Subject: [PATCH 056/174] dt-bindings: arm: cpus: Document 'qcom,freq-domain' property Add devicetree documentation for 'qcom,freq-domain' property specific to Qualcomm CPUs. This property is used to reference the CPUFREQ node along with Domain ID (0/1). Signed-off-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0dcebc48ea22..9fd50accb226 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -313,6 +313,12 @@ properties: * arm/msm/qcom,kpss-acc.txt + qcom,freq-domain: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + CPUs supporting freq-domain must set their "qcom,freq-domain" property + with phandle to a cpufreq_hw node followed by the Domain ID(0/1). + rockchip,pmu: $ref: '/schemas/types.yaml#/definitions/phandle' description: | From 6ebf835ad55d14bbc8a3f6179d98132c3a844865 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 20 Oct 2020 21:09:44 +0530 Subject: [PATCH 057/174] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings Convert Qualcomm cpufreq devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204 ++++++++++++++++++ 2 files changed, 204 insertions(+), 172 deletions(-) delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index 9299028ee712..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,172 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequency -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". - -- clocks - Usage: required - Value type: From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: From common clock binding. - Definition: must be "xo", "alternate". - -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -- #freq-domain-cells: - Usage: required. - Definition: Number of cells in a freqency domain specifier. - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property with -phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch -DCVS state together. - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; - reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml new file mode 100644 index 000000000000..bc81b6203e27 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Manivannan Sadhasivam + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw + + - description: v2 of CPUFREQ HW (EPSS) + items: + - enum: + - qcom,sm8250-cpufreq-epss + - const: qcom,cpufreq-epss + + reg: + minItems: 2 + maxItems: 3 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: freq-domain0 + - const: freq-domain1 + - const: freq-domain2 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + '#freq-domain-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster + // switch DCVS state together. + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + }; +... From 0485ef79b6ba56a5141c320aa4f05dc903a96724 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Jun 2021 22:35:49 +0200 Subject: [PATCH 058/174] cpufreq: qcom-hw: Add kerneldoc to some functions Some functions may not be very straightforward to understand: add kerneldoc to some ones in order to improve readability. Signed-off-by: AngeloGioacchino Del Regno --- drivers/cpufreq/qcom-cpufreq-hw.c | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index effbb680b453..27a4c782129e 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -55,6 +55,13 @@ struct qcom_cpufreq_data { static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; +/** + * qcom_cpufreq_set_bw() - Set interconnect bandwidth + * @policy: CPUFreq policy structure + * @freq_khz: CPU Frequency in KHz + * + * Returns: Zero for success, otherwise negative value on errors + */ static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, unsigned long freq_khz) { @@ -76,6 +83,20 @@ static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, return ret; } +/** + * qcom_cpufreq_update_opp() - Update CPU OPP tables + * @policy: CPUFreq policy structure + * @freq_khz: CPU Frequency for OPP entry in KHz + * @volt: CPU Voltage for OPP entry in microvolts + * + * The CPU frequencies and voltages are being read from the Operating + * State Manager (OSM) and the related OPPs, read from DT, need to be + * updated to reflect what the hardware will set for each p-state. + * If there is no OPP table specified in DT, then this function will + * add dynamic ones. + * + * Returns: Zero for success, otherwise negative value on errors + */ static int qcom_cpufreq_update_opp(struct device *cpu_dev, unsigned long freq_khz, unsigned long volt) @@ -96,6 +117,17 @@ static int qcom_cpufreq_update_opp(struct device *cpu_dev, return dev_pm_opp_enable(cpu_dev, freq_hz); } +/** + * qcom_cpufreq_hw_target_index() - Set frequency/voltage + * @policy: CPUFreq policy structure + * @index: Performance state index to be set + * + * This function sends a request to the Operating State Manager + * to set a Performance State index, so, to set frequency and + * voltage for the target CPU/cluster. + * + * Returns: Always zero + */ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { @@ -111,6 +143,12 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, return 0; } +/** + * qcom_cpufreq_hw_get() - Get current Performance State from OSM + * @cpu: CPU number + * + * Returns: Current CPU/Cluster frequency or zero + */ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) { struct qcom_cpufreq_data *data; @@ -144,6 +182,17 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, return policy->freq_table[index].frequency; } +/** + * qcom_cpufreq_hw_read_lut() - Read Lookup Table from the OSM + * @cpu_dev: CPU device + * @policy: CPUFreq policy structure + * + * The Operating State Manager Lookup Table can always be read, even + * in case it was pre-programmed by the bootloader or by TrustZone. + * Read the LUT from it in order to build OPPs containing DVFS info. + * + * Returns: Zero for success, otherwise negative number on errors. + */ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, struct cpufreq_policy *policy) { @@ -244,6 +293,11 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, return 0; } +/* + * qcom_get_related_cpus - Get mask of CPUs in the same frequency domain + * @index: CPU number + * @m: Returned CPU mask + */ static void qcom_get_related_cpus(int index, struct cpumask *m) { struct device_node *cpu_np; From 40e639041d9b3d63f2ff07c1f4da00ca120e84bd Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Jun 2021 22:42:25 +0200 Subject: [PATCH 059/174] cpufreq: qcom-hw: Implement CPRh aware OSM programming On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is being programmed in the bootloader and write-protected by the hypervisor, leaving to the OS read-only access to some of its registers (in order to read the Lookup Tables and also some status registers) and write access to the p-state register, for for the OS to request a specific performance state to trigger a DVFS switch on the CPU through the OSM hardware. On old SoCs though (MSM8998, SDM630/660 and variants), the bootloader will *not* initialize the OSM (and the CPRh, as it is a requirement for it) before booting the OS, making any request to trigger a performance state change ineffective, as the hardware doesn't have any Lookup Table, nor is storing any parameter to trigger a DVFS switch. In this case, basically all of the OSM registers are *not* write protected for the OS, even though some are - but write access is granted through SCM calls. This commit introduces support for OSM programming, which has to be done on these old SoCs that were distributed (almost?) always with a bootloader that does not do any CPRh nor OSM init before booting the kernel. In order to program the OSM on these SoCs, it is necessary to fullfill a "special" requirement: the Core Power Reduction Hardened (CPRh) hardware block must be initialized, as the OSM is "talking" to it in order to perform the Voltage part of DVFS; here, we are calling initialization of this through Linux generic power domains, specifically by requesting a genpd attach from the qcom-cpufreq-hw driver, which will give back voltages associated to each CPU frequency that has been declared in the OPPs, scaled and interpolated with the previous one, and will also give us parameters for the Array Power Mux (APM) and mem-acc, in order for this driver to be then able to generate the Lookup Tables that will be finally programmed to the OSM hardware. After writing the parameters to the OSM and enabling it, all the programming work will never happen anymore until a OS reboot, so all of the allocations and "the rest" will be disposed-of: this is done mainly to leave the code that was referred only to the new SoCs intact, as to also emphasize on the fact that the OSM HW is, in the end, the exact same; apart some register offsets that are slightly different, the entire logic is the same. This also adds the parameters to support CPU scaling on SDM630 and MSM8998. Signed-off-by: AngeloGioacchino Del Regno [Fixup for 5.15 by Jami] --- drivers/cpufreq/qcom-cpufreq-hw.c | 1078 ++++++++++++++++++++++++++++- 1 file changed, 1057 insertions(+), 21 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 27a4c782129e..a0313398473f 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -1,38 +1,261 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * OSM hardware initial programming + * Copyright (C) 2020, AngeloGioacchino Del Regno + * */ #include #include +#include #include #include #include +#include #include #include #include #include +#include #include #include #include +#include +#include #define LUT_MAX_ENTRIES 40U -#define LUT_SRC GENMASK(31, 30) +#define LUT_SRC_845 GENMASK(31, 30) +#define LUT_SRC_8998 GENMASK(27, 26) +#define LUT_PLL_DIV GENMASK(25, 24) #define LUT_L_VAL GENMASK(7, 0) #define LUT_CORE_COUNT GENMASK(18, 16) +#define LUT_VOLT_VC GENMASK(21, 16) #define LUT_VOLT GENMASK(11, 0) -#define CLK_HW_DIV 2 #define LUT_TURBO_IND 1 +#define OSM_BOOT_TIME_US 5 + +#define CYCLE_COUNTER_CLK_RATIO GENMASK(5, 1) +#define OSM_XO_RATIO_VAL (10 - 1) +#define CYCLE_COUNTER_USE_XO_EDGE BIT(8) + +/* FSM Boost Control */ +#define CC_BOOST_EN BIT(0) +#define PS_BOOST_EN BIT(1) +#define DCVS_BOOST_EN BIT(2) +#define BOOST_TIMER_REG_HI GENMASK(31, 16) +#define BOOST_TIMER_REG_LO GENMASK(15, 0) + +#define PLL_WAIT_LOCK_TIME_NS 2000 +#define SAFE_FREQ_WAIT_NS 1000 +#define DEXT_DECREMENT_WAIT_NS 200 + +#define BOOST_SYNC_DELAY 5 + +#define HYSTERESIS_UP_MASK GENMASK(31, 16) +#define HYSTERESIS_DN_MASK GENMASK(15, 0) +#define HYSTERESIS_CC_NS 200 +#define HYSTERESIS_LLM_NS 65535 + +/* FSM Droop Control */ +#define PC_RET_EXIT_DROOP_EN BIT(3) +#define WFX_DROOP_EN BIT(4) +#define DCVS_DROOP_EN BIT(5) +#define DROOP_TIMER1 GENMASK(31, 16) +#define DROOP_TIMER0 GENMASK(15, 0) +#define DROOP_CTRL_VAL (BIT(3) | BIT(17) | BIT(31)) +#define DROOP_TIMER_NS 100 +#define DROOP_WAIT_RELEASE_TIMER_NS 50 +#define DROOP_RELEASE_TIMER_NS 1 + +/* PLL Override Control */ +#define PLL_OVERRIDE_DROOP_EN BIT(0) + +/* Sequencer */ +#define SEQUENCER_REG(base, n) (base + (n * 4)) +#define SEQ_APM_THRESH_VC 15 +#define SEQ_APM_THRESH_PREVC 31 +#define SEQ_MEM_ACC_LVAL 32 +#define SEQ_MEM_ACC_0 55 +#define SEQ_APM_CROSSOVER_VC 72 +#define SEQ_APM_PARAM 76 +#define SEQ_MEM_ACC_CROSSOVER_VC 88 +#define SEQ_MEM_ACC_MAX_LEVELS 4 +#define SEQ_MEMACC_REG(base, n) SEQUENCER_REG(base, SEQ_MEM_ACC_0 + n) + +/* ACD */ +#define ACD_WRITE_CTL_UPDATE_EN BIT(0) +#define ACD_WRITE_CTL_SELECT_SHIFT 1 + +/** + * struct qcom_cpufreq_soc_setup_data - Register offsets for OSM setup + * + * @reg_osm_sequencer: OSM Sequencer (used to get physical address) + * @reg_override: Override parameters + * @reg_spare: Spare parameters (MEMACC-to-VC) + * @reg_cc_zero_behav: Virtual Corner for cluster power collapse + * @reg_spm_cc_hyst: DCVS-CC Wait time for frequency inc/decrement + * @reg_spm_cc_dcvs_dis: DCVS-CC en/disable control + * @reg_spm_core_ret_map: Treat cores in retention as active/inactive + * @reg_llm_freq_vote_hyst: DCVS-LLM Wait time for frequency inc/decrement + * @reg_llm_volt_vote_hyst: DCVS-LLM Wait time for voltage inc/decrement + * @reg_llm_intf_dcvs_dis: DCVS-LLM en/disable control + * @reg_seq1: Sequencer extra register + * @reg_pdn_fsm_ctrl: Boost and Droop FSMs en/disable control + * @reg_cc_boost_timer: CC-Boost FSM wait first timer register + * @reg_dcvs_boost_timer: DCVS-Boost FSM wait first timer register + * @reg_ps_boost_timer: PS-Boost FSM wait first timer register + * @boost_timer_reg_len: Length of boost timer registers + * @reg_boost_sync_delay: PLL signal timing control for Boost + * @reg_droop_ctrl: Droop control value + * @reg_droop_release_ctrl: Wait for Droop release + * @reg_droop_unstall_ctrl: Wait for Droop unstall + * @reg_droop_wait_release_ctrl: Time to wait for state release + * @reg_droop_timer_ctrl: Droop timer + * @reg_droop_sync_delay: PLL signal timing control for Droop + * @reg_pll_override: PLL Droop Override en/disable control + * @reg_cycle_counter: OSM CPU cycle counter + * + * This structure holds the register offsets that are used to set-up + * the Operating State Manager (OSM) parameters, when it is not (or + * not entirely) configured from the bootloader and TrustZone. + * + * Acronyms used in this documentation: + * CC = Core Count + * PS = Power-Save + * VC = Virtual Corner + * LLM = Limits Load Management + * DCVS = Dynamic Clock and Voltage Scaling + */ +struct qcom_cpufreq_soc_setup_data { + /* OSM phys register offsets */ + u16 reg_osm_sequencer; + + /* Frequency domain register offsets */ + u16 reg_override; + u16 reg_spare; + u16 reg_cc_zero_behav; + u16 reg_spm_cc_hyst; + u16 reg_spm_cc_dcvs_dis; + u16 reg_spm_core_ret_map; + u16 reg_llm_freq_vote_hyst; + u16 reg_llm_volt_vote_hyst; + u16 reg_llm_intf_dcvs_dis; + u16 reg_seq1; + u16 reg_pdn_fsm_ctrl; + u16 reg_cc_boost_timer; + u16 reg_dcvs_boost_timer; + u16 reg_ps_boost_timer; + u16 boost_timer_reg_len; + u16 reg_boost_sync_delay; + u16 reg_droop_ctrl; + u16 reg_droop_release_ctrl; + u16 reg_droop_unstall_ctrl; + u16 reg_droop_wait_release_ctrl; + u16 reg_droop_timer_ctrl; + u16 reg_droop_sync_delay; + u16 reg_pll_override; + u16 reg_cycle_counter; +}; + +/** + * struct qcom_cpufreq_soc_acd_data - Adaptive Clock Distribution data + * + * @tl_delay_reg: Tunable-Length Delay (TLD) register offset + * @acd_ctrl_reg: Control Register (CR) register offset + * @softstart_reg: Soft Start Control Register (SSCR) register offset + * @ext_intf_reg: External interface configuration register offset + * @auto_xfer_reg: Auto Register-Transfer register offset + * @auto_xfer_cfg_reg: Auto Register-Transfer Configuration reg offset + * @auto_xfer_ctl_reg: Auto Register-Transfer Control register offset + * @auto_xfer_sts_reg: Auto Register-Transfer Status register offset + * @dcvs_sw_reg: Software DCVS register offset + * @gfmux_cfg_reg: Glitch-Free MUX configuration register offset + * @write_ctl_reg: Write Control register + * @write_sts_reg: Write Status register + * @tl_delay_val: Tunable-Length Delay (TLD) value + * @acd_ctrl_val: Control Register (CR) value + * @softstart_val: Soft Start Control Register (SSCR) value + * @ext_intf0_val: Initial external interface configuration value + * @ext_intf1_val: Final external interface configuration value + * @auto_xfer_val: Auto-register Transfer Control value + * + * This structure holds the register offsets (from the ACD iospace base) + * and the parameters that are required to configure the OSM to + * initialize the Adaptive Clock Distribution (ACD) system. + */ +struct qcom_cpufreq_soc_acd_data { + u8 tl_delay_reg; + u8 acd_ctrl_reg; + u8 softstart_reg; + u8 ext_intf_reg; + u8 auto_xfer_reg; + u8 auto_xfer_cfg_reg; + u8 auto_xfer_ctl_reg; + u8 auto_xfer_sts_reg; + u8 dcvs_sw_reg; + u8 gfmux_cfg_reg; + u8 write_ctl_reg; + u8 write_sts_reg; + u32 tl_delay_val; + u32 acd_ctrl_val; + u32 softstart_val; + u32 ext_intf0_val; + u32 ext_intf1_val; + u32 auto_xfer_val; +}; + +/** + * struct qcom_cpufreq_hw_params - Operating State Manager (OSM) Parameters + * + * @volt_lut_val: Value composed of: virtual corner (vc) and voltage in mV. + * @freq_lut_val: Value composed of: core count, clock source and output + * frequency in MHz. + * @override_val: PLL parameters that the OSM uses to override the previous + * setting coming from the bootloader, or when uninitialized. + * @spare_val: Spare register, used by both this driver and the OSM HW + * to identify MEM-ACC levels in relation to virtual corners. + * + * This structure holds the parameters to write to the OSM registers for + * one "Virtual Corner" (VC), or one Performance State (p-state). + */ +struct qcom_cpufreq_hw_params { + u32 volt_lut_val; + u32 freq_lut_val; + u32 override_val; + u32 spare_val; +}; #define HZ_PER_KHZ 1000 +/** + * struct qcom_cpufreq_soc_data - SoC specific register offsets of the OSM + * + * @reg_enable: OSM enable status + * @reg_index: Index of the Virtual Corner + * @reg_freq_lut: Frequency Lookup Table + * @reg_freq_lut_src_mask: Frequency Lookup Table clock-source mask + * @reg_volt_lut: Voltage Lookup Table + * @reg_perf_state: Performance State request register + * @lut_row_size: Lookup Table row size + * @clk_hw_div: Divider for "alternate" OSM clock-source + * @uses_tz: OSM already set-up and protected by TrustZone + * @setup_regs: Register offsets for OSM setup + */ struct qcom_cpufreq_soc_data { u32 reg_enable; + u32 reg_index; u32 reg_freq_lut; + u32 reg_freq_lut_src_mask; u32 reg_volt_lut; u32 reg_current_vote; u32 reg_perf_state; u8 lut_row_size; + u8 clk_hw_div; + bool uses_tz; + const struct qcom_cpufreq_soc_setup_data setup_regs; + const struct qcom_cpufreq_soc_acd_data acd_data; }; struct qcom_cpufreq_data { @@ -52,6 +275,7 @@ struct qcom_cpufreq_data { struct cpufreq_policy *policy; }; +static const char *cprh_genpd_names[] = { "cprh", NULL }; static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; @@ -182,6 +406,574 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, return policy->freq_table[index].frequency; } +/** + * qcom_cpufreq_hw_boost_setup() - Sets up OSM boost timer registers + * @timer0_addr: Start of boost timer0 register group + * @len: Length (size) of "sub" registers in timer0 group + */ +static void qcom_cpufreq_hw_boost_setup(void __iomem *timer0_addr, u32 len) +{ + u32 val; + + /* timer_reg0 */ + val = FIELD_PREP(BOOST_TIMER_REG_LO, PLL_WAIT_LOCK_TIME_NS); + val |= FIELD_PREP(BOOST_TIMER_REG_HI, SAFE_FREQ_WAIT_NS); + writel(val, timer0_addr); + + /* timer_reg1 */ + val = FIELD_PREP(BOOST_TIMER_REG_LO, PLL_WAIT_LOCK_TIME_NS); + val |= FIELD_PREP(BOOST_TIMER_REG_HI, PLL_WAIT_LOCK_TIME_NS); + writel(val, timer0_addr + len); + + /* timer_reg2 */ + val = FIELD_PREP(BOOST_TIMER_REG_LO, DEXT_DECREMENT_WAIT_NS); + writel(val, timer0_addr + (2 * len)); +} + +/** + * qcom_cpufreq_gen_params() - Generate parameters to send to the hardware + * @cpu_dev: CPU device + * @data: SoC specific register offsets + * @hw_tbl: Pointer to return the array of parameters + * @apm_vc: APM Virtual Corner crossover number, returned to the caller + * @acc_vc: MEMACC Virtual Corner crossover number, returned to the caller + * @cpu_count: Number of CPUs in the frequency domain + * @num_entries: Number of allocated (and filled) elements in the table, + * returned to the caller + * + * This function allocates a 'qcom_cpufreq_hw_params' parameters table, + * fills it and returns it to the consumer, ready to get sent to the HW. + * Since the APM threshold is just one + * Freeing the table after usage is left to the caller. + * + * Returns: Zero for success, otherwise negative value on errors. + */ +static int qcom_cpufreq_gen_params(struct device *cpu_dev, + struct qcom_cpufreq_data *data, + struct qcom_cpufreq_hw_params **hw_tbl, + int *apm_vc, int *acc_vc, int cpu_count, + u8 *num_entries) +{ + struct device **genpd_cpr_vdev; + struct platform_device *pdev = cpufreq_get_driver_data(); + const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; + struct cpr_ext_data *cpr_data; + struct dev_pm_opp *genpd_opp; + unsigned long rate; + int apm_uV, acc_uV, i, gpd_opp_cnt, ret = 0; + + ret = devm_pm_opp_attach_genpd(cpu_dev, cprh_genpd_names, &genpd_cpr_vdev); + if (ret) { + dev_err(&pdev->dev, "Could not attach to pm_domain: %d\n", ret); + return ret; + } + + if (IS_ERR_OR_NULL(*genpd_cpr_vdev)) + return -EINVAL; + + /* + * In the CPR3 driver we have assigned data to the genpd newly created + * virtual device: this contains MEMACC and APM thresholds, as passing + * them through OPPs would be an API abuse. + */ + cpr_data = dev_get_drvdata(*genpd_cpr_vdev); + if (cpr_data == NULL) { + dev_err(&pdev->dev, "Cannot get CPR data\n"); + return -ENODATA; + } + + /* Get the count of available OPPs coming from the power domain */ + gpd_opp_cnt = dev_pm_opp_get_opp_count(cpu_dev); + if (gpd_opp_cnt < 2) { + ret = gpd_opp_cnt > 0 ? -EINVAL : gpd_opp_cnt; + goto detach_gpd; + } + + /* If we get no APM voltage, the system is going to be unstable */ + apm_uV = cpr_data->apm_threshold_uV; + if (apm_uV <= 0) { + ret = -EINVAL; + goto detach_gpd; + } + + /* + * Set apm_vc to a less than zero value: this is used later in the + * logic making sure that we're returning the right virtual corner + * for APM switch. + */ + *apm_vc = -1; + + /* + * Get the ACC threshold voltage: this is optional and not every + * SoC, or every SoC version, or every binning, needs it. + */ + if (cpr_data->mem_acc_threshold_uV <= 0) { + acc_uV = INT_MAX; + *acc_vc = U8_MAX; + } else { + acc_uV = cpr_data->mem_acc_threshold_uV; + *acc_vc = -1; + } + + *hw_tbl = devm_kmalloc_array(&pdev->dev, gpd_opp_cnt, + sizeof(**hw_tbl), GFP_KERNEL); + if (!hw_tbl) { + ret = -ENOMEM; + goto detach_gpd; + } + + for (i = 0, rate = 1000; i <= gpd_opp_cnt ; rate++, i++) { + struct qcom_cpufreq_hw_params *entry = *hw_tbl + i; + struct device_node *np; + u32 pll_div, millivolts, f_src; + + /* + * Find the next enabled OPP's frequency (ignores APM/ACC). + * + * We expect to get an error when we try to go past the last + * defined frequency, so we quit the loop gracefully without + * signaling any error, as this is the expected behavior. + */ + genpd_opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); + if (IS_ERR(genpd_opp)) + break; + + /* Get mandatory and optional properties from the OPP DT */ + np = dev_pm_opp_get_of_node(genpd_opp); + if (!np) { + ret = -ENOENT; + goto detach_gpd; + } + + if (of_property_read_u32(np, "qcom,pll-override", + &entry->override_val)) { + ret = -EINVAL; + of_node_put(np); + goto detach_gpd; + } + + if (of_property_read_u32(np, "qcom,spare-data", + &entry->spare_val)) + entry->spare_val = 0; + + if (of_property_read_u32(np, "qcom,pll-div", &pll_div)) + pll_div = 0; + + of_node_put(np); + + /* Get voltage in microvolts, then convert to millivolts */ + millivolts = dev_pm_opp_get_voltage(genpd_opp); + if (millivolts >= apm_uV && *apm_vc < 0) + *apm_vc = i; + if (millivolts >= acc_uV && *acc_vc < 0) + *acc_vc = i; + + millivolts /= 1000; + + if (millivolts < 150 || millivolts > 1400) { + dev_err(&pdev->dev, + "Read invalid voltage: %u.\n", millivolts); + return -EINVAL; + } + + /* In the OSM firmware, "Virtual Corner" levels start from 0 */ + entry->volt_lut_val = FIELD_PREP(LUT_VOLT_VC, i); + entry->volt_lut_val |= FIELD_PREP(LUT_VOLT, millivolts); + + /* + * Only the first frequency has alternate source, as it is + * always that one that is used for low power idle states. + */ + f_src = i ? 1 : 0; + f_src <<= ffs(soc_data->reg_freq_lut_src_mask) - 1; + entry->freq_lut_val = f_src | div_u64(rate, xo_rate); + entry->freq_lut_val |= FIELD_PREP(LUT_CORE_COUNT, cpu_count); + + /* + * PLL divider is not always 0 and there is no way to determine + * it automatically, as setting this value higher than DIV1 + * will make the OSM HW to effectively set the PLL at 2-4x + * the CPU frequency and then divide the CPU clock by this div, + * so this value is effectively used as both a multiplier and + * divider. + * This value cannot be calculated because it depends on + * manual calibration and is (most probably) used to choose + * a PLL frequency that gives the least possible jitter. + */ + entry->freq_lut_val |= FIELD_PREP(LUT_PLL_DIV, pll_div); + + dev_dbg(&pdev->dev, + "[%d] freq=0x%x volt=0x%x override=0x%x spare=0x%x\n", + i, entry->freq_lut_val, entry->volt_lut_val, + entry->override_val, entry->spare_val); + dev_pm_opp_put(genpd_opp); + genpd_opp = NULL; + } + + /* + * If we've got a customized mem-acc corner but we couldn't + * find any suitable crossover, or the corner is less than + * the minimum amount of required corners for mem-acc scaling, + * the values are not valid, hence fall back to LUT values. + */ + if (acc_uV != INT_MAX && *acc_vc < SEQ_MEM_ACC_MAX_LEVELS - 1) { + dev_dbg(&pdev->dev, + "MEM-ACC corner: invalid values VC%d %duV\n", + *acc_vc, acc_uV); + *acc_vc = U8_MAX; + } + + /* + * If we have probed less params than what we need, then the + * OPP table that we got from the genpd is malformed for some + * reason: in this case, do not apply the table to the HW. + */ + if (i < gpd_opp_cnt) { + dev_err(&pdev->dev, "Got bad OPP table from power domain.\n"); + ret = -EINVAL; + goto detach_gpd; + } + *num_entries = i; + +detach_gpd: + return ret; +} + +static inline u32 qcom_cpufreq_acd_regbit(u8 acd_reg_offset) +{ + return BIT(acd_reg_offset / 4); +} + +static int qcom_cpufreq_hw_acd_write_autoxfer(struct qcom_cpufreq_data *data, + void __iomem *acd_base, u32 val) +{ + const struct qcom_cpufreq_soc_data *sdata = data->soc_data; + const struct qcom_cpufreq_soc_acd_data *aregs = &sdata->acd_data; + u32 regval = 0; + + writel(val, acd_base + aregs->auto_xfer_cfg_reg); + + /* (Clear, then) Set AUTOXFER START */ + writel(0, acd_base + aregs->auto_xfer_reg); + writel(1, acd_base + aregs->auto_xfer_reg); + + /* Poll for status: if the first bit is set the transfer is done. */ + return readl_poll_timeout(acd_base + aregs->auto_xfer_sts_reg, regval, + regval & BIT(0), 1, 3); +} + +static int qcom_cpufreq_hw_acd_write_xfer(struct qcom_cpufreq_data *data, + void __iomem *acd_base, u8 reg, + u32 val) +{ + const struct qcom_cpufreq_soc_data *sdata = data->soc_data; + const struct qcom_cpufreq_soc_acd_data *aregs = &sdata->acd_data; + u32 regval = 0; + + /* Write to the register, then initiate manual transfer */ + writel(val, acd_base + reg); + + /* Clear write control register */ + writel(0, acd_base + aregs->write_ctl_reg); + + regval = (reg / 4) << ACD_WRITE_CTL_SELECT_SHIFT; + regval |= ACD_WRITE_CTL_UPDATE_EN; + writel(regval, acd_base + aregs->write_ctl_reg); + + /* Wait until ACD Local Transfer is done */ + return readl_poll_timeout(acd_base + aregs->write_sts_reg, regval, + regval & qcom_cpufreq_acd_regbit(reg), 1, 3); +} + +/** + * qcom_cpufreq_hw_acd_init() - Initialize ACD params in the OSM + * @cpu_dev: CPU device + * @policy: CPUFreq policy structure + * @index: Instance number (CPU cluster number) + * + * On some SoCs it is required to send the ACD configuration parameters + * to the OSM. This function takes the parameters from the SoC specific + * configuration and writes them only if a "osm-acdN" iospace has been + * declared (hence, it's present). + * + * Returns: Zero for success, otherwise negative number on error. + */ +static int qcom_cpufreq_hw_acd_init(struct device *cpu_dev, + struct cpufreq_policy *policy, + int index) +{ + struct platform_device *pdev = cpufreq_get_driver_data(); + struct qcom_cpufreq_data *ddata = policy->driver_data; + const struct qcom_cpufreq_soc_data *sdata = ddata->soc_data; + const struct qcom_cpufreq_soc_acd_data *aregs = &sdata->acd_data; + char acd_resname[] = "osm-acdX"; + void __iomem *acd_base; + u32 rmask; + int ret; + + snprintf(acd_resname, sizeof(acd_resname), "osm-acd%d", index); + + acd_base = devm_platform_ioremap_resource_byname(pdev, acd_resname); + if (IS_ERR(acd_base)) { + dev_vdbg(cpu_dev, "Skipping ACD initialization.\n"); + return 0; + } + + writel(aregs->tl_delay_val, acd_base + aregs->tl_delay_reg); + writel(aregs->acd_ctrl_val, acd_base + aregs->acd_ctrl_reg); + writel(aregs->softstart_val, acd_base + aregs->softstart_reg); + writel(aregs->ext_intf0_val, acd_base + aregs->ext_intf_reg); + writel(aregs->auto_xfer_val, acd_base + aregs->auto_xfer_ctl_reg); + + rmask = qcom_cpufreq_acd_regbit(aregs->acd_ctrl_reg) | + qcom_cpufreq_acd_regbit(aregs->tl_delay_reg) | + qcom_cpufreq_acd_regbit(aregs->softstart_reg) | + qcom_cpufreq_acd_regbit(aregs->ext_intf_reg); + ret = qcom_cpufreq_hw_acd_write_autoxfer(ddata, acd_base, rmask); + if (ret) + return ret; + + /* Switch CPUSS clock source to ACD clock */ + ret = qcom_cpufreq_hw_acd_write_xfer(ddata, acd_base, + aregs->gfmux_cfg_reg, 1); + if (ret) + return ret; + + /* (Set, then) Clear DCVS_SW */ + ret = qcom_cpufreq_hw_acd_write_xfer(ddata, acd_base, + aregs->dcvs_sw_reg, 1); + if (ret) + return ret; + ret = qcom_cpufreq_hw_acd_write_xfer(ddata, acd_base, + aregs->dcvs_sw_reg, 0); + if (ret) + return ret; + + /* Wait for clock switch time */ + udelay(1); + + /* Program the final ACD external interface */ + ret = qcom_cpufreq_hw_acd_write_xfer(ddata, acd_base, + aregs->ext_intf_reg, + aregs->ext_intf1_val); + if (ret) + return ret; + + /* Initiate transfer of the final ACD value */ + rmask |= qcom_cpufreq_acd_regbit(aregs->gfmux_cfg_reg); + writel(rmask, acd_base + aregs->auto_xfer_cfg_reg); + + /* Wait for ACD to stabilize. Same wait as the OSM boot time... */ + udelay(OSM_BOOT_TIME_US); + return 0; +} + +/** + * qcom_cpufreq_hw_write_lut() - Write Lookup Table params to the OSM + * @cpu_dev: CPU device + * @policy: CPUFreq policy structure + * @cpu_count: Number of CPUs in the frequency domain + * @index: Instance number (CPU cluster number) + * + * Program all the Lookup Table (LUT) entries and related thresholds + * to the Operating State Manager on platforms where the same hasn't + * been done already by the bootloader or TrustZone before booting + * the operating system's kernel; + * On these platforms, write access to the OSM is (obviously) not + * blocked by the hypervisor. + * + * Returns: Zero for success, otherwise negative number on error. + */ +static int qcom_cpufreq_hw_write_lut(struct device *cpu_dev, + struct cpufreq_policy *policy, + int cpu_count, int index) +{ + struct platform_device *pdev = cpufreq_get_driver_data(); + struct qcom_cpufreq_data *ddata = policy->driver_data; + const struct qcom_cpufreq_soc_data *sdata = ddata->soc_data; + const struct qcom_cpufreq_soc_setup_data *sregs = &sdata->setup_regs; + struct qcom_cpufreq_hw_params *hw_tbl; + struct resource *osm_rsrc; + char osm_resname[] = "osm-domainX"; + u32 sreg, seq_addr, acc_lval = 0, last_spare = 1; + u8 num_entries = 0; + int apm_vc = INT_MAX, acc_vc = U8_MAX, acc_idx = 0; + int acc_val[SEQ_MEM_ACC_MAX_LEVELS], i, ret; + + snprintf(osm_resname, sizeof(osm_resname), "osm-domain%d", index); + + /* + * On some SoCs the OSM is not getting programmed from bootloader + * and needs to be done here: in this case, we need to retrieve + * the base physical address for the "Sequencer", so we will get + * the OSM base phys and apply the sequencer offset. + * + * Note: We are not remapping this iospace because we are really + * sending the physical address through SCM calls later. + */ + osm_rsrc = platform_get_resource_byname(pdev, IORESOURCE_MEM, osm_resname); + if (!osm_rsrc) + return -ENODEV; + + seq_addr = osm_rsrc->start + sregs->reg_osm_sequencer; + + ret = qcom_cpufreq_gen_params(cpu_dev, ddata, &hw_tbl, &apm_vc, + &acc_vc, cpu_count, &num_entries); + if (ret) + return ret; + + /* If we get less than 2 entries, scaling doesn't make sense */ + if (num_entries < 2) { + dev_err(&pdev->dev, "Not enough LUT entries found (%u)\n", num_entries); + return -EINVAL; + } + + for (i = 0; i < LUT_MAX_ENTRIES; i++) { + struct qcom_cpufreq_hw_params *entry; + int pos = i * sdata->lut_row_size; + + /* + * If we have reached the end of the params table, write + * the last valid entry until the end of the OSM table. + */ + if (i < num_entries) + entry = &hw_tbl[i]; + else + entry = &hw_tbl[num_entries - 1]; + + writel(i, ddata->base + sdata->reg_index + pos); + writel(entry->volt_lut_val, ddata->base + sdata->reg_volt_lut + pos); + writel(entry->freq_lut_val, ddata->base + sdata->reg_freq_lut + pos); + writel(entry->override_val, ddata->base + sregs->reg_override + pos); + writel(entry->spare_val, ddata->base + sregs->reg_spare + pos); + + dev_dbg(cpu_dev, "Writing [%d] v:0x%x f:0x%x ovr:0x%x s:0x%x\n", i, + entry->volt_lut_val, entry->freq_lut_val, + entry->override_val, entry->spare_val); + + /* + * MEM-ACC Virtual Corner threshold voltage: this gets set + * as the pairs of corners in which there is a transition + * between one MEM-ACC level and the next one. + * + * Notes: The spare_val can never be zero; + * The first spare_val is always 1; + * The maximum number of pairs is two (four registers). + * + * Example: (C = Corner Level - M = MEM-ACC Level) + * C0 M1 - C1 M1 - C2 M2 - C3 M2 - C4 M2 - C5 M3 + * Pairs: 1-2, 4-5 + */ + if (entry->spare_val <= last_spare || + acc_idx >= SEQ_MEM_ACC_MAX_LEVELS - 1) + continue; + + /* Standard mem-acc pairs using spare_val LUT crossovers */ + last_spare = entry->spare_val; + acc_val[acc_idx] = i - 1; + acc_idx++; + acc_val[acc_idx] = i; + acc_idx++; + } + + /* Sanity check: we *must* have two mem-acc crossovers (four values) */ + if (acc_idx < SEQ_MEM_ACC_MAX_LEVELS - 1) + return -EINVAL; + + /* + * Customized mem-acc corners, if any; in this case, the last corner + * in the external (CPRh) LUT is this one, placed after the APM one. + */ + if (acc_vc > 0 && acc_vc != U8_MAX) { + sreg = SEQUENCER_REG(seq_addr, SEQ_MEM_ACC_CROSSOVER_VC); + ret = qcom_scm_io_writel(sreg, num_entries + 1); + if (ret) + return ret; + + /* + * At the price of very-slightly higher power consumption, + * switch the ACC at one corner lower than what we've found, + * as this seems to be needed on at least some MSM8998 chips + * to achieve full system stability + */ + acc_vc--; + + /* Change only if we have to move the corner down */ + if (acc_vc < acc_val[3]) { + acc_val[2] = acc_vc - 1; + acc_val[3] = acc_vc; + } + + /* If needed, sanitize previously stored vals from the LUT */ + if (acc_val[2] <= acc_val[1]) + acc_val[1] = acc_val[2] - 1; + if (acc_val[1] <= acc_val[0]) + acc_val[0] = acc_val[1] - 1; + } + + for (i = 0; i < SEQ_MEM_ACC_MAX_LEVELS; i++) { + ret = qcom_scm_io_writel(SEQ_MEMACC_REG(seq_addr, i), acc_val[i]); + if (ret) + return ret; + } + dev_dbg(cpu_dev, "Wrote MEM-ACC Pairs: [%u-%u] [%u-%u]\n", + acc_val[0], acc_val[1], acc_val[2], acc_val[3]); + + /* + * Program the L_VAL of the first corner requesting MEM-ACC + * voltage level 3 to the right sequencer register + */ + acc_lval = FIELD_GET(LUT_L_VAL, hw_tbl[acc_val[3]].freq_lut_val); + ret = qcom_scm_io_writel(SEQUENCER_REG(seq_addr, SEQ_MEM_ACC_LVAL), acc_lval); + if (ret) { + dev_dbg(cpu_dev, "Cannot send memacc l_val\n"); + return ret; + } + dev_dbg(cpu_dev, "MEM-ACC L-Val is %u\n", acc_lval); + + /* + * Array Power Mux threshold level: the first virtual corner + * that requires a switch sequence of the APM from MX to APC. + */ + if (apm_vc == INT_MAX) + apm_vc = LUT_MAX_ENTRIES - 1; + + /* + * APM crossover virtual corner refers to CPRh: there, the APM corner + * is always appended to the table (so, at the end of it, right after + * the cluster dvfs entries). + */ + writel(num_entries, ddata->base + sregs->reg_seq1); + ret = qcom_scm_io_writel(SEQUENCER_REG(seq_addr, SEQ_APM_CROSSOVER_VC), num_entries); + if (ret) + return ret; + + ret = qcom_scm_io_writel(SEQUENCER_REG(seq_addr, SEQ_APM_THRESH_VC), apm_vc); + if (ret) + return ret; + + ret = qcom_scm_io_writel(SEQUENCER_REG(seq_addr, SEQ_APM_THRESH_PREVC), apm_vc - 1); + if (ret) + return ret; + + ret = qcom_scm_io_writel(SEQUENCER_REG(seq_addr, SEQ_APM_PARAM), + (0x39 | apm_vc << 6)); + if (ret) + return ret; + dev_dbg(cpu_dev, "Wrote APM Pair: [%u-%u]\n", apm_vc - 1, apm_vc); + + /* + * We succeeded! Dispose of the table that got allocated during + * qcom_cpufreq_gen_params, as that contains parameters that are + * relevant only to the context of OSM programming, which is done + * only once. + */ + if (hw_tbl) + devm_kfree(&pdev->dev, hw_tbl); + + return 0; +} + /** * qcom_cpufreq_hw_read_lut() - Read Lookup Table from the OSM * @cpu_dev: CPU device @@ -230,14 +1022,16 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, } for (i = 0; i < LUT_MAX_ENTRIES; i++) { - data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + - i * soc_data->lut_row_size); - src = FIELD_GET(LUT_SRC, data); + data = readl(drv_data->base + soc_data->reg_freq_lut + + i * soc_data->lut_row_size); + src = data & soc_data->reg_freq_lut_src_mask; + src >>= ffs(soc_data->reg_freq_lut_src_mask) - 1; + lval = FIELD_GET(LUT_L_VAL, data); core_count = FIELD_GET(LUT_CORE_COUNT, data); - data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + - i * soc_data->lut_row_size); + data = readl(drv_data->base + soc_data->reg_volt_lut + + i * soc_data->lut_row_size); volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) @@ -275,8 +1069,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; } else { - dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", - freq); + dev_warn(cpu_dev, "can't update OPP for freq=%u\n", freq); } } @@ -297,11 +1090,14 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, * qcom_get_related_cpus - Get mask of CPUs in the same frequency domain * @index: CPU number * @m: Returned CPU mask + * + * Returns: Count of CPUs inserted in the cpumask or negative number for error. */ -static void qcom_get_related_cpus(int index, struct cpumask *m) +static int qcom_get_related_cpus(int index, struct cpumask *m) { struct device_node *cpu_np; struct of_phandle_args args; + int count = 0; int cpu, ret; for_each_possible_cpu(cpu) { @@ -310,15 +1106,18 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) continue; ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", - "#freq-domain-cells", 0, - &args); + "#freq-domain-cells", 0, &args); of_node_put(cpu_np); if (ret < 0) continue; - if (index == args.args[0]) + if (index == args.args[0]) { cpumask_set_cpu(cpu, m); + count++; + } } + + return count > 0 ? count : -EINVAL; } static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) @@ -397,22 +1196,91 @@ static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x110, + .reg_freq_lut_src_mask = LUT_SRC_845, .reg_volt_lut = 0x114, .reg_current_vote = 0x704, .reg_perf_state = 0x920, .lut_row_size = 32, + .clk_hw_div = 2, + .uses_tz = true, +}; + +static const struct qcom_cpufreq_soc_data msm8998_soc_data = { + .reg_enable = 0x4, + .reg_index = 0x150, + .reg_freq_lut = 0x154, + .reg_freq_lut_src_mask = LUT_SRC_8998, + .reg_volt_lut = 0x158, + .reg_perf_state = 0xf10, + .lut_row_size = 32, + .clk_hw_div = 1, + .uses_tz = false, + .setup_regs = { + /* Physical offset for sequencer scm calls */ + .reg_osm_sequencer = 0x300, + + /* Frequency domain offsets */ + .reg_override = 0x15c, + .reg_spare = 0x164, + .reg_cc_zero_behav = 0x0c, + .reg_spm_cc_hyst = 0x1c, + .reg_spm_cc_dcvs_dis = 0x20, + .reg_spm_core_ret_map = 0x24, + .reg_llm_freq_vote_hyst = 0x2c, + .reg_llm_volt_vote_hyst = 0x30, + .reg_llm_intf_dcvs_dis = 0x34, + .reg_seq1 = 0x48, + .reg_pdn_fsm_ctrl = 0x70, + .reg_cc_boost_timer = 0x74, + .reg_dcvs_boost_timer = 0x84, + .reg_ps_boost_timer = 0x94, + .boost_timer_reg_len = 0x4, + .reg_boost_sync_delay = 0xa0, + .reg_droop_ctrl = 0xa4, + .reg_droop_release_ctrl = 0xa8, + .reg_droop_unstall_ctrl = 0xac, + .reg_droop_wait_release_ctrl = 0xb0, + .reg_droop_timer_ctrl = 0xb8, + .reg_droop_sync_delay = 0xbc, + .reg_pll_override = 0xc0, + .reg_cycle_counter = 0xf00, + }, + .acd_data = { + .acd_ctrl_reg = 0x4, + .tl_delay_reg = 0x8, + .softstart_reg = 0x28, + .ext_intf_reg = 0x30, + .dcvs_sw_reg = 0x34, + .gfmux_cfg_reg = 0x3c, + .auto_xfer_cfg_reg = 0x80, + .auto_xfer_reg = 0x84, + .auto_xfer_ctl_reg = 0x88, + .auto_xfer_sts_reg = 0x8c, + .write_ctl_reg = 0x90, + .write_sts_reg = 0x94, + .tl_delay_val = 38417, + .acd_ctrl_val = 0x2b5ffd, + .softstart_val = 0x501, + .ext_intf0_val = 0x2cf9ae8, + .ext_intf1_val = 0x2cf9afe, + .auto_xfer_val = 0x15, + }, }; static const struct qcom_cpufreq_soc_data epss_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x100, + .reg_freq_lut_src_mask = LUT_SRC_845, .reg_volt_lut = 0x200, .reg_perf_state = 0x320, .lut_row_size = 4, + .clk_hw_div = 2, + .uses_tz = true, }; static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, + { .compatible = "qcom,cpufreq-hw-8998", .data = &msm8998_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, {} }; @@ -469,6 +1337,130 @@ static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data) free_irq(data->throttle_irq, data); } +/** + * qcom_cpufreq_hw_osm_setup() - Setup and enable the OSM + * @cpu_dev: CPU device + * @policy: CPUFreq policy structure + * @cpu_count: Number of CPUs in the frequency domain + * + * On some platforms, the Operating State Manager (OSM) is not getting + * programmed by the bootloader, nor by TrustZone before booting the OS + * and its register space is not write-protected by the hypervisor. + * In this case, to achieve CPU DVFS, it is needed to program it from + * the OS itself, which includes setting LUT and all the various tunables + * that are required for it to manage the CPU frequencies and voltages + * on its own. + * Calling this function on a platform that had the OSM set-up by TZ + * will result in a hypervisor fault with system reboot in most cases. + * + * Returns: Zero for success, otherwise negative number on errors. + */ +static int qcom_cpufreq_hw_osm_setup(struct device *cpu_dev, + struct cpufreq_policy *policy, + int cpu_count, int index) +{ + struct qcom_cpufreq_data *drv_data = policy->driver_data; + const struct qcom_cpufreq_soc_setup_data *setup_regs; + u32 val; + int ret; + + ret = qcom_cpufreq_hw_write_lut(cpu_dev, policy, cpu_count, index); + if (ret) + return ret; + + setup_regs = &drv_data->soc_data->setup_regs; + + /* Set OSM to XO clock ratio and use XO edge for the cycle counter */ + val = FIELD_PREP(CYCLE_COUNTER_CLK_RATIO, OSM_XO_RATIO_VAL); + val |= CYCLE_COUNTER_USE_XO_EDGE; + + /* Enable the CPU cycle counter */ + val |= BIT(0); + writel(val, drv_data->base + setup_regs->reg_cycle_counter); + + /* CoreCount DCVS Policy: Wait time for frequency inc/decrement */ + val = FIELD_PREP(HYSTERESIS_UP_MASK, HYSTERESIS_CC_NS); + val |= FIELD_PREP(HYSTERESIS_DN_MASK, HYSTERESIS_CC_NS); + writel(val, drv_data->base + setup_regs->reg_spm_cc_hyst); + + /* Set the frequency index 0 and override for cluster power collapse */ + writel(BIT(0), drv_data->base + setup_regs->reg_cc_zero_behav); + + /* Treat cores in retention as active */ + writel(0, drv_data->base + setup_regs->reg_spm_core_ret_map); + + /* Enable CoreCount based DCVS */ + writel(0, drv_data->base + setup_regs->reg_spm_cc_dcvs_dis); + + /* CoreCount DCVS-LLM Policy: Wait time for frequency inc/decrement */ + val = FIELD_PREP(HYSTERESIS_UP_MASK, HYSTERESIS_LLM_NS); + val |= FIELD_PREP(HYSTERESIS_DN_MASK, HYSTERESIS_LLM_NS); + writel(val, drv_data->base + setup_regs->reg_llm_freq_vote_hyst); + + /* CoreCount DCVS-LLM Policy: Wait time for voltage inc/decrement */ + val = FIELD_PREP(HYSTERESIS_UP_MASK, HYSTERESIS_LLM_NS); + val |= FIELD_PREP(HYSTERESIS_DN_MASK, HYSTERESIS_LLM_NS); + writel(val, drv_data->base + setup_regs->reg_llm_volt_vote_hyst); + + /* Enable LLM frequency+voltage voting */ + writel(0, drv_data->base + setup_regs->reg_llm_intf_dcvs_dis); + + /* Setup Boost FSM Timers */ + qcom_cpufreq_hw_boost_setup(drv_data->base + setup_regs->reg_cc_boost_timer, + setup_regs->boost_timer_reg_len); + qcom_cpufreq_hw_boost_setup(drv_data->base + setup_regs->reg_dcvs_boost_timer, + setup_regs->boost_timer_reg_len); + qcom_cpufreq_hw_boost_setup(drv_data->base + setup_regs->reg_ps_boost_timer, + setup_regs->boost_timer_reg_len); + + /* PLL signal timing control for Boost */ + writel(BOOST_SYNC_DELAY, drv_data->base + setup_regs->reg_boost_sync_delay); + + /* Setup WFx and PC/RET droop unstall */ + val = FIELD_PREP(DROOP_TIMER1, DROOP_TIMER_NS); + val |= FIELD_PREP(DROOP_TIMER0, DROOP_TIMER_NS); + writel(val, drv_data->base + setup_regs->reg_droop_unstall_ctrl); + + /* Setup WFx and PC/RET droop wait-to-release */ + val = FIELD_PREP(DROOP_TIMER1, DROOP_WAIT_RELEASE_TIMER_NS); + val |= FIELD_PREP(DROOP_TIMER0, DROOP_WAIT_RELEASE_TIMER_NS); + writel(val, drv_data->base + setup_regs->reg_droop_wait_release_ctrl); + + /* PLL signal timing control for Droop */ + writel(1, drv_data->base + setup_regs->reg_droop_sync_delay); + + /* Setup DCVS timers */ + writel(DROOP_RELEASE_TIMER_NS, + drv_data->base + setup_regs->reg_droop_release_ctrl); + writel(DROOP_TIMER_NS, drv_data->base + setup_regs->reg_droop_timer_ctrl); + + /* Setup Droop control */ + val = readl(drv_data->base + setup_regs->reg_droop_ctrl); + val |= DROOP_CTRL_VAL; + writel(val, drv_data->base + setup_regs->reg_droop_ctrl); + + /* Enable CC-Boost, DCVS-Boost, PS-Boost, WFx, PC/RET, DCVS FSM */ + val = readl(drv_data->base + setup_regs->reg_pdn_fsm_ctrl); + val |= CC_BOOST_EN | PS_BOOST_EN | DCVS_BOOST_EN; + val |= WFX_DROOP_EN | PC_RET_EXIT_DROOP_EN | DCVS_DROOP_EN; + writel(val, drv_data->base + setup_regs->reg_pdn_fsm_ctrl); + + /* Enable PLL Droop Override */ + val = PLL_OVERRIDE_DROOP_EN; + writel(val, drv_data->base + setup_regs->reg_pll_override); + + /* Initialize the Adaptive Clock Distribution */ + ret = qcom_cpufreq_hw_acd_init(cpu_dev, policy, index); + if (ret) + return ret; + + /* We're ready: enable the OSM and give it time to boot (5uS) */ + writel(1, drv_data->base + drv_data->soc_data->reg_enable); + udelay(OSM_BOOT_TIME_US); + + return 0; +} + static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct platform_device *pdev = cpufreq_get_driver_data(); @@ -479,7 +1471,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct resource *res; void __iomem *base; struct qcom_cpufreq_data *data; - int ret, index; + char fdom_resname[] = "freq-domainX"; + int cpu_count, index, ret; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -500,7 +1493,9 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) index = args.args[0]; - res = platform_get_resource(pdev, IORESOURCE_MEM, index); + snprintf(fdom_resname, sizeof(fdom_resname), "freq-domain%d", index); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, fdom_resname); if (!res) { dev_err(dev, "failed to get mem resource %d\n", index); return -ENODEV; @@ -628,9 +1623,50 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = { static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + const struct qcom_cpufreq_soc_data *soc_data; + struct device_node *pd_node; + struct platform_device *pd_dev; struct device *cpu_dev; struct clk *clk; - int ret; + int clk_div, ret; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) + return -EPROBE_DEFER; + + soc_data = of_device_get_match_data(&pdev->dev); + if (!soc_data) + return -EINVAL; + + if (!soc_data->uses_tz) { + /* + * When the OSM is not pre-programmed from TZ, we will + * need to program the sequencer through SCM calls. + */ + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + + /* + * If there are no power-domains, OSM programming cannot be + * performed, as in that case, we wouldn't know where to take + * the params from... + */ + pd_node = of_parse_phandle(cpu_dev->of_node, "power-domains", 0); + if (!pd_node) { + ret = PTR_ERR(pd_node); + dev_err(cpu_dev, "power domain not found: %d\n", ret); + return ret; + } + + /* + * If the power domain device is not registered yet, then + * defer probing this driver until that is available. + */ + pd_dev = of_find_device_by_node(pd_node); + if (!pd_dev || !pd_dev->dev.driver || + !device_is_bound(&pd_dev->dev)) + return -EPROBE_DEFER; + } clk = clk_get(&pdev->dev, "xo"); if (IS_ERR(clk)) @@ -643,16 +1679,16 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); - cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; + clk_div = soc_data->clk_hw_div; + if (clk_div == 0) + clk_div++; + + cpu_hw_rate = clk_get_rate(clk) / clk_div; clk_put(clk); cpufreq_qcom_hw_driver.driver_data = pdev; /* Check for optional interconnect paths on CPU0 */ - cpu_dev = get_cpu_device(0); - if (!cpu_dev) - return -EPROBE_DEFER; - ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); if (ret) return ret; From 62c31274b5dd3924b26a3089722f8c6050237420 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 19 Jan 2021 13:03:11 +0100 Subject: [PATCH 060/174] cpufreq: qcom-hw: Allow getting the maximum transition latency for OPPs In order to fine-tune the frequency scaling from various governors, allow to set a maximum transition latency from OPPs, which may be different depending on the SoC. Signed-off-by: AngeloGioacchino Del Regno [Fixup for 5.15 by Jami] --- drivers/cpufreq/qcom-cpufreq-hw.c | 37 ++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index a0313398473f..e7e924fafc9d 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -1472,6 +1472,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) void __iomem *base; struct qcom_cpufreq_data *data; char fdom_resname[] = "freq-domainX"; + unsigned int transition_latency; int cpu_count, index, ret; cpu_dev = get_cpu_device(policy->cpu); @@ -1522,6 +1523,25 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->soc_data = of_device_get_match_data(&pdev->dev); data->base = base; data->res = res; + policy->driver_data = data; + + cpu_count = qcom_get_related_cpus(index, policy->cpus); + if (!cpumask_weight(policy->cpus)) { + dev_err(dev, "Domain-%d failed to get related CPUs\n", index); + ret = -ENOENT; + goto error; + } + + policy->dvfs_possible_from_any_cpu = true; + if (!data->soc_data->uses_tz) { + ret = qcom_cpufreq_hw_osm_setup(cpu_dev, policy, + cpu_count, index); + if (ret) { + dev_err(dev, "Cannot setup the OSM for CPU%d: %d\n", + policy->cpu, ret); + goto error; + } + } /* HW should be in enabled state to proceed */ if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { @@ -1530,16 +1550,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto error; } - qcom_get_related_cpus(index, policy->cpus); - if (!cpumask_weight(policy->cpus)) { - dev_err(dev, "Domain-%d failed to get related CPUs\n", index); - ret = -ENOENT; - goto error; - } - - policy->driver_data = data; - policy->dvfs_possible_from_any_cpu = true; - ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); @@ -1553,6 +1563,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto error; } + transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); + if (!transition_latency) + transition_latency = CPUFREQ_ETERNAL; + + policy->cpuinfo.transition_latency = transition_latency; + if (policy_has_boost_freq(policy)) { ret = cpufreq_enable_boost_support(); if (ret) @@ -1565,6 +1581,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) return 0; error: + policy->driver_data = NULL; kfree(data); unmap_base: iounmap(base); From f660d49d1aa62b0fd1cc0914d38e0230e70a9f55 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 9 Jan 2021 12:58:27 +0100 Subject: [PATCH 061/174] dt-bindings: cpufreq: qcom-hw: Add bindings for 8998 The OSM programming addition has been done under the qcom,cpufreq-hw-8998 compatible name: specify the requirement of two additional register spaces for this functionality. This implementation, with the same compatible, has been tested on MSM8998 and SDM630. Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 67 ++++++++++++++----- 1 file changed, 52 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index bc81b6203e27..29b663321a0b 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -18,6 +18,10 @@ description: | properties: compatible: oneOf: + - description: Non-secure v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw-8998 + - description: v1 of CPUFREQ HW items: - const: qcom,cpufreq-hw @@ -28,21 +32,9 @@ properties: - qcom,sm8250-cpufreq-epss - const: qcom,cpufreq-epss - reg: - minItems: 2 - maxItems: 3 - items: - - description: Frequency domain 0 register region - - description: Frequency domain 1 register region - - description: Frequency domain 2 register region + reg: {} - reg-names: - minItems: 2 - maxItems: 3 - items: - - const: freq-domain0 - - const: freq-domain1 - - const: freq-domain2 + reg-names: {} clocks: items: @@ -57,10 +49,55 @@ properties: '#freq-domain-cells': const: 1 +if: + properties: + compatible: + contains: + const: qcom,cpufreq-hw-8998 +then: + properties: + reg: + minItems: 2 + maxItems: 6 + items: + - description: Frequency domain 0 register region + - description: Operating State Manager domain 0 register region + - description: Frequency domain 1 register region + - description: Operating State Manager domain 1 register region + - description: PLL ACD domain 0 register region (if ACD programming required) + - description: PLL ACD domain 1 register region (if ACD programming required) + + reg-names: + minItems: 2 + maxItems: 6 + items: + - const: "osm-domain0" + - const: "freq-domain0" + - const: "osm-domain1" + - const: "freq-domain1" + - const: "osm-acd0" + - const: "osm-acd1" + +else: + properties: + reg: + minItems: 2 + maxItems: 3 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: "freq-domain0" + - const: "freq-domain1" + - const: "freq-domain2" + required: - compatible - reg - - reg-names - clocks - clock-names - '#freq-domain-cells' From b232c0dfd0315b6c595c4b037f3c3c5bce3aebb1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Jun 2021 23:05:40 +0200 Subject: [PATCH 062/174] dt-bindings: cpufreq: qcom-hw: Make reg-names a required property The property reg-names is required after the addition of the OSM programming sequence, as that mandates specifying different register domains; to avoid confusion and improve devicetree readability, specifying the regions names was made mandatory. --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 29b663321a0b..17fd6a6cefb0 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -98,6 +98,7 @@ else: required: - compatible - reg + - reg-names - clocks - clock-names - '#freq-domain-cells' From 3b78949610a058a35a7ab26baa19567e0225ec12 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 24 Nov 2020 20:31:05 +0100 Subject: [PATCH 063/174] soc: qcom: cpr: Move common functions to new file In preparation for implementing a new driver that will be handling CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new file. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for 5.15 & 5.17) --- drivers/soc/qcom/Makefile | 2 +- drivers/soc/qcom/cpr-common.c | 349 +++++++++++++++++++++++++++++ drivers/soc/qcom/cpr-common.h | 113 ++++++++++ drivers/soc/qcom/cpr.c | 408 +++------------------------------- 4 files changed, 490 insertions(+), 382 deletions(-) create mode 100644 drivers/soc/qcom/cpr-common.c create mode 100644 drivers/soc/qcom/cpr-common.h diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 70d5de69fd7b..bed55881dfd9 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -3,7 +3,7 @@ CFLAGS_rpmh-rsc.o := -I$(src) obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o -obj-$(CONFIG_QCOM_CPR) += cpr.o +obj-$(CONFIG_QCOM_CPR) += cpr-common.o cpr.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/cpr-common.c b/drivers/soc/qcom/cpr-common.c new file mode 100644 index 000000000000..540bb074358d --- /dev/null +++ b/drivers/soc/qcom/cpr-common.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpr-common.h" + +int cpr_populate_ring_osc_idx(struct device *dev, + struct fuse_corner *fuse_corner, + const struct cpr_fuse *cpr_fuse, + int num_fuse_corners) +{ + struct fuse_corner *end = fuse_corner + num_fuse_corners; + u32 data; + int ret; + + for (; fuse_corner < end; fuse_corner++, cpr_fuse++) { + ret = nvmem_cell_read_variable_le_u32(dev, cpr_fuse->ring_osc, &data); + if (ret) + return ret; + fuse_corner->ring_osc_idx = data; + } + + return 0; +} + +int cpr_read_fuse_uV(int init_v_width, int step_size_uV, int ref_uV, + int adj, int step_volt, const char *init_v_efuse, + struct device *dev) +{ + int steps, uV; + u32 bits = 0; + int ret; + + ret = nvmem_cell_read_variable_le_u32(dev, init_v_efuse, &bits); + if (ret) + return ret; + + steps = bits & (BIT(init_v_width - 1) - 1); + /* Not two's complement.. instead highest bit is sign bit */ + if (bits & BIT(init_v_width - 1)) + steps = -steps; + + uV = ref_uV + steps * step_size_uV; + + /* Apply open-loop fixed adjustments to fused values */ + uV += adj; + + return DIV_ROUND_UP(uV, step_volt) * step_volt; +} + +const struct cpr_fuse *cpr_get_fuses(struct device *dev, int tid, + int num_fuse_corners) +{ + struct cpr_fuse *fuses; + int i; + + fuses = devm_kcalloc(dev, num_fuse_corners, + sizeof(struct cpr_fuse), + GFP_KERNEL); + if (!fuses) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < num_fuse_corners; i++) { + char tbuf[50]; + + snprintf(tbuf, sizeof(tbuf), "cpr%d_ring_osc%d", tid, i + 1); + fuses[i].ring_osc = devm_kstrdup(dev, tbuf, GFP_KERNEL); + if (!fuses[i].ring_osc) + return ERR_PTR(-ENOMEM); + + snprintf(tbuf, sizeof(tbuf), + "cpr%d_init_voltage%d", tid, i + 1); + fuses[i].init_voltage = devm_kstrdup(dev, tbuf, + GFP_KERNEL); + if (!fuses[i].init_voltage) + return ERR_PTR(-ENOMEM); + + snprintf(tbuf, sizeof(tbuf), "cpr%d_quotient%d", tid, i + 1); + fuses[i].quotient = devm_kstrdup(dev, tbuf, GFP_KERNEL); + if (!fuses[i].quotient) + return ERR_PTR(-ENOMEM); + + snprintf(tbuf, sizeof(tbuf), + "cpr%d_quotient_offset%d", tid, i + 1); + fuses[i].quotient_offset = devm_kstrdup(dev, tbuf, + GFP_KERNEL); + if (!fuses[i].quotient_offset) + return ERR_PTR(-ENOMEM); + } + + return fuses; +} + +int cpr_populate_fuse_common(struct device *dev, + struct fuse_corner_data *fdata, + const struct cpr_fuse *cpr_fuse, + struct fuse_corner *fuse_corner, + int step_volt, int init_v_width, + int init_v_step) +{ + int uV, ret; + + /* Populate uV */ + uV = cpr_read_fuse_uV(init_v_width, init_v_step, + fdata->ref_uV, fdata->volt_oloop_adjust, + step_volt, cpr_fuse->init_voltage, dev); + if (uV < 0) + return uV; + + /* + * Update SoC voltages: platforms might choose a different + * regulators than the one used to characterize the algorithms + * (ie, init_voltage_step). + */ + fdata->min_uV = roundup(fdata->min_uV, step_volt); + fdata->max_uV = roundup(fdata->max_uV, step_volt); + + fuse_corner->min_uV = fdata->min_uV; + fuse_corner->max_uV = fdata->max_uV; + fuse_corner->uV = clamp(uV, fuse_corner->min_uV, fuse_corner->max_uV); + + /* Populate target quotient by scaling */ + ret = nvmem_cell_read_variable_le_u32(dev, cpr_fuse->quotient, &fuse_corner->quot); + if (ret) + return ret; + + fuse_corner->quot *= fdata->quot_scale; + fuse_corner->quot += fdata->quot_offset; + fuse_corner->quot += fdata->quot_adjust; + + return 0; +} + +/* + * Returns: Index of the initial corner or negative number for error. + */ +int cpr_find_initial_corner(struct device *dev, struct clk *cpu_clk, + struct corner *corners, int num_corners) +{ + unsigned long rate; + struct corner *iter, *corner; + const struct corner *end; + unsigned int ret = 0; + + if (!cpu_clk) + return -EINVAL; + + end = &corners[num_corners - 1]; + rate = clk_get_rate(cpu_clk); + + /* + * Some bootloaders set a CPU clock frequency that is not defined + * in the OPP table. When running at an unlisted frequency, + * cpufreq_online() will change to the OPP which has the lowest + * frequency, at or above the unlisted frequency. + * Since cpufreq_online() always "rounds up" in the case of an + * unlisted frequency, this function always "rounds down" in case + * of an unlisted frequency. That way, when cpufreq_online() + * triggers the first ever call to cpr_set_performance_state(), + * it will correctly determine the direction as UP. + */ + for (iter = corners; iter <= end; iter++) { + if (iter->freq > rate) + break; + ret++; + if (iter->freq == rate) { + corner = iter; + break; + } + if (iter->freq < rate) + corner = iter; + } + + if (!corner) { + dev_err(dev, "boot up corner not found\n"); + return -EINVAL; + } + + dev_dbg(dev, "boot up perf state: %u\n", ret); + + return ret; +} + +u32 cpr_get_fuse_corner(struct dev_pm_opp *opp, u32 tid) +{ + struct device_node *np; + u32 fc; + + np = dev_pm_opp_get_of_node(opp); + if (of_property_read_u32_index(np, "qcom,opp-fuse-level", tid, &fc)) { + pr_debug("%s: missing 'qcom,opp-fuse-level' property\n", + __func__); + fc = 0; + } + + of_node_put(np); + + return fc; +} + +unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, + struct device *cpu_dev) +{ + u64 rate = 0; + struct device_node *ref_np; + struct device_node *desc_np; + struct device_node *child_np = NULL; + struct device_node *child_req_np = NULL; + + desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); + if (!desc_np) + return 0; + + ref_np = dev_pm_opp_get_of_node(ref); + if (!ref_np) + goto out_ref; + + do { + of_node_put(child_req_np); + child_np = of_get_next_available_child(desc_np, child_np); + child_req_np = of_parse_phandle(child_np, "required-opps", 0); + } while (child_np && child_req_np != ref_np); + + if (child_np && child_req_np == ref_np) + of_property_read_u64(child_np, "opp-hz", &rate); + + of_node_put(child_req_np); + of_node_put(child_np); + of_node_put(ref_np); +out_ref: + of_node_put(desc_np); + + return (unsigned long) rate; +} + +int cpr_calculate_scaling(const char *quot_offset, + struct device *dev, + const struct fuse_corner_data *fdata, + const struct corner *corner) +{ + u32 quot_diff = 0; + unsigned long freq_diff; + int scaling; + const struct fuse_corner *fuse, *prev_fuse; + int ret; + + fuse = corner->fuse_corner; + prev_fuse = fuse - 1; + + if (quot_offset) { + ret = nvmem_cell_read_variable_le_u32(dev, quot_offset, "_diff); + if (ret) + return ret; + + quot_diff *= fdata->quot_offset_scale; + quot_diff += fdata->quot_offset_adjust; + } else { + quot_diff = fuse->quot - prev_fuse->quot; + } + + freq_diff = fuse->max_freq - prev_fuse->max_freq; + freq_diff /= 1000000; /* Convert to MHz */ + scaling = 1000 * quot_diff / freq_diff; + return min(scaling, fdata->max_quot_scale); +} + +int cpr_interpolate(const struct corner *corner, int step_volt, + const struct fuse_corner_data *fdata) +{ + unsigned long f_high, f_low, f_diff; + int uV_high, uV_low, uV; + u64 temp, temp_limit; + const struct fuse_corner *fuse, *prev_fuse; + + fuse = corner->fuse_corner; + prev_fuse = fuse - 1; + + f_high = fuse->max_freq; + f_low = prev_fuse->max_freq; + uV_high = fuse->uV; + uV_low = prev_fuse->uV; + f_diff = fuse->max_freq - corner->freq; + + /* + * Don't interpolate in the wrong direction. This could happen + * if the adjusted fuse voltage overlaps with the previous fuse's + * adjusted voltage. + */ + if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq) + return corner->uV; + + temp = f_diff * (uV_high - uV_low); + temp = div64_ul(temp, f_high - f_low); + + /* + * max_volt_scale has units of uV/MHz while freq values + * have units of Hz. Divide by 1000000 to convert to. + */ + temp_limit = f_diff * fdata->max_volt_scale; + do_div(temp_limit, 1000000); + + uV = uV_high - min(temp, temp_limit); + return roundup(uV, step_volt); +} + +int cpr_check_vreg_constraints(struct device *dev, struct regulator *vreg, + struct fuse_corner *f) +{ + int ret; + + ret = regulator_is_supported_voltage(vreg, f->min_uV, f->min_uV); + if (!ret) { + dev_err(dev, "min uV: %d not supported by regulator\n", + f->min_uV); + return -EINVAL; + } + + ret = regulator_is_supported_voltage(vreg, f->max_uV, f->max_uV); + if (!ret) { + dev_err(dev, "max uV: %d not supported by regulator\n", + f->max_uV); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/soc/qcom/cpr-common.h b/drivers/soc/qcom/cpr-common.h new file mode 100644 index 000000000000..83a1f7c941b8 --- /dev/null +++ b/drivers/soc/qcom/cpr-common.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include +#include +#include +#include + +enum voltage_change_dir { + NO_CHANGE, + DOWN, + UP, +}; + +struct fuse_corner_data { + int ref_uV; + int max_uV; + int min_uV; + int range_uV; + /* fuse volt: closed/open loop */ + int volt_cloop_adjust; + int volt_oloop_adjust; + int max_volt_scale; + int max_quot_scale; + /* fuse quot */ + int quot_offset; + int quot_scale; + int quot_adjust; + /* fuse quot_offset */ + int quot_offset_scale; + int quot_offset_adjust; +}; + +struct cpr_fuse { + char *ring_osc; + char *init_voltage; + char *quotient; + char *quotient_offset; +}; + +struct fuse_corner { + int min_uV; + int max_uV; + int uV; + int quot; + int step_quot; + const struct reg_sequence *accs; + int num_accs; + unsigned long max_freq; + u8 ring_osc_idx; +}; + +struct corner { + int min_uV; + int max_uV; + int uV; + int last_uV; + int quot_adjust; + u32 save_ctl; + u32 save_irq; + unsigned long freq; + bool is_open_loop; + struct fuse_corner *fuse_corner; +}; + +struct corner_data { + unsigned int fuse_corner; + unsigned long freq; +}; + +struct acc_desc { + unsigned int enable_reg; + u32 enable_mask; + + struct reg_sequence *config; + struct reg_sequence *settings; + int num_regs_per_fuse; +}; + +struct cpr_acc_desc { + const struct cpr_desc *cpr_desc; + const struct acc_desc *acc_desc; +}; + + +int cpr_read_efuse(struct device *dev, const char *cname, u32 *data); +int cpr_populate_ring_osc_idx(struct device *dev, + struct fuse_corner *fuse_corner, + const struct cpr_fuse *cpr_fuse, + int num_fuse_corners); +int cpr_read_fuse_uV(int init_v_width, int step_size_uV, int ref_uV, + int adj, int step_volt, const char *init_v_efuse, + struct device *dev); +const struct cpr_fuse *cpr_get_fuses(struct device *dev, int tid, + int num_fuse_corners); +int cpr_populate_fuse_common(struct device *dev, + struct fuse_corner_data *fdata, + const struct cpr_fuse *cpr_fuse, + struct fuse_corner *fuse_corner, + int step_volt, int init_v_width, + int init_v_step); +int cpr_find_initial_corner(struct device *dev, struct clk *cpu_clk, + struct corner *corners, int num_corners); +u32 cpr_get_fuse_corner(struct dev_pm_opp *opp, u32 tid); +unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, + struct device *cpu_dev); +int cpr_calculate_scaling(const char *quot_offset, + struct device *dev, + const struct fuse_corner_data *fdata, + const struct corner *corner); +int cpr_interpolate(const struct corner *corner, int step_volt, + const struct fuse_corner_data *fdata); +int cpr_check_vreg_constraints(struct device *dev, struct regulator *vreg, + struct fuse_corner *f); diff --git a/drivers/soc/qcom/cpr.c b/drivers/soc/qcom/cpr.c index e9b854ed1bdf..6c9947ac2455 100644 --- a/drivers/soc/qcom/cpr.c +++ b/drivers/soc/qcom/cpr.c @@ -25,6 +25,7 @@ #include #include #include +#include "cpr-common.h" /* Register Offsets for RB-CPR and Bit Definitions */ @@ -124,45 +125,12 @@ #define FUSE_REVISION_UNKNOWN (-1) -enum voltage_change_dir { - NO_CHANGE, - DOWN, - UP, -}; - -struct cpr_fuse { - char *ring_osc; - char *init_voltage; - char *quotient; - char *quotient_offset; -}; - -struct fuse_corner_data { - int ref_uV; - int max_uV; - int min_uV; - int max_volt_scale; - int max_quot_scale; - /* fuse quot */ - int quot_offset; - int quot_scale; - int quot_adjust; - /* fuse quot_offset */ - int quot_offset_scale; - int quot_offset_adjust; -}; - struct cpr_fuses { int init_voltage_step; int init_voltage_width; struct fuse_corner_data *fuse_corner_data; }; -struct corner_data { - unsigned int fuse_corner; - unsigned long freq; -}; - struct cpr_desc { unsigned int num_fuse_corners; int min_diff_quot; @@ -184,44 +152,6 @@ struct cpr_desc { bool reduce_to_corner_uV; }; -struct acc_desc { - unsigned int enable_reg; - u32 enable_mask; - - struct reg_sequence *config; - struct reg_sequence *settings; - int num_regs_per_fuse; -}; - -struct cpr_acc_desc { - const struct cpr_desc *cpr_desc; - const struct acc_desc *acc_desc; -}; - -struct fuse_corner { - int min_uV; - int max_uV; - int uV; - int quot; - int step_quot; - const struct reg_sequence *accs; - int num_accs; - unsigned long max_freq; - u8 ring_osc_idx; -}; - -struct corner { - int min_uV; - int max_uV; - int uV; - int last_uV; - int quot_adjust; - u32 save_ctl; - u32 save_irq; - unsigned long freq; - struct fuse_corner *fuse_corner; -}; - struct cpr_drv { unsigned int num_corners; unsigned int ref_clk_khz; @@ -801,62 +731,16 @@ unlock: return ret; } -static int -cpr_populate_ring_osc_idx(struct cpr_drv *drv) -{ - struct fuse_corner *fuse = drv->fuse_corners; - struct fuse_corner *end = fuse + drv->desc->num_fuse_corners; - const struct cpr_fuse *fuses = drv->cpr_fuses; - u32 data; - int ret; - - for (; fuse < end; fuse++, fuses++) { - ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); - if (ret) - return ret; - fuse->ring_osc_idx = data; - } - - return 0; -} - -static int cpr_read_fuse_uV(const struct cpr_desc *desc, - const struct fuse_corner_data *fdata, - const char *init_v_efuse, - int step_volt, - struct cpr_drv *drv) -{ - int step_size_uV, steps, uV; - u32 bits = 0; - int ret; - - ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); - if (ret) - return ret; - - steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1); - /* Not two's complement.. instead highest bit is sign bit */ - if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1)) - steps = -steps; - - step_size_uV = desc->cpr_fuses.init_voltage_step; - - uV = fdata->ref_uV + steps * step_size_uV; - return DIV_ROUND_UP(uV, step_volt) * step_volt; -} - static int cpr_fuse_corner_init(struct cpr_drv *drv) { const struct cpr_desc *desc = drv->desc; - const struct cpr_fuse *fuses = drv->cpr_fuses; + const struct cpr_fuse *cpr_fuse = drv->cpr_fuses; const struct acc_desc *acc_desc = drv->acc_desc; - int i; - unsigned int step_volt; struct fuse_corner_data *fdata; struct fuse_corner *fuse, *end; - int uV; const struct reg_sequence *accs; - int ret; + unsigned int step_volt; + int i, ret; accs = acc_desc->settings; @@ -869,24 +753,16 @@ static int cpr_fuse_corner_init(struct cpr_drv *drv) end = &fuse[desc->num_fuse_corners - 1]; fdata = desc->cpr_fuses.fuse_corner_data; - for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) { - /* - * Update SoC voltages: platforms might choose a different - * regulators than the one used to characterize the algorithms - * (ie, init_voltage_step). - */ - fdata->min_uV = roundup(fdata->min_uV, step_volt); - fdata->max_uV = roundup(fdata->max_uV, step_volt); + for (i = 0; fuse <= end; fuse++, cpr_fuse++, i++, fdata++) { + ret = cpr_populate_fuse_common( + drv->dev, fdata, cpr_fuse, + fuse, step_volt, + desc->cpr_fuses.init_voltage_width, + desc->cpr_fuses.init_voltage_step); + if (ret) + return ret; - /* Populate uV */ - uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage, - step_volt, drv); - if (uV < 0) - return uV; - - fuse->min_uV = fdata->min_uV; - fuse->max_uV = fdata->max_uV; - fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV); + fuse->step_quot = desc->step_quot[fuse->ring_osc_idx]; if (fuse == end) { /* @@ -898,16 +774,6 @@ static int cpr_fuse_corner_init(struct cpr_drv *drv) end->max_uV = max(end->max_uV, end->uV); } - /* Populate target quotient by scaling */ - ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); - if (ret) - return ret; - - fuse->quot *= fdata->quot_scale; - fuse->quot += fdata->quot_offset; - fuse->quot += fdata->quot_adjust; - fuse->step_quot = desc->step_quot[fuse->ring_osc_idx]; - /* Populate acc settings */ fuse->accs = accs; fuse->num_accs = acc_desc->num_regs_per_fuse; @@ -924,25 +790,9 @@ static int cpr_fuse_corner_init(struct cpr_drv *drv) else if (fuse->uV < fuse->min_uV) fuse->uV = fuse->min_uV; - ret = regulator_is_supported_voltage(drv->vdd_apc, - fuse->min_uV, - fuse->min_uV); - if (!ret) { - dev_err(drv->dev, - "min uV: %d (fuse corner: %d) not supported by regulator\n", - fuse->min_uV, i); - return -EINVAL; - } - - ret = regulator_is_supported_voltage(drv->vdd_apc, - fuse->max_uV, - fuse->max_uV); - if (!ret) { - dev_err(drv->dev, - "max uV: %d (fuse corner: %d) not supported by regulator\n", - fuse->max_uV, i); - return -EINVAL; - } + ret = cpr_check_vreg_constraints(drv->dev, drv->vdd_apc, fuse); + if (ret) + return ret; dev_dbg(drv->dev, "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n", @@ -953,126 +803,6 @@ static int cpr_fuse_corner_init(struct cpr_drv *drv) return 0; } -static int cpr_calculate_scaling(const char *quot_offset, - struct cpr_drv *drv, - const struct fuse_corner_data *fdata, - const struct corner *corner) -{ - u32 quot_diff = 0; - unsigned long freq_diff; - int scaling; - const struct fuse_corner *fuse, *prev_fuse; - int ret; - - fuse = corner->fuse_corner; - prev_fuse = fuse - 1; - - if (quot_offset) { - ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); - if (ret) - return ret; - - quot_diff *= fdata->quot_offset_scale; - quot_diff += fdata->quot_offset_adjust; - } else { - quot_diff = fuse->quot - prev_fuse->quot; - } - - freq_diff = fuse->max_freq - prev_fuse->max_freq; - freq_diff /= 1000000; /* Convert to MHz */ - scaling = 1000 * quot_diff / freq_diff; - return min(scaling, fdata->max_quot_scale); -} - -static int cpr_interpolate(const struct corner *corner, int step_volt, - const struct fuse_corner_data *fdata) -{ - unsigned long f_high, f_low, f_diff; - int uV_high, uV_low, uV; - u64 temp, temp_limit; - const struct fuse_corner *fuse, *prev_fuse; - - fuse = corner->fuse_corner; - prev_fuse = fuse - 1; - - f_high = fuse->max_freq; - f_low = prev_fuse->max_freq; - uV_high = fuse->uV; - uV_low = prev_fuse->uV; - f_diff = fuse->max_freq - corner->freq; - - /* - * Don't interpolate in the wrong direction. This could happen - * if the adjusted fuse voltage overlaps with the previous fuse's - * adjusted voltage. - */ - if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq) - return corner->uV; - - temp = f_diff * (uV_high - uV_low); - temp = div64_ul(temp, f_high - f_low); - - /* - * max_volt_scale has units of uV/MHz while freq values - * have units of Hz. Divide by 1000000 to convert to. - */ - temp_limit = f_diff * fdata->max_volt_scale; - do_div(temp_limit, 1000000); - - uV = uV_high - min(temp, temp_limit); - return roundup(uV, step_volt); -} - -static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp) -{ - struct device_node *np; - unsigned int fuse_corner = 0; - - np = dev_pm_opp_get_of_node(opp); - if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner)) - pr_err("%s: missing 'qcom,opp-fuse-level' property\n", - __func__); - - of_node_put(np); - - return fuse_corner; -} - -static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, - struct device *cpu_dev) -{ - u64 rate = 0; - struct device_node *ref_np; - struct device_node *desc_np; - struct device_node *child_np = NULL; - struct device_node *child_req_np = NULL; - - desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); - if (!desc_np) - return 0; - - ref_np = dev_pm_opp_get_of_node(ref); - if (!ref_np) - goto out_ref; - - do { - of_node_put(child_req_np); - child_np = of_get_next_available_child(desc_np, child_np); - child_req_np = of_parse_phandle(child_np, "required-opps", 0); - } while (child_np && child_req_np != ref_np); - - if (child_np && child_req_np == ref_np) - of_property_read_u64(child_np, "opp-hz", &rate); - - of_node_put(child_req_np); - of_node_put(child_np); - of_node_put(ref_np); -out_ref: - of_node_put(desc_np); - - return (unsigned long) rate; -} - static int cpr_corner_init(struct cpr_drv *drv) { const struct cpr_desc *desc = drv->desc; @@ -1110,7 +840,7 @@ static int cpr_corner_init(struct cpr_drv *drv) opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level); if (IS_ERR(opp)) return -EINVAL; - fc = cpr_get_fuse_corner(opp); + fc = cpr_get_fuse_corner(opp, 0); if (!fc) { dev_pm_opp_put(opp); return -EINVAL; @@ -1186,7 +916,7 @@ static int cpr_corner_init(struct cpr_drv *drv) corner->uV = fuse->uV; if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) { - scaling = cpr_calculate_scaling(quot_offset, drv, + scaling = cpr_calculate_scaling(quot_offset, drv->dev, fdata, corner); if (scaling < 0) return scaling; @@ -1224,47 +954,6 @@ static int cpr_corner_init(struct cpr_drv *drv) return 0; } -static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv) -{ - const struct cpr_desc *desc = drv->desc; - struct cpr_fuse *fuses; - int i; - - fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners, - sizeof(struct cpr_fuse), - GFP_KERNEL); - if (!fuses) - return ERR_PTR(-ENOMEM); - - for (i = 0; i < desc->num_fuse_corners; i++) { - char tbuf[32]; - - snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1); - fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); - if (!fuses[i].ring_osc) - return ERR_PTR(-ENOMEM); - - snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1); - fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf, - GFP_KERNEL); - if (!fuses[i].init_voltage) - return ERR_PTR(-ENOMEM); - - snprintf(tbuf, 32, "cpr_quotient%d", i + 1); - fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); - if (!fuses[i].quotient) - return ERR_PTR(-ENOMEM); - - snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1); - fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf, - GFP_KERNEL); - if (!fuses[i].quotient_offset) - return ERR_PTR(-ENOMEM); - } - - return fuses; -} - static void cpr_set_loop_allowed(struct cpr_drv *drv) { drv->loop_disabled = false; @@ -1296,54 +985,6 @@ static int cpr_init_parameters(struct cpr_drv *drv) return 0; } -static int cpr_find_initial_corner(struct cpr_drv *drv) -{ - unsigned long rate; - const struct corner *end; - struct corner *iter; - unsigned int i = 0; - - if (!drv->cpu_clk) { - dev_err(drv->dev, "cannot get rate from NULL clk\n"); - return -EINVAL; - } - - end = &drv->corners[drv->num_corners - 1]; - rate = clk_get_rate(drv->cpu_clk); - - /* - * Some bootloaders set a CPU clock frequency that is not defined - * in the OPP table. When running at an unlisted frequency, - * cpufreq_online() will change to the OPP which has the lowest - * frequency, at or above the unlisted frequency. - * Since cpufreq_online() always "rounds up" in the case of an - * unlisted frequency, this function always "rounds down" in case - * of an unlisted frequency. That way, when cpufreq_online() - * triggers the first ever call to cpr_set_performance_state(), - * it will correctly determine the direction as UP. - */ - for (iter = drv->corners; iter <= end; iter++) { - if (iter->freq > rate) - break; - i++; - if (iter->freq == rate) { - drv->corner = iter; - break; - } - if (iter->freq < rate) - drv->corner = iter; - } - - if (!drv->corner) { - dev_err(drv->dev, "boot up corner not found\n"); - return -EINVAL; - } - - dev_dbg(drv->dev, "boot up perf state: %u\n", i); - - return 0; -} - static const struct cpr_desc qcs404_cpr_desc = { .num_fuse_corners = 3, .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF, @@ -1531,8 +1172,9 @@ static int cpr_pd_attach_dev(struct generic_pm_domain *domain, if (ret) goto unlock; - ret = cpr_find_initial_corner(drv); - if (ret) + ret = cpr_find_initial_corner(drv->dev, drv->cpu_clk, drv->corners, + drv->num_corners); + if (ret < 0) goto unlock; if (acc_desc->config) @@ -1616,6 +1258,7 @@ static int cpr_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct cpr_drv *drv; + const struct cpr_desc *desc; int irq, ret; const struct cpr_acc_desc *data; struct device_node *np; @@ -1631,6 +1274,7 @@ static int cpr_probe(struct platform_device *pdev) drv->dev = dev; drv->desc = data->cpr_desc; drv->acc_desc = data->acc_desc; + desc = drv->desc; drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners, sizeof(*drv->fuse_corners), @@ -1670,11 +1314,13 @@ static int cpr_probe(struct platform_device *pdev) if (ret) return ret; - drv->cpr_fuses = cpr_get_fuses(drv); + drv->cpr_fuses = cpr_get_fuses(drv->dev, 0, desc->num_fuse_corners); if (IS_ERR(drv->cpr_fuses)) return PTR_ERR(drv->cpr_fuses); - ret = cpr_populate_ring_osc_idx(drv); + ret = cpr_populate_ring_osc_idx(drv->dev, drv->fuse_corners, + drv->cpr_fuses, + desc->num_fuse_corners); if (ret) return ret; From dffdf154579292413b6e70bf907fbc1cfb70c2d1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 25 Nov 2020 20:29:26 +0100 Subject: [PATCH 064/174] dt-bindings: avs: cpr: Convert binding to YAML schema Convert the qcom,cpr.txt document to YAML schema and place it in the appropriate directory, since this driver was moved from power/avs to soc/qcom, but forgets to move the documentation. Fixes: a7305e684fcf ("PM: AVS: qcom-cpr: Move the driver to the qcom specific drivers") Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/power/avs/qcom,cpr.txt | 131 +------------- .../bindings/soc/qcom/qcom,cpr.yaml | 167 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 169 insertions(+), 131 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt index ab0d5ebbad4e..2ada8cd08949 100644 --- a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -1,130 +1 @@ -QCOM CPR (Core Power Reduction) - -CPR (Core Power Reduction) is a technology to reduce core power on a CPU -or other device. Each OPP of a device corresponds to a "corner" that has -a range of valid voltages for a particular frequency. While the device is -running at a particular frequency, CPR monitors dynamic factors such as -temperature, etc. and suggests adjustments to the voltage to save power -and meet silicon characteristic requirements. - -- compatible: - Usage: required - Value type: - Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 - -- reg: - Usage: required - Value type: - Definition: base address and size of the rbcpr register region - -- interrupts: - Usage: required - Value type: - Definition: should specify the CPR interrupt - -- clocks: - Usage: required - Value type: - Definition: phandle to the reference clock - -- clock-names: - Usage: required - Value type: - Definition: must be "ref" - -- vdd-apc-supply: - Usage: required - Value type: - Definition: phandle to the vdd-apc-supply regulator - -- #power-domain-cells: - Usage: required - Value type: - Definition: should be 0 - -- operating-points-v2: - Usage: required - Value type: - Definition: A phandle to the OPP table containing the - performance states supported by the CPR - power domain - -- acc-syscon: - Usage: optional - Value type: - Definition: phandle to syscon for writing ACC settings - -- nvmem-cells: - Usage: required - Value type: - Definition: phandle to nvmem cells containing the data - that makes up a fuse corner, for each fuse corner. - As well as the CPR fuse revision. - -- nvmem-cell-names: - Usage: required - Value type: - Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", - "cpr_quotient_offset3", "cpr_init_voltage1", - "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", - "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", - "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" - for qcs404. - -Example: - - cpr_opp_table: cpr-opp-table { - compatible = "operating-points-v2-qcom-level"; - - cpr_opp1: opp1 { - opp-level = <1>; - qcom,opp-fuse-level = <1>; - }; - cpr_opp2: opp2 { - opp-level = <2>; - qcom,opp-fuse-level = <2>; - }; - cpr_opp3: opp3 { - opp-level = <3>; - qcom,opp-fuse-level = <3>; - }; - }; - - power-controller@b018000 { - compatible = "qcom,qcs404-cpr", "qcom,cpr"; - reg = <0x0b018000 0x1000>; - interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; - clocks = <&xo_board>; - clock-names = "ref"; - vdd-apc-supply = <&pms405_s3>; - #power-domain-cells = <0>; - operating-points-v2 = <&cpr_opp_table>; - acc-syscon = <&tcsr>; - - nvmem-cells = <&cpr_efuse_quot_offset1>, - <&cpr_efuse_quot_offset2>, - <&cpr_efuse_quot_offset3>, - <&cpr_efuse_init_voltage1>, - <&cpr_efuse_init_voltage2>, - <&cpr_efuse_init_voltage3>, - <&cpr_efuse_quot1>, - <&cpr_efuse_quot2>, - <&cpr_efuse_quot3>, - <&cpr_efuse_ring1>, - <&cpr_efuse_ring2>, - <&cpr_efuse_ring3>, - <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; - }; +This file has been moved to ../../soc/qcom/qcom,cpr.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml new file mode 100644 index 000000000000..f58dc6c138a6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Core Power Reduction (CPR) + +description: | + CPR (Core Power Reduction) is a technology to reduce core power on a CPU + or other device. Each OPP of a device corresponds to a "corner" that has + a range of valid voltages for a particular frequency. While the device is + running at a particular frequency, CPR monitors dynamic factors such as + temperature, etc. and suggests adjustments to the voltage to save power + and meet silicon characteristic requirements. + +maintainers: + - Niklas Cassel + +properties: + compatible: + items: + - enum: + - qcom,qcs404-cpr + - const: qcom,cpr + + reg: + description: Base address and size of the RBCPR register region + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: ref + + clocks: + items: + - description: CPR reference clock + + vdd-apc-supply: + description: Autonomous Phase Control (APC) power supply + + '#power-domain-cells': + const: 0 + + acc-syscon: + description: phandle to syscon for writing ACC settings + + nvmem-cells: + minItems: 9 + maxItems: 32 + description: Cells containing the fuse corners and revision data + + nvmem-cell-names: + minItems: 9 + maxItems: 32 + + operating-points-v2: true + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - vdd-apc-supply + - "#power-domain-cells" + - nvmem-cells + - nvmem-cell-names + - operating-points-v2 + +additionalProperties: false + +examples: + - | + #include + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x100>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cpr>; + power-domain-names = "cpr"; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cpr_opp1>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cpr_opp2>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cpr_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cpr_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <3>; + }; + }; + + power-controller@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr0_quotient_offset1", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_fuse_revision"; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index cd0f68d4a34a..13dae1deb655 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15967,7 +15967,7 @@ M: Niklas Cassel L: linux-pm@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt +F: Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml F: drivers/soc/qcom/cpr.c QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 From 0023cba0a21a1d087ea6c510fd7ca81ce8f8cbb4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 25 Nov 2020 11:23:17 +0100 Subject: [PATCH 065/174] arm64: qcom: qcs404: Change CPR nvmem-names The CPR driver's common functions were split and put in another file in order to support newer CPR revisions: to simplify the commonization, the expected names of the fuses had to be changed in order for both new and old support to use the same fuse name retrieval function and keeping the naming consistent. The thread id was added to the fuse name and, since CPRv1 does not support threads, it is expected to always read ID 0, which means that the expected name here is now "cpr0_(fuse_name)" instead of "cpr_(fuse_name)": luckily, QCS404 is the only user so change it accordingly. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6db753b49326..2a7f6ffe1b90 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1173,19 +1173,19 @@ <&cpr_efuse_ring2>, <&cpr_efuse_ring3>, <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; + nvmem-cell-names = "cpr0_quotient_offset1", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_fuse_revision"; }; timer@b120000 { From 71dfa2b6234b62cd995d82fef66d9f4b4b65bde5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 24 Nov 2020 20:39:22 +0100 Subject: [PATCH 066/174] soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened This commit introduces a new driver, based on the one for cpr v1, to enable support for the newer Qualcomm Core Power Reduction hardware, known downstream as CPR3, CPR4 and CPRh, and support for MSM8998 and SDM630 CPU power reduction. In these new versions of the hardware, support for various new features was introduced, including voltage reduction for the GPU, security hardening and a new way of controlling CPU DVFS, consisting in internal communication between microcontrollers, specifically the CPR-Hardened and the Operating State Manager. The CPR v3, v4 and CPRh are present in a broad range of SoCs, from the mid-range to the high end ones including, but not limited to, MSM8953/8996/8998, SDM630/636/660/845. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/qcom/Kconfig | 17 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/cpr-common.c | 35 +- drivers/soc/qcom/cpr-common.h | 4 + drivers/soc/qcom/cpr3.c | 2897 +++++++++++++++++++++++++++++++++ include/soc/qcom/cpr.h | 17 + 6 files changed, 2965 insertions(+), 6 deletions(-) create mode 100644 drivers/soc/qcom/cpr3.c create mode 100644 include/soc/qcom/cpr.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e718b8735444..354b38ef1df0 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -42,6 +42,23 @@ config QCOM_CPR To compile this driver as a module, choose M here: the module will be called qcom-cpr +config QCOM_CPR3 + tristate "QCOM Core Power Reduction (CPR v3/v4/Hardened) support" + depends on ARCH_QCOM && HAS_IOMEM + select PM_OPP + select REGMAP + help + Say Y here to enable support for the CPR hardware found on a broad + variety of Qualcomm SoCs like MSM8996, MSM8998, SDM630, SDM660, + SDM845 and others. + + This driver populates OPP tables and makes adjustments to them + based on feedback from the CPR hardware. If you want to do CPU + and/or GPU frequency scaling say Y here. + + To compile this driver as a module, choose M here: the module will + be called qcom-cpr3 + config QCOM_GENI_SE tristate "QCOM GENI Serial Engine Driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index bed55881dfd9..31e95892e575 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_CPR) += cpr-common.o cpr.o +obj-$(CONFIG_QCOM_CPR3) += cpr-common.o cpr3.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/cpr-common.c b/drivers/soc/qcom/cpr-common.c index 540bb074358d..25a1559ac388 100644 --- a/drivers/soc/qcom/cpr-common.c +++ b/drivers/soc/qcom/cpr-common.c @@ -219,6 +219,29 @@ u32 cpr_get_fuse_corner(struct dev_pm_opp *opp, u32 tid) of_node_put(np); return fc; + +} + +void cpr_get_corner_post_vadj(struct dev_pm_opp *opp, u32 tid, + s32 *open_loop, s32 *closed_loop) +{ + struct device_node *np; + + /* + * There is no of_property_read_s32_index, so we just store the + * result into a s32 variable. After all, the OF API is doing + * the exact same for of_property_read_s32... + */ + np = dev_pm_opp_get_of_node(opp); + if (of_property_read_u32_index(np, "qcom,opp-oloop-vadj", tid, + open_loop)) + *open_loop = 0; + + if (of_property_read_u32_index(np, "qcom,opp-cloop-vadj", tid, + closed_loop)) + *closed_loop = 0; + + of_node_put(np); } unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, @@ -261,11 +284,10 @@ int cpr_calculate_scaling(const char *quot_offset, const struct fuse_corner_data *fdata, const struct corner *corner) { - u32 quot_diff = 0; - unsigned long freq_diff; - int scaling; + u64 freq_diff; const struct fuse_corner *fuse, *prev_fuse; - int ret; + u32 quot_diff; + int scaling, ret; fuse = corner->fuse_corner; prev_fuse = fuse - 1; @@ -282,8 +304,9 @@ int cpr_calculate_scaling(const char *quot_offset, } freq_diff = fuse->max_freq - prev_fuse->max_freq; - freq_diff /= 1000000; /* Convert to MHz */ - scaling = 1000 * quot_diff / freq_diff; + freq_diff = div_u64(freq_diff, 1000000); /* Convert to MHz */ + scaling = 1000 * quot_diff; + do_div(scaling, freq_diff); return min(scaling, fdata->max_quot_scale); } diff --git a/drivers/soc/qcom/cpr-common.h b/drivers/soc/qcom/cpr-common.h index 83a1f7c941b8..96ff6301c81e 100644 --- a/drivers/soc/qcom/cpr-common.h +++ b/drivers/soc/qcom/cpr-common.h @@ -65,6 +65,8 @@ struct corner { struct corner_data { unsigned int fuse_corner; unsigned long freq; + int oloop_vadj; + int cloop_vadj; }; struct acc_desc { @@ -101,6 +103,8 @@ int cpr_populate_fuse_common(struct device *dev, int cpr_find_initial_corner(struct device *dev, struct clk *cpu_clk, struct corner *corners, int num_corners); u32 cpr_get_fuse_corner(struct dev_pm_opp *opp, u32 tid); +void cpr_get_corner_post_vadj(struct dev_pm_opp *opp, u32 tid, + s32 *open_loop, s32 *closed_loop); unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, struct device *cpu_dev); int cpr_calculate_scaling(const char *quot_offset, diff --git a/drivers/soc/qcom/cpr3.c b/drivers/soc/qcom/cpr3.c new file mode 100644 index 000000000000..7e368b39d07c --- /dev/null +++ b/drivers/soc/qcom/cpr3.c @@ -0,0 +1,2897 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019 Linaro Limited + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpr-common.h" + +#define CPR3_RO_COUNT 16 +#define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0) + +/* CPR3 registers */ +#define CPR3_REG_CPR_VERSION 0x0 +#define CPRH_CPR_VERSION_4P5 0x40050000 + +#define CPR3_REG_CPR_CTL 0x4 +#define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0) +#define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1) +#define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1 +#define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6) +#define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1 +#define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2 +#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3 +#define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9) +#define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9 + +#define CPR3_REG_CPR_STATUS 0x8 +#define CPR3_CPR_STATUS_BUSY_MASK BIT(0) + +/* + * This register is not present on controllers that support HW closed-loop + * except CPR4 APSS controller. + */ +#define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC + +#define CPR3_REG_CPR_STEP_QUOT 0x14 +#define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0) +#define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0 +#define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6) +#define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6 +#define CPRH_DELTA_QUOT_STEP_FACTOR 4 + +#define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro)) +#define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor)) + +#define CPR3_REG_CONT_CMD 0x800 +#define CPR3_CONT_CMD_ACK 0x1 +#define CPR3_CONT_CMD_NACK 0x0 + +#define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread)) +#define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0) +#define CPR3_THRESH_CONS_DOWN_SHIFT 0 +#define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4) +#define CPR3_THRESH_CONS_UP_SHIFT 4 +#define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8) +#define CPR3_THRESH_DOWN_THRESH_SHIFT 8 +#define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13) +#define CPR3_THRESH_UP_THRESH_SHIFT 13 + +#define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread)) + +#define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread)) +#define CPR3_RESULT0_BUSY_MASK BIT(0) +#define CPR3_RESULT0_STEP_DN_MASK BIT(1) +#define CPR3_RESULT0_STEP_UP_MASK BIT(2) +#define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3) +#define CPR3_RESULT0_ERROR_STEPS_SHIFT 3 +#define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8) +#define CPR3_RESULT0_ERROR_SHIFT 8 + +#define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread)) +#define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0) +#define CPR3_RESULT1_QUOT_MIN_SHIFT 0 +#define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12) +#define CPR3_RESULT1_QUOT_MAX_SHIFT 12 +#define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24) +#define CPR3_RESULT1_RO_MIN_SHIFT 24 +#define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28) +#define CPR3_RESULT1_RO_MAX_SHIFT 28 + +#define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread)) +#define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0) +#define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0 +#define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6) +#define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6 +#define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16) +#define CPR3_RESULT2_SENSOR_MIN_SHIFT 16 +#define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24) +#define CPR3_RESULT2_SENSOR_MAX_SHIFT 24 + +#define CPR3_REG_IRQ_EN 0x81C +#define CPR3_REG_IRQ_CLEAR 0x820 +#define CPR3_REG_IRQ_STATUS 0x824 +#define CPR3_IRQ_UP BIT(3) +#define CPR3_IRQ_MID BIT(2) +#define CPR3_IRQ_DOWN BIT(1) +#define CPR3_IRQ_ALL (CPR3_IRQ_UP | CPR3_IRQ_MID | CPR3_IRQ_DOWN) + +#define CPR3_REG_TARGET_QUOT(thread, ro) (0x840 + 0x440 * (thread) + 0x4 * (ro)) + +/* Registers found only on controllers that support HW closed-loop. */ +#define CPR3_REG_PD_THROTTLE 0xE8 + +#define CPR3_REG_HW_CLOSED_LOOP_DISABLED 0x3000 +#define CPR3_REG_CPR_TIMER_MID_CONT 0x3004 +#define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008 + +/* CPR4 controller specific registers and bit definitions */ +#define CPR4_REG_CPR_TIMER_CLAMP 0x10 +#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27) + +#define CPR4_REG_MISC 0x700 +#define CPR4_MISC_RESET_STEP_QUOT_LOOP_EN BIT(2) +#define CPR4_MISC_THREAD_HAS_ALWAYS_VOTE_EN BIT(3) + +#define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4 +#define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0) +#define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0 +#define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5) +#define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5 + +#define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8 +#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18) +#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHFT 18 + +#define CPR4_REG_MARGIN_ADJ_CTL 0x7F8 +#define CPR4_MARGIN_ADJ_HW_CLOSED_LOOP_EN BIT(4) +#define CPR4_MARGIN_ADJ_PER_RO_KV_MARGIN_EN BIT(7) +#define CPR4_MARGIN_ADJ_PMIC_STEP_SIZE_MASK GENMASK(16, 12) +#define CPR4_MARGIN_ADJ_PMIC_STEP_SIZE_SHIFT 12 +#define CPR4_MARGIN_ADJ_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26) +#define CPR4_MARGIN_ADJ_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26 + +#define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread)) +#define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31) +#define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0) + +/* CPRh controller specific registers and bit definitions */ +#define __CPRH_REG_CORNER(rbase, tbase, tid, cnum) (rbase + (tbase * tid) + (0x4 * cnum)) +#define CPRH_REG_CORNER(d, t, c) __CPRH_REG_CORNER(d->reg_corner, d->reg_corner_tid, t, c) + +#define CPRH_CTL_OSM_ENABLED BIT(0) +#define CPRH_CTL_BASE_VOLTAGE_MASK GENMASK(10, 1) +#define CPRH_CTL_BASE_VOLTAGE_SHIFT 1 +#define CPRH_CTL_MODE_SWITCH_DELAY_MASK GENMASK(24, 17) +#define CPRH_CTL_MODE_SWITCH_DELAY_SHIFT 17 +#define CPRH_CTL_VOLTAGE_MULTIPLIER_MASK GENMASK(28, 25) +#define CPRH_CTL_VOLTAGE_MULTIPLIER_SHIFT 25 + +#define CPRH_CORNER_INIT_VOLTAGE_MASK GENMASK(7, 0) +#define CPRH_CORNER_INIT_VOLTAGE_SHIFT 0 +#define CPRH_CORNER_FLOOR_VOLTAGE_MASK GENMASK(15, 8) +#define CPRH_CORNER_FLOOR_VOLTAGE_SHIFT 8 +#define CPRH_CORNER_QUOT_DELTA_MASK GENMASK(24, 16) +#define CPRH_CORNER_QUOT_DELTA_SHIFT 16 +#define CPRH_CORNER_RO_SEL_MASK GENMASK(28, 25) +#define CPRH_CORNER_RO_SEL_SHIFT 25 +#define CPRH_CORNER_CPR_CL_DISABLE BIT(29) + +#define CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE 255 +#define CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE 255 +#define CPRH_CORNER_QUOT_DELTA_MAX_VALUE 511 + +enum cpr_type { + CTRL_TYPE_CPR3, + CTRL_TYPE_CPR4, + CTRL_TYPE_CPRH, + CTRL_TYPE_MAX, +}; + +/* + * struct cpr_thread_desc - CPR Thread-specific parameters + * + * @controller_id: Identifier of the CPR controller expected by the HW + * @ro_scaling_factor: Scaling factor for each ring oscillator entry + * @hw_tid: Identifier of the CPR thread expected by the HW + * @init_voltage_step: Voltage in uV for number of steps read from fuse array + * @init_voltage_width: Bit-width of the voltage read from the fuse array + * @sensor_range_start: First sensor ID used by a thread + * @sensor_range_end: Last sensor ID used by a thread + * @num_fuse_corners: Number of valid entries in fuse_corner_data + * @step_quot_init_min: Minimum achievable step quotient for this corner + * @step_quot_init_max: Maximum achievable step quotient for this corner + * @fuse_corner_data: Parameters for calculation of each fuse corner + */ +struct cpr_thread_desc { + u8 controller_id; + u8 hw_tid; + const int (*ro_scaling_factor)[CPR3_RO_COUNT]; + int ro_avail_corners; + int init_voltage_step; + int init_voltage_width; + u8 sensor_range_start; + u8 sensor_range_end; + u8 step_quot_init_min; + u8 step_quot_init_max; + unsigned int num_fuse_corners; + struct fuse_corner_data *fuse_corner_data; +}; + +/* + * struct cpr_desc - Driver instance-wide CPR parameters + * + * @cpr_type: Type (base version) of the CPR controller + * @num_threads: Max. number of threads supported by this controller + * @timer_delay_us: Loop delay time in uS + * @timer_updn_delay_us: Voltage after-up/before-down delay time in uS + * @timer_cons_up: Wait between consecutive up requests in uS + * @timer_cons_down: Wait between consecutive down requests in uS + * @up_threshold: Generic corner up threshold + * @down_threshold: Generic corner down threshold + * @idle_clocks: CPR Sensor: idle timer in cpr clocks unit + * @count_mode: CPR Sensor: counting mode + * @count_repeat: CPR Sensor: number of times to repeat reading + * @gcnt_us: CPR measurement interval in uS + * @vreg_step_fixed: Regulator voltage per step (if vreg unusable) + * @vreg_step_up_limit: Num. of steps up at once before re-measuring sensors + * @vreg_step_down_limit: Num. of steps dn at once before re-measuring sensors + * @vdd_settle_time_us: Settling timer to account for one VDD supply step + * @corner_settle_time_us: Settle time for corner switch request + * @mem_acc_threshold: Memory Accelerator (MEM-ACC) voltage threshold + * @apm_threshold: Array Power Mux (APM) voltage threshold + * @apm_crossover: Array Power Mux (APM) corner crossover voltage + * @apm_hysteresis: Hysteresis for APM V-threshold related calculations + * @cpr_base_voltage: Safety: Absolute minimum voltage (uV) on this CPR + * @cpr_max_voltage: Safety: Absolute maximum voltage (uV) on this CPR + * @pd_throttle_val: CPR Power Domain throttle during voltage switch + * @threads: Array containing "CPR Thread" specific parameters + * @reduce_to_fuse_uV: Reduce corner max volts (if higher) to fuse ceiling + * @reduce_to_corner_uV: Reduce corner max volts (if higher) to corner ceil. + * @hw_closed_loop_en: Enable CPR HW Closed-Loop voltage auto-adjustment + */ +struct cpr_desc { + enum cpr_type cpr_type; + unsigned int num_threads; + unsigned int timer_delay_us; + u8 timer_updn_delay_us; + u8 timer_cons_up; + u8 timer_cons_down; + u8 up_threshold; + u8 down_threshold; + u8 idle_clocks; + u8 count_mode; + u8 count_repeat; + u8 gcnt_us; + u16 vreg_step_fixed; + u8 vreg_step_up_limit; + u8 vreg_step_down_limit; + u8 vdd_settle_time_us; + u8 corner_settle_time_us; + int mem_acc_threshold; + int apm_threshold; + int apm_crossover; + int apm_hysteresis; + u32 cpr_base_voltage; + u32 cpr_max_voltage; + u32 pd_throttle_val; + + const struct cpr_thread_desc **threads; + bool reduce_to_fuse_uV; + bool reduce_to_corner_uV; + bool hw_closed_loop_en; +}; + +struct cpr_drv; +struct cpr_thread { + int num_corners; + int id; + bool enabled; + void __iomem *base; + struct clk *cpu_clk; + struct corner *corner; + struct corner *corners; + struct fuse_corner *fuse_corners; + struct cpr_drv *drv; + struct cpr_ext_data ext_data; + struct generic_pm_domain pd; + struct device *attached_cpu_dev; + struct work_struct restart_work; + bool restarting; + + const struct cpr_fuse *cpr_fuses; + const struct cpr_thread_desc *desc; +}; + +struct cpr_drv { + int irq; + unsigned int ref_clk_khz; + struct device *dev; + struct mutex lock; + struct regulator *vreg; + struct regmap *tcsr; + u32 gcnt; + u32 speed_bin; + u32 fusing_rev; + u32 last_uV; + u32 cpr_hw_rev; + u32 reg_corner; + u32 reg_corner_tid; + u32 reg_ctl; + u32 reg_status; + int fuse_level_set; + int extra_corners; + unsigned int vreg_step; + bool enabled; + + struct cpr_thread *threads; + struct genpd_onecell_data cell_data; + + const struct cpr_desc *desc; + const struct acc_desc *acc_desc; + struct dentry *debugfs; +}; + +/** + * cpr_get_ro_factor() - Get fuse corner ring oscillator factor + * + * Not all threads have different scaling factors for each + * Fuse Corner: if the RO factors are the same for all corners, + * then only one is specified, instead of uselessly repeating + * the same array for FC-times. + * This function checks for the same and gives back the right + * factor for the requested ring oscillator. + * + * Return: Ring oscillator factor + */ +static int cpr_get_ro_factor(const struct cpr_thread_desc *tdesc, + int fnum, int ro_idx) +{ + int ro_fnum; + + if (tdesc->ro_avail_corners == tdesc->num_fuse_corners) + ro_fnum = fnum; + else + ro_fnum = 0; + + return tdesc->ro_scaling_factor[ro_fnum][ro_idx]; +} + +static void cpr_write(struct cpr_thread *thread, u32 offset, u32 value) +{ + writel(value, thread->base + offset); +} + +static u32 cpr_read(struct cpr_thread *thread, u32 offset) +{ + return readl(thread->base + offset); +} + +static void +cpr_masked_write(struct cpr_thread *thread, u32 offset, u32 mask, u32 value) +{ + u32 val; + + val = readl(thread->base + offset); + val &= ~mask; + val |= value & mask; + writel(val, thread->base + offset); +} + +static void cpr_irq_clr(struct cpr_thread *thread) +{ + cpr_write(thread, CPR3_REG_IRQ_CLEAR, CPR3_IRQ_ALL); +} + +static void cpr_irq_clr_nack(struct cpr_thread *thread) +{ + cpr_irq_clr(thread); + cpr_write(thread, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_NACK); +} + +static void cpr_irq_clr_ack(struct cpr_thread *thread) +{ + cpr_irq_clr(thread); + cpr_write(thread, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_ACK); +} + +static void cpr_irq_set(struct cpr_thread *thread, u32 int_bits) +{ + /* On CPR-hardened, interrupts are managed by and on firmware */ + if (thread->drv->desc->cpr_type == CTRL_TYPE_CPRH) + return; + + cpr_write(thread, CPR3_REG_IRQ_EN, int_bits); +} + +/** + * cpr_ctl_enable() - Enable CPR thread + * @thread: Structure holding CPR thread-specific parameters + */ +static void cpr_ctl_enable(struct cpr_thread *thread) +{ + if (thread->drv->enabled && !thread->restarting) { + cpr_masked_write(thread, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_LOOP_EN_MASK, + CPR3_CPR_CTL_LOOP_EN_MASK); + } +} + +/** + * cpr_ctl_disable() - Disable CPR thread + * @thread: Structure holding CPR thread-specific parameters + */ +static void cpr_ctl_disable(struct cpr_thread *thread) +{ + const struct cpr_desc *desc = thread->drv->desc; + + if (desc->cpr_type != CTRL_TYPE_CPRH) { + cpr_irq_set(thread, 0); + cpr_irq_clr(thread); + } + + cpr_masked_write(thread, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_LOOP_EN_MASK, 0); +} + +/** + * cpr_ctl_is_enabled() - Check if thread is enabled + * @thread: Structure holding CPR thread-specific parameters + * + * Return: true if the CPR is enabled, false if it is disabled. + */ +static bool cpr_ctl_is_enabled(struct cpr_thread *thread) +{ + u32 reg_val; + + reg_val = cpr_read(thread, CPR3_REG_CPR_CTL); + return reg_val & CPR3_CPR_CTL_LOOP_EN_MASK; +} + +/** + * cpr_check_any_thread_busy() - Check if HW is done processing + * @thread: Structure holding CPR thread-specific parameters + * + * Return: true if the CPR is busy, false if it is ready. + */ +static bool cpr_check_any_thread_busy(struct cpr_thread *thread) +{ + int i; + + for (i = 0; i < thread->drv->desc->num_threads; i++) + if (cpr_read(thread, CPR3_REG_RESULT0(i)) & + CPR3_RESULT0_BUSY_MASK) + return true; + + return false; +} + +static void cpr_restart_worker(struct work_struct *work) +{ + struct cpr_thread *thread = container_of(work, struct cpr_thread, + restart_work); + struct cpr_drv *drv = thread->drv; + int i; + + mutex_lock(&drv->lock); + + thread->restarting = true; + cpr_ctl_disable(thread); + disable_irq(drv->irq); + + mutex_unlock(&drv->lock); + + for (i = 0; i < 20; i++) { + u32 cpr_status = cpr_read(thread, CPR3_REG_CPR_STATUS); + u32 ctl = cpr_read(thread, CPR3_REG_CPR_CTL); + + if ((cpr_status & CPR3_CPR_STATUS_BUSY_MASK) && + !(ctl & CPR3_CPR_CTL_LOOP_EN_MASK)) + break; + + udelay(10); + } + + cpr_irq_clr(thread); + + for (i = 0; i < 20; i++) { + u32 status = cpr_read(thread, CPR3_REG_IRQ_STATUS); + + if (!(status & CPR3_IRQ_ALL)) + break; + udelay(10); + } + + mutex_lock(&drv->lock); + + thread->restarting = false; + enable_irq(drv->irq); + cpr_ctl_enable(thread); + + mutex_unlock(&drv->lock); +} + +/** + * cpr_corner_restore() - Restore saved corner level + * @thread: Structure holding CPR thread-specific parameters + * @corner: Structure holding the saved corner level + */ +static void cpr_corner_restore(struct cpr_thread *thread, + struct corner *corner) +{ + struct cpr_drv *drv = thread->drv; + struct fuse_corner *fuse = corner->fuse_corner; + const struct cpr_thread_desc *tdesc = thread->desc; + u32 ro_sel = fuse->ring_osc_idx; + + cpr_write(thread, CPR3_REG_GCNT(ro_sel), drv->gcnt); + + cpr_write(thread, CPR3_REG_RO_MASK(tdesc->hw_tid), + CPR3_RO_MASK & ~BIT(ro_sel)); + + cpr_write(thread, CPR3_REG_TARGET_QUOT(tdesc->hw_tid, ro_sel), + fuse->quot - corner->quot_adjust); + + if (drv->desc->cpr_type == CTRL_TYPE_CPR4) { + cpr_masked_write(thread, + CPR4_REG_CPR_MASK_THREAD(tdesc->hw_tid), + CPR4_CPR_MASK_THREAD_DISABLE_THREAD | + CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, 0); + } + + thread->corner = corner; + corner->last_uV = corner->uV; +} + +/** + * cpr_set_acc() - Set fuse level to the mem-acc + * @thread: Structure holding CPR thread-specific parameters + * @f: Fuse level + */ +static void cpr_set_acc(struct cpr_drv *drv, int f) +{ + const struct acc_desc *desc = drv->acc_desc; + struct reg_sequence *s = desc->settings; + int n = desc->num_regs_per_fuse; + + if (!s || f == drv->fuse_level_set) + return; + + regmap_multi_reg_write(drv->tcsr, s + (n * f), n); + drv->fuse_level_set = f; +} + +/** + * cpr_post_voltage() - Actions to execute before setting voltage + * @thread: Structure holding CPR thread-specific parameters + * @dir: Enumeration for voltage change direction + * @fuse_level: Fuse corner for mem-acc, if supported. + * + * Return: Zero for success or negative number on errors. + */ +static int cpr_pre_voltage(struct cpr_thread *thread, + enum voltage_change_dir dir, + int fuse_level) +{ + struct cpr_drv *drv = thread->drv; + + if (drv->desc->cpr_type == CTRL_TYPE_CPR3 && + drv->desc->pd_throttle_val) + cpr_write(thread, CPR3_REG_PD_THROTTLE, + drv->desc->pd_throttle_val); + + if (drv->tcsr && dir == DOWN) + cpr_set_acc(drv, fuse_level); + + return 0; +} + +/** + * cpr_post_voltage() - Actions to execute after setting voltage + * @thread: Structure holding CPR thread-specific parameters + * @dir: Enumeration for voltage change direction + * @fuse_level: Fuse corner for mem-acc, if supported. + * + * Return: Zero for success or negative number on errors. + */ +static int cpr_post_voltage(struct cpr_thread *thread, + enum voltage_change_dir dir, + int fuse_level) +{ + struct cpr_drv *drv = thread->drv; + + if (drv->tcsr && dir == UP) + cpr_set_acc(drv, fuse_level); + + if (drv->desc->cpr_type == CTRL_TYPE_CPR3) + cpr_write(thread, CPR3_REG_PD_THROTTLE, 0); + + return 0; +} + +/** + * cpr_commit_state() - Set the newly requested voltage + * @thread: Structure holding CPR thread-specific parameters + * + * Return: IRQ_SUCCESS for success, IRQ_NONE if the CPR is disabled. + */ +static int cpr_commit_state(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + int min_uV = 0, max_uV = 0, new_uV = 0, fuse_level = 0; + enum voltage_change_dir dir; + u32 next_irqmask = 0; + int ret, i; + + /* On CPRhardened, control states are managed in firmware */ + if (drv->desc->cpr_type == CTRL_TYPE_CPRH) + return 0; + + for (i = 0; i < drv->desc->num_threads; i++) { + struct cpr_thread *thread = &drv->threads[i]; + + if (!thread->corner) + continue; + + fuse_level = max(fuse_level, + (int) (thread->corner->fuse_corner - + &thread->fuse_corners[0])); + + max_uV = max(max_uV, thread->corner->max_uV); + min_uV = max(min_uV, thread->corner->min_uV); + new_uV = max(new_uV, thread->corner->last_uV); + } + dev_vdbg(drv->dev, "%s: new uV: %d, last uV: %d\n", + __func__, new_uV, drv->last_uV); + + /* + * Safety measure: if the voltage is out of the globally allowed + * range, then go out and warn the user. + * This should *never* happen. + */ + if (new_uV > drv->desc->cpr_max_voltage || + new_uV < drv->desc->cpr_base_voltage) { + dev_warn(drv->dev, "Voltage (%u uV) out of range.", new_uV); + return -EINVAL; + } + + if (new_uV == drv->last_uV || fuse_level == drv->fuse_level_set) + goto out; + + if (fuse_level > drv->fuse_level_set) + dir = UP; + else + dir = DOWN; + + ret = cpr_pre_voltage(thread, fuse_level, dir); + if (ret) + return ret; + + dev_vdbg(drv->dev, "setting voltage: %d\n", new_uV); + + ret = regulator_set_voltage(drv->vreg, new_uV, new_uV); + if (ret) { + dev_err_ratelimited(drv->dev, "failed to set voltage %d: %d\n", new_uV, ret); + return ret; + } + + ret = cpr_post_voltage(thread, fuse_level, dir); + if (ret) + return ret; + + drv->last_uV = new_uV; +out: + if (new_uV > min_uV) + next_irqmask |= CPR3_IRQ_DOWN; + if (new_uV < max_uV) + next_irqmask |= CPR3_IRQ_UP; + + cpr_irq_set(thread, next_irqmask); + + return 0; +} + +static unsigned int cpr_get_cur_perf_state(struct cpr_thread *thread) +{ + return thread->corner ? thread->corner - thread->corners + 1 : 0; +} + +/** + * cpr_scale() - Calculate new voltage for the received direction + * @thread: Structure holding CPR thread-specific parameters + * @dir: Enumeration for voltage change direction + * + * The CPR scales one by one: this function calculates the new + * voltage to set when a voltage-UP or voltage-DOWN request comes + * and stores it into the per-thread structure that gets passed. + */ +static void cpr_scale(struct cpr_thread *thread, enum voltage_change_dir dir) +{ + struct cpr_drv *drv = thread->drv; + const struct cpr_thread_desc *tdesc = thread->desc; + u32 val, error_steps; + int last_uV, new_uV; + struct corner *corner; + + if (dir != UP && dir != DOWN) + return; + + corner = thread->corner; + val = cpr_read(thread, CPR3_REG_RESULT0(tdesc->hw_tid)); + error_steps = val >> CPR3_RESULT0_ERROR_STEPS_SHIFT; + error_steps &= CPR3_RESULT0_ERROR_STEPS_MASK; + + last_uV = corner->last_uV; + + if (dir == UP) { + if (!(val & CPR3_RESULT0_STEP_UP_MASK)) + return; + + /* Calculate new voltage */ + new_uV = last_uV + drv->vreg_step; + new_uV = min(new_uV, corner->max_uV); + + dev_vdbg(drv->dev, "[T%u] UP - new_uV=%d last_uV=%d p-state=%u st=%u\n", + thread->id, new_uV, last_uV, + cpr_get_cur_perf_state(thread), error_steps); + } else { + if (!(val & CPR3_RESULT0_STEP_DN_MASK)) + return; + + /* Calculate new voltage */ + new_uV = last_uV - drv->vreg_step; + new_uV = max(new_uV, corner->min_uV); + dev_vdbg(drv->dev, "[T%u] DOWN - new_uV=%d last_uV=%d p-state=%u st=%u\n", + thread->id, new_uV, last_uV, + cpr_get_cur_perf_state(thread), error_steps); + } + corner->last_uV = new_uV; +} + +/** + * cpr_irq_handler() - Handle CPR3/CPR4 status interrupts + * @irq: Number of the interrupt + * @dev: Pointer to the cpr_thread structure + * + * Handle the interrupts coming from non-hardened CPR HW as to get + * an ok to scale voltages immediately, or to pass error status to + * the hardware (either success/ACK or failure/NACK). + * + * Return: IRQ_SUCCESS for success, IRQ_NONE if the CPR is disabled. + */ +static irqreturn_t cpr_irq_handler(int irq, void *dev) +{ + struct cpr_thread *thread = dev; + struct cpr_drv *drv = thread->drv; + irqreturn_t ret = IRQ_HANDLED; + int i, rc; + enum voltage_change_dir dir = NO_CHANGE; + u32 val; + + mutex_lock(&drv->lock); + + val = cpr_read(thread, CPR3_REG_IRQ_STATUS); + + dev_vdbg(drv->dev, "IRQ_STATUS = %#02x\n", val); + + if (!cpr_ctl_is_enabled(thread)) { + dev_vdbg(drv->dev, "CPR is disabled\n"); + ret = IRQ_NONE; + } else if (cpr_check_any_thread_busy(thread)) { + cpr_irq_clr_nack(thread); + dev_dbg(drv->dev, "CPR measurement is not ready\n"); + } else { + /* + * Following sequence of handling is as per each IRQ's + * priority + */ + if (val & CPR3_IRQ_UP) + dir = UP; + else if (val & CPR3_IRQ_DOWN) + dir = DOWN; + + if (dir != NO_CHANGE) { + for (i = 0; i < drv->desc->num_threads; i++) { + thread = &drv->threads[i]; + cpr_scale(thread, dir); + } + + rc = cpr_commit_state(thread); + if (rc) + cpr_irq_clr_nack(thread); + else + cpr_irq_clr_ack(thread); + } else if (val & CPR3_IRQ_MID) { + dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n"); + } else { + dev_warn(drv->dev, "IRQ occurred for unknown flag (%#08x)\n", val); + schedule_work(&thread->restart_work); + } + } + + mutex_unlock(&drv->lock); + + return ret; +} + +static int cpr_switch(struct cpr_drv *drv) +{ + int i, ret; + bool enabled = false; + + if (drv->desc->cpr_type == CTRL_TYPE_CPRH) + return 0; + + for (i = 0; i < drv->desc->num_threads && !enabled; i++) + enabled = drv->threads[i].enabled; + + dev_vdbg(drv->dev, "%s: enabled = %d\n", __func__, enabled); + + if (enabled == drv->enabled) + return 0; + + if (enabled) { + ret = regulator_enable(drv->vreg); + if (ret) + return ret; + + drv->enabled = enabled; + + for (i = 0; i < drv->desc->num_threads; i++) + if (drv->threads[i].corner) + break; + + if (i < drv->desc->num_threads) { + cpr_irq_clr(&drv->threads[i]); + + cpr_commit_state(&drv->threads[i]); + cpr_ctl_enable(&drv->threads[i]); + } + } else { + for (i = 0; i < drv->desc->num_threads && !enabled; i++) + cpr_ctl_disable(&drv->threads[i]); + + drv->enabled = enabled; + + ret = regulator_disable(drv->vreg); + if (ret < 0) + return ret; + } + + return 0; +} + +/** + * cpr_enable() - Enables a CPR thread + * @thread: Structure holding CPR thread-specific parameters + * + * Return: Zero for success or negative number on errors. + */ +static int cpr_enable(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + int ret; + + dev_dbg(drv->dev, "Enabling thread %d\n", thread->id); + + mutex_lock(&drv->lock); + + thread->enabled = true; + ret = cpr_switch(thread->drv); + + mutex_unlock(&drv->lock); + + return ret; +} + +/** + * cpr_disable() - Disables a CPR thread + * @thread: Structure holding CPR thread-specific parameters + * + * Return: Zero for success or negative number on errors. + */ +static int cpr_disable(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + int ret; + + dev_dbg(drv->dev, "Disabling thread %d\n", thread->id); + + mutex_lock(&drv->lock); + + thread->enabled = false; + ret = cpr_switch(thread->drv); + + mutex_unlock(&drv->lock); + + return ret; +} + +/** + * cpr_configure() - Configure main HW parameters + * @thread: Structure holding CPR thread-specific parameters + * + * This function configures the main CPR hardware parameters, such as + * internal timers (and delays), sensor ownerships, activates and/or + * deactivates cpr-threads and others, as one sequence for all of the + * versions supported in this driver. By design, the function may + * return a success earlier if the sequence for "a previous version" + * has ended. + * + * Context: The CPR must be clocked before calling this function! + * + * Return: Zero for success or negative number on errors. + */ +static int cpr_configure(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + const struct cpr_desc *desc = drv->desc; + const struct cpr_thread_desc *tdesc = thread->desc; + u32 val; + int i; + + /* Disable interrupt and CPR */ + cpr_irq_set(thread, 0); + cpr_write(thread, CPR3_REG_CPR_CTL, 0); + + /* Init and save gcnt */ + drv->gcnt = drv->ref_clk_khz * desc->gcnt_us; + do_div(drv->gcnt, 1000); + + /* Program the delay count for the timer */ + val = drv->ref_clk_khz * desc->timer_delay_us; + do_div(val, 1000); + if (desc->cpr_type == CTRL_TYPE_CPR3) { + cpr_write(thread, CPR3_REG_CPR_TIMER_MID_CONT, val); + + val = drv->ref_clk_khz * desc->timer_updn_delay_us; + do_div(val, 1000); + cpr_write(thread, CPR3_REG_CPR_TIMER_UP_DN_CONT, val); + } else { + cpr_write(thread, CPR3_REG_CPR_TIMER_AUTO_CONT, val); + } + dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val, + desc->timer_delay_us); + + /* Program the control register */ + val = desc->idle_clocks << CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT; + val |= desc->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT; + val |= desc->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT; + cpr_write(thread, CPR3_REG_CPR_CTL, val); + + /* Configure CPR default step quotients */ + val = tdesc->step_quot_init_min << CPR3_CPR_STEP_QUOT_MIN_SHIFT; + val |= tdesc->step_quot_init_max << CPR3_CPR_STEP_QUOT_MAX_SHIFT; + + cpr_write(thread, CPR3_REG_CPR_STEP_QUOT, val); + + /* + * Configure the CPR sensor ownership always on thread 0 + * TODO: SDM845 has different ownership for sensors!! + */ + for (i = tdesc->sensor_range_start; i < tdesc->sensor_range_end; i++) + cpr_write(thread, CPR3_REG_SENSOR_OWNER(i), 0); + + /* Program Consecutive Up & Down */ + val = desc->timer_cons_up << CPR3_THRESH_CONS_UP_SHIFT; + val |= desc->timer_cons_down << CPR3_THRESH_CONS_DOWN_SHIFT; + val |= desc->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT; + val |= desc->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT; + cpr_write(thread, CPR3_REG_THRESH(tdesc->hw_tid), val); + + /* Mask all ring oscillators for all threads initially */ + cpr_write(thread, CPR3_REG_RO_MASK(tdesc->hw_tid), CPR3_RO_MASK); + + /* HW Closed-loop control */ + if (desc->cpr_type == CTRL_TYPE_CPR3) { + cpr_write(thread, CPR3_REG_HW_CLOSED_LOOP_DISABLED, + !desc->hw_closed_loop_en); + } else { + cpr_masked_write(thread, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_HW_CLOSED_LOOP_EN, + desc->hw_closed_loop_en ? + CPR4_MARGIN_ADJ_HW_CLOSED_LOOP_EN : 0); + } + + /* Additional configuration for CPR4 and beyond */ + if (desc->cpr_type < CTRL_TYPE_CPR4) + return 0; + + /* Disable threads initially only on non-hardened CPR4 */ + if (desc->cpr_type == CTRL_TYPE_CPR4) { + cpr_masked_write(thread, CPR4_REG_CPR_MASK_THREAD(1), + CPR4_CPR_MASK_THREAD_DISABLE_THREAD | + CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK, + CPR4_CPR_MASK_THREAD_DISABLE_THREAD | + CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK); + } + + if (tdesc->hw_tid > 0) { + cpr_masked_write(thread, CPR4_REG_MISC, + CPR4_MISC_RESET_STEP_QUOT_LOOP_EN | + CPR4_MISC_THREAD_HAS_ALWAYS_VOTE_EN, + CPR4_MISC_RESET_STEP_QUOT_LOOP_EN | + CPR4_MISC_THREAD_HAS_ALWAYS_VOTE_EN); + } + + val = drv->vreg_step; + do_div(val, 1000); + cpr_masked_write(thread, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_PMIC_STEP_SIZE_MASK, + val << CPR4_MARGIN_ADJ_PMIC_STEP_SIZE_SHIFT); + + cpr_masked_write(thread, CPR4_REG_SAW_ERROR_STEP_LIMIT, + CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK, + desc->vreg_step_down_limit << + CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT); + + cpr_masked_write(thread, CPR4_REG_SAW_ERROR_STEP_LIMIT, + CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK, + desc->vreg_step_up_limit << + CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT); + + cpr_masked_write(thread, CPR4_REG_MARGIN_ADJ_CTL, + CPR4_MARGIN_ADJ_PER_RO_KV_MARGIN_EN, + CPR4_MARGIN_ADJ_PER_RO_KV_MARGIN_EN); + + if (tdesc->hw_tid > 0) { + cpr_masked_write(thread, CPR4_REG_CPR_TIMER_CLAMP, + CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN, + CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN); + } + + /* Settling timer to account for one VDD supply step */ + if (desc->vdd_settle_time_us > 0) { + u32 m = CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK; + u32 s = CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHFT; + + cpr_masked_write(thread, CPR4_REG_MARGIN_TEMP_CORE_TIMERS, + m, desc->vdd_settle_time_us << s); + } + + /* Additional configuration for CPR-hardened */ + if (desc->cpr_type < CTRL_TYPE_CPRH) + return 0; + + /* Settling timer to account for one corner-switch request */ + if (desc->corner_settle_time_us > 0) { + cpr_masked_write(thread, drv->reg_ctl, + CPRH_CTL_MODE_SWITCH_DELAY_MASK, + desc->corner_settle_time_us << + CPRH_CTL_MODE_SWITCH_DELAY_SHIFT); + } + + /* Base voltage and multiplier values for CPRh internal calculations */ + cpr_masked_write(thread, drv->reg_ctl, + CPRH_CTL_BASE_VOLTAGE_MASK, + (DIV_ROUND_UP(desc->cpr_base_voltage, + drv->vreg_step) << + CPRH_CTL_BASE_VOLTAGE_SHIFT)); + + cpr_masked_write(thread, drv->reg_ctl, + CPRH_CTL_VOLTAGE_MULTIPLIER_MASK, + DIV_ROUND_UP(drv->vreg_step, 1000) << + CPRH_CTL_VOLTAGE_MULTIPLIER_SHIFT); + + return 0; +} + + +static int cprh_dummy_set_performance_state(struct generic_pm_domain *domain, + unsigned int state) +{ + return 0; +} + +static int cpr_set_performance_state(struct generic_pm_domain *domain, + unsigned int state) +{ + struct cpr_thread *thread = container_of(domain, struct cpr_thread, pd); + struct cpr_drv *drv = thread->drv; + struct corner *corner, *end; + int ret = 0; + + mutex_lock(&drv->lock); + + dev_dbg(drv->dev, "setting perf state: %u (prev state: %u thread: %u)\n", + state, cpr_get_cur_perf_state(thread), thread->id); + + /* + * Determine new corner we're going to. + * Remove one since lowest performance state is 1. + */ + corner = thread->corners + state - 1; + end = &thread->corners[thread->num_corners - 1]; + if (corner > end || corner < thread->corners) { + ret = -EINVAL; + goto unlock; + } + + cpr_ctl_disable(thread); + + cpr_irq_clr(thread); + if (thread->corner != corner) + cpr_corner_restore(thread, corner); + + ret = cpr_commit_state(thread); + if (ret) + goto unlock; + + cpr_ctl_enable(thread); +unlock: + mutex_unlock(&drv->lock); + + dev_dbg(drv->dev, "set perf state %u on thread %u\n", state, thread->id); + + return ret; +} + +/** + * cpr3_adjust_quot - Adjust the closed-loop quotients + * @thread: Structure holding CPR thread-specific parameters + * + * Calculates the quotient adjustment factor based on closed-loop + * quotients and ring oscillator factor. + * + * Return: Adjusted quotient + */ +static int cpr3_adjust_quot(int ring_osc_factor, int volt_closed_loop) +{ + s64 temp; + + if (ring_osc_factor == 0 || volt_closed_loop == 0) + return 0; + + temp = (s64)(ring_osc_factor * volt_closed_loop); + return (int)div_s64(temp, 1000000); +} + +/** + * cpr_fuse_corner_init() - Calculate fuse corner table + * @thread: Structure holding CPR thread-specific parameters + * + * This function populates the fuse corners table by reading the + * values from the fuses, eventually adjusting them with a fixed + * per-corner offset and doing basic checks about them being + * supported by the regulator that is assigned to this CPR - if + * it is available (on CPR-Hardened, there is no usable vreg, as + * that is protected by the hypervisor). + * + * Return: Zero for success, negative number on error + */ +static int cpr_fuse_corner_init(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + const struct cpr_thread_desc *desc = thread->desc; + const struct cpr_fuse *cpr_fuse = thread->cpr_fuses; + struct fuse_corner_data *fdata; + struct fuse_corner *fuse, *prev_fuse, *end; + int i, ret; + + /* Populate fuse_corner members */ + fuse = thread->fuse_corners; + prev_fuse = &fuse[0]; + end = &fuse[desc->num_fuse_corners - 1]; + fdata = desc->fuse_corner_data; + + for (i = 0; fuse <= end; fuse++, cpr_fuse++, i++, fdata++) { + int factor = cpr_get_ro_factor(desc, i, fuse->ring_osc_idx); + + ret = cpr_populate_fuse_common(drv->dev, fdata, cpr_fuse, + fuse, drv->vreg_step, + desc->init_voltage_width, + desc->init_voltage_step); + if (ret) + return ret; + + /* + * Adjust the fuse quot with per-fuse-corner closed-loop + * voltage adjustment parameters. + */ + fuse->quot += cpr3_adjust_quot(factor, fdata->volt_cloop_adjust); + + /* CPRh: no regulator access... */ + if (drv->desc->cpr_type == CTRL_TYPE_CPRH) + goto skip_pvs_restrict; + + /* Re-check if corner voltage range is supported by regulator */ + ret = cpr_check_vreg_constraints(drv->dev, drv->vreg, fuse); + if (ret) + return ret; + +skip_pvs_restrict: + if (fuse->uV < prev_fuse->uV) + fuse->uV = prev_fuse->uV; + prev_fuse = fuse; + dev_dbg(drv->dev, "fuse corner %d: [%d %d %d] RO%hhu quot %d\n", + i, fuse->min_uV, fuse->uV, fuse->max_uV, + fuse->ring_osc_idx, fuse->quot); + + /* Check if constraints are valid */ + if (fuse->uV < fuse->min_uV || fuse->uV > fuse->max_uV) { + dev_err(drv->dev, "fuse corner %d: Bad voltage range.\n", i); + return -EINVAL; + } + } + + return 0; +} + +static void cpr3_restrict_corner(struct corner *corner, int threshold, + int hysteresis, int step) +{ + if (threshold > corner->min_uV && threshold <= corner->max_uV) { + if (corner->uV >= threshold) { + corner->min_uV = max(corner->min_uV, + threshold - hysteresis); + if (corner->min_uV > corner->uV) + corner->uV = corner->min_uV; + } else { + corner->max_uV = threshold; + corner->max_uV -= step; + } + } +} + +/* + * cprh_corner_adjust_opps() - Set voltage on each CPU OPP table entry + * + * On CPR-Hardened, the voltage level is controlled internally through + * the OSM hardware: in order to initialize the latter, we have to + * communicate the voltage to its driver, so that it will be able to + * write the right parameters (as they have to be set both on the CPRh + * and on the OSM) on it. + * This function is called only for CPRh. + * + * Return: Zero for success, negative number for error. + */ +static int cprh_corner_adjust_opps(struct cpr_thread *thread) +{ + struct corner *corner = thread->corners; + struct cpr_drv *drv = thread->drv; + int i, ret; + + for (i = 0; i < thread->num_corners; i++) { + ret = dev_pm_opp_adjust_voltage(thread->attached_cpu_dev, + corner[i].freq, + corner[i].uV, + corner[i].min_uV, + corner[i].max_uV); + if (ret) + break; + + dev_dbg(drv->dev, "OPP voltage adjusted for %lu kHz, %d uV\n", + corner[i].freq, corner[i].uV); + } + + /* If we couldn't adjust voltage for all corners, something went wrong */ + if (i < thread->num_corners) + return -EINVAL; + + return ret; +} + +/** + * cpr3_corner_init() - Calculate and set-up corners for the CPR HW + * @thread: Structure holding CPR thread-specific parameters + * + * This function calculates all the corner parameters by comparing + * and interpolating the values read from the various set-points + * read from the fuses (also called "fuse corners") to generate and + * program to the CPR a lookup table that describes each voltage + * step, mapped to a performance level (or corner number). + * + * It also programs other essential parameters on the CPR and - if + * we are dealing with CPR-Hardened, it will also enable the internal + * interface between the Operating State Manager (OSM) and the CPRh + * in order to achieve CPU DVFS. + * + * Return: Zero for success, negative number on error + */ +static int cpr3_corner_init(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + const struct cpr_desc *desc = drv->desc; + const struct cpr_thread_desc *tdesc = thread->desc; + const struct cpr_fuse *fuses = thread->cpr_fuses; + int i, ret, total_corners, extra_corners, level, scaling = 0; + unsigned int fnum, fc; + const char *quot_offset; + const struct fuse_corner_data *fdata; + struct fuse_corner *fuse, *prev_fuse; + struct corner *corner, *prev_corner, *end; + struct corner_data *cdata; + struct dev_pm_opp *opp; + unsigned long freq; + u32 ring_osc_mask = CPR3_RO_MASK, min_quotient = U32_MAX; + + corner = thread->corners; + prev_corner = &thread->corners[0]; + end = &corner[thread->num_corners - 1]; + + cdata = devm_kcalloc(drv->dev, thread->num_corners + drv->extra_corners, + sizeof(struct corner_data), GFP_KERNEL); + if (!cdata) + return -ENOMEM; + + for (level = 1; level <= thread->num_corners; level++) { + opp = dev_pm_opp_find_level_exact(&thread->pd.dev, level); + if (IS_ERR(opp)) + return -EINVAL; + + /* + * If there is only one specified qcom,opp-fuse-level, then + * it is assumed that this only one is global and valid for + * all IDs, so try to get the specific one but, on failure, + * go for the global one. + */ + fc = cpr_get_fuse_corner(opp, thread->id); + if (fc == 0) { + fc = cpr_get_fuse_corner(opp, 0); + if (fc == 0) { + dev_err(drv->dev, "qcom,opp-fuse-level is missing!\n"); + dev_pm_opp_put(opp); + return -EINVAL; + } + } + fnum = fc - 1; + + freq = cpr_get_opp_hz_for_req(opp, thread->attached_cpu_dev); + if (!freq) { + thread->num_corners = max(level - 1, 0); + end = &thread->corners[thread->num_corners - 1]; + break; + } + + /* + * If any post-vadj (open/closed loop) is not specified, then + * it's zero, meaning that it is not required for this corner. + */ + cpr_get_corner_post_vadj(opp, thread->id, + &cdata[level - 1].oloop_vadj, + &cdata[level - 1].cloop_vadj); + cdata[level - 1].fuse_corner = fnum; + cdata[level - 1].freq = freq; + + fuse = &thread->fuse_corners[fnum]; + dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n", + freq, dev_pm_opp_get_level(opp) - 1, fnum); + if (freq > fuse->max_freq) + fuse->max_freq = freq; + dev_pm_opp_put(opp); + + /* + * Make sure that the frequencies in the table are in ascending + * order, as this is critical for the algorithm to work. + */ + if (cdata[level - 2].freq > freq) { + dev_err(drv->dev, "Frequency table not in ascending order.\n"); + return -EINVAL; + } + } + + if (thread->num_corners < 2) { + dev_err(drv->dev, "need at least 2 OPPs to use CPR\n"); + return -EINVAL; + } + + /* + * Get the quotient adjustment scaling factor, according to: + * + * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1)) + * / (freq(corner_N) - freq(corner_N-1)), max_factor) + * + * QUOT(corner_N): quotient read from fuse for fuse corner N + * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1) + * freq(corner_N): max frequency in MHz supported by fuse corner N + * freq(corner_N-1): max frequency in MHz supported by fuse corner + * (N - 1) + * + * Then walk through the corners mapped to each fuse corner + * and calculate the quotient adjustment for each one using the + * following formula: + * + * quot_adjust = (freq_max - freq_corner) * scaling / 1000 + * + * freq_max: max frequency in MHz supported by the fuse corner + * freq_corner: frequency in MHz corresponding to the corner + * scaling: calculated from above equation + * + * + * + + + * | v | + * q | f c o | f c + * u | c l | c + * o | f t | f + * t | c a | c + * | c f g | c f + * | e | + * +--------------- +---------------- + * 0 1 2 3 4 5 6 0 1 2 3 4 5 6 + * corner corner + * + * c = corner + * f = fuse corner + * + */ + for (i = 0; corner <= end; corner++, i++) { + unsigned long freq_diff_mhz; + int ro_fac, vadj, prev_quot; + + fnum = cdata[i].fuse_corner; + fdata = &tdesc->fuse_corner_data[fnum]; + quot_offset = fuses[fnum].quotient_offset; + fuse = &thread->fuse_corners[fnum]; + ring_osc_mask &= (u16)(~BIT(fuse->ring_osc_idx)); + if (fnum) + prev_fuse = &thread->fuse_corners[fnum - 1]; + else + prev_fuse = NULL; + + corner->fuse_corner = fuse; + corner->freq = cdata[i].freq; + corner->uV = fuse->uV; + + if (prev_fuse) { + if (prev_fuse->ring_osc_idx == fuse->ring_osc_idx) + quot_offset = NULL; + + scaling = cpr_calculate_scaling(quot_offset, drv->dev, + fdata, corner); + if (scaling < 0) + return scaling; + + freq_diff_mhz = fuse->max_freq - corner->freq; + do_div(freq_diff_mhz, 1000000); /* now in MHz */ + + corner->quot_adjust = scaling * freq_diff_mhz; + do_div(corner->quot_adjust, 1000); + + /* Fine-tune QUOT (closed-loop) based on fixed values */ + ro_fac = cpr_get_ro_factor(tdesc, fnum, fuse->ring_osc_idx); + vadj = cdata[i].cloop_vadj; + corner->quot_adjust -= cpr3_adjust_quot(ro_fac, vadj); + dev_vdbg(drv->dev, "Quot fine-tuning to %d for post-vadj=%d\n", + corner->quot_adjust, vadj); + + /* + * Make sure that we scale (up) monotonically. + * P.S.: Fuse quots can never be descending. + */ + prev_quot = prev_corner->fuse_corner->quot; + prev_quot -= prev_corner->quot_adjust; + if (fuse->quot - corner->quot_adjust < prev_quot) { + int new_adj = prev_corner->fuse_corner->quot; + new_adj -= fuse->quot; + dev_vdbg(drv->dev, "Monotonic increase forced: %d->%d\n", + corner->quot_adjust, new_adj); + corner->quot_adjust = new_adj; + } + + corner->uV = cpr_interpolate(corner, + drv->vreg_step, fdata); + } + /* Negative fuse quotients are nonsense. */ + if (fuse->quot < corner->quot_adjust) + return -EINVAL; + + min_quotient = min(min_quotient, + (u32)(fuse->quot - corner->quot_adjust)); + + /* Fine-tune voltages (open-loop) based on fixed values */ + corner->uV += cdata[i].oloop_vadj; + dev_dbg(drv->dev, "Voltage fine-tuning to %d for post-vadj=%d\n", + corner->uV, cdata[i].oloop_vadj); + + corner->max_uV = fuse->max_uV; + corner->min_uV = fuse->min_uV; + corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV); + dev_vdbg(drv->dev, "Clamped after interpolation: [%d %d %d]\n", + corner->min_uV, corner->uV, corner->max_uV); + + /* Make sure that we scale monotonically here, too. */ + if (corner->uV < prev_corner->uV) + corner->uV = prev_corner->uV; + + corner->last_uV = corner->uV; + + /* Reduce the ceiling voltage if needed */ + if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV) + corner->max_uV = corner->uV; + else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV) + corner->max_uV = max(corner->min_uV, fuse->uV); + + corner->min_uV = max(corner->max_uV - fdata->range_uV, + corner->min_uV); + + /* + * Adjust per-corner floor and ceiling voltages so that + * they do not overlap the memory Array Power Mux (APM) + * nor the Memory Accelerator (MEM-ACC) threshold voltages. + */ + if (desc->apm_threshold) + cpr3_restrict_corner(corner, desc->apm_threshold, + desc->apm_hysteresis, + drv->vreg_step); + if (desc->mem_acc_threshold) + cpr3_restrict_corner(corner, desc->mem_acc_threshold, + 0, drv->vreg_step); + + prev_corner = corner; + dev_dbg(drv->dev, "corner %d: [%d %d %d] scaling %d quot %d\n", i, + corner->min_uV, corner->uV, corner->max_uV, scaling, + fuse->quot - corner->quot_adjust); + } + + /* Additional setup for CPRh only */ + if (desc->cpr_type < CTRL_TYPE_CPRH) + return 0; + + /* If the OPPs can't be adjusted, programming the CPRh is useless */ + ret = cprh_corner_adjust_opps(thread); + if (ret) { + dev_err(drv->dev, "Cannot adjust CPU OPP voltages: %d\n", ret); + return ret; + } + + total_corners = thread->num_corners; + extra_corners = drv->extra_corners; + + /* If the APM extra corner exists, add it now. */ + if (desc->apm_crossover && desc->apm_threshold && extra_corners) { + /* Program the APM crossover corner on the CPR-Hardened */ + thread->corners[total_corners].uV = desc->apm_crossover; + thread->corners[total_corners].min_uV = desc->apm_crossover; + thread->corners[total_corners].max_uV = desc->apm_crossover; + thread->corners[total_corners].is_open_loop = true; + + /* + * We have calculated the APM parameters for this clock plan: + * make the APM *threshold* available to external callers. + * The crossover is used only internally in the CPR. + */ + thread->ext_data.apm_threshold_uV = desc->apm_threshold; + + dev_dbg(drv->dev, "corner %d (APM): [%d %d %d] Open-Loop\n", + total_corners, desc->apm_crossover, + desc->apm_crossover, desc->apm_crossover); + + total_corners++; + extra_corners--; + } + + if (desc->mem_acc_threshold && extra_corners) { + /* Program the Memory Accelerator threshold corner to CPRh */ + thread->corners[total_corners].uV = desc->mem_acc_threshold; + thread->corners[total_corners].min_uV = desc->mem_acc_threshold; + thread->corners[total_corners].max_uV = desc->mem_acc_threshold; + thread->corners[total_corners].is_open_loop = true; + + /* + * We have calculated a mem-acc threshold for this clock plan: + * make it available to external callers. + */ + thread->ext_data.mem_acc_threshold_uV = desc->mem_acc_threshold; + + dev_dbg(drv->dev, "corner %d (MEMACC): [%d %d %d] Open-Loop\n", + total_corners, desc->mem_acc_threshold, + desc->mem_acc_threshold, desc->mem_acc_threshold); + + total_corners++; + extra_corners--; + } + + /* + * If there are any extra corners left, it means that even though we + * expect to fill in both APM and MEM-ACC crossovers, one couldn't + * satisfy requirements, which means that the specified parameters + * are wrong: in this case, inform the user and bail out, otherwise + * if we go on writing the (invalid) table to the CPR-Hardened, the + * hardware (in this case, the CPU) will surely freeze and crash. + */ + if (unlikely(extra_corners)) { + dev_err(drv->dev, "APM/MEM-ACC corners: bad parameters.\n"); + return -EINVAL; + } + /* Reassign extra_corners, as we have to exclude delta_quot for them */ + extra_corners = drv->extra_corners; + + /* Disable the interface between OSM and CPRh */ + cpr_masked_write(thread, drv->reg_ctl, + CPRH_CTL_OSM_ENABLED, 0); + + /* Program the GCNT before unmasking ring oscillator(s) */ + for (i = 0; i < CPR3_RO_COUNT; i++) { + if (!(ring_osc_mask & BIT(i))) { + cpr_write(thread, CPR3_REG_GCNT(i), drv->gcnt); + dev_vdbg(drv->dev, "RO%d gcnt=%d\n", i, drv->gcnt); + } + } + + /* + * Unmask the ring oscillator(s) that we're going to use: it seems + * to be mandatory to do this *before* sending the rest of the + * CPRhardened specific configuration. + */ + dev_dbg(drv->dev, "Unmasking ring oscillators with mask 0x%x\n", ring_osc_mask); + cpr_write(thread, CPR3_REG_RO_MASK(tdesc->hw_tid), ring_osc_mask); + + /* Setup minimum quotients for ring oscillators */ + for (i = 0; i < CPR3_RO_COUNT; i++) { + u32 tgt_quot_reg = CPR3_REG_TARGET_QUOT(tdesc->hw_tid, i); + u32 tgt_quot_val = 0; + + if (!(ring_osc_mask & BIT(i))) + tgt_quot_val = min_quotient; + + cpr_write(thread, tgt_quot_reg, tgt_quot_val); + dev_vdbg(drv->dev, "Programmed min quotient %u for Ring Oscillator %d\n", + tgt_quot_val, tgt_quot_reg); + } + + for (i = 0; i < total_corners; i++) { + int volt_oloop_steps, volt_floor_steps, delta_quot_steps; + int ring_osc; + u32 val; + + fnum = cdata[i].fuse_corner; + fuse = &thread->fuse_corners[fnum]; + + val = thread->corners[i].uV - desc->cpr_base_voltage; + volt_oloop_steps = DIV_ROUND_UP(val, drv->vreg_step); + + val = thread->corners[i].min_uV - desc->cpr_base_voltage; + volt_floor_steps = DIV_ROUND_UP(val, drv->vreg_step); + + /* + * If we are accessing corners that are not used as + * an active DCVS set-point, then always select RO 0 + * and zero out the delta quotient. + */ + if (i >= thread->num_corners) { + ring_osc = 0; + delta_quot_steps = 0; + } else { + ring_osc = fuse->ring_osc_idx; + val = fuse->quot - thread->corners[i].quot_adjust; + val -= min_quotient; + delta_quot_steps = DIV_ROUND_UP(val, + CPRH_DELTA_QUOT_STEP_FACTOR); + } + + if (volt_oloop_steps > CPRH_CORNER_INIT_VOLTAGE_MAX_VALUE || + volt_floor_steps > CPRH_CORNER_FLOOR_VOLTAGE_MAX_VALUE || + delta_quot_steps > CPRH_CORNER_QUOT_DELTA_MAX_VALUE) { + dev_err(drv->dev, "Invalid cfg: oloop=%d, floor=%d, delta=%d\n", + volt_oloop_steps, volt_floor_steps, + delta_quot_steps); + return -EINVAL; + } + /* Green light: Go, Go, Go! */ + + /* Set number of open-loop steps */ + val = volt_oloop_steps << CPRH_CORNER_INIT_VOLTAGE_SHIFT; + val &= CPRH_CORNER_INIT_VOLTAGE_MASK; + + /* Set number of floor voltage steps */ + val |= (volt_floor_steps << CPRH_CORNER_FLOOR_VOLTAGE_SHIFT) & + CPRH_CORNER_FLOOR_VOLTAGE_MASK; + + /* Set number of target quotient delta steps */ + val |= (delta_quot_steps << CPRH_CORNER_QUOT_DELTA_SHIFT) & + CPRH_CORNER_QUOT_DELTA_MASK; + + /* Select ring oscillator for this corner */ + val |= (ring_osc << CPRH_CORNER_RO_SEL_SHIFT) & + CPRH_CORNER_RO_SEL_MASK; + + /* Open loop corner is usually APM/ACC crossover */ + if (thread->corners[i].is_open_loop) { + dev_dbg(drv->dev, "Disabling Closed-Loop on corner %d\n", i); + val |= CPRH_CORNER_CPR_CL_DISABLE; + } + cpr_write(thread, CPRH_REG_CORNER(drv, tdesc->hw_tid, i), val); + + dev_dbg(drv->dev, "steps [%d]: open-loop %d, floor %d, delta_quot %d\n", + i, volt_oloop_steps, volt_floor_steps, + delta_quot_steps); + } + + /* YAY! Setup is done! Enable the internal loop to start CPR. */ + cpr_masked_write(thread, CPR3_REG_CPR_CTL, + CPR3_CPR_CTL_LOOP_EN_MASK, + CPR3_CPR_CTL_LOOP_EN_MASK); + + /* + * All the writes are going through before enabling internal + * communication between the OSM and the CPRh controllers + * because we are never using relaxed accessors, but should + * we use them, it would be critical to issue a barrier here, + * otherwise there is a high risk of hardware lockups due to + * under-voltage for the selected CPU clock. + * + * Please note that the CPR-hardened gets set-up in Linux but + * then gets actually used in firmware (and only by the OSM); + * after handing it off we will have no more control on it. + */ + + /* Enable the interface between OSM and CPRh */ + cpr_masked_write(thread, drv->reg_ctl, + CPRH_CTL_OSM_ENABLED, + CPRH_CTL_OSM_ENABLED); + + /* On success, free cdata manually */ + devm_kfree(drv->dev, cdata); + return 0; +} + +/** + * cpr3_init_parameters() - Initialize CPR global parameters + * @drv: Main driver structure + * + * Initial "integrity" checks and setup for the thread-independent parameters. + * + * Return: Zero for success, negative number on error + */ +static int cpr3_init_parameters(struct cpr_drv *drv) +{ + const struct cpr_desc *desc = drv->desc; + struct clk *clk; + + clk = devm_clk_get(drv->dev, "ref"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + drv->ref_clk_khz = clk_get_rate(clk); + do_div(drv->ref_clk_khz, 1000); + + /* On CPRh this clock is not always-on... */ + if (desc->cpr_type == CTRL_TYPE_CPRH) + clk_prepare_enable(clk); + else + devm_clk_put(drv->dev, clk); + + if (desc->timer_cons_up > CPR3_THRESH_CONS_UP_MASK || + desc->timer_cons_down > CPR3_THRESH_CONS_DOWN_MASK || + desc->up_threshold > CPR3_THRESH_UP_THRESH_MASK || + desc->down_threshold > CPR3_THRESH_DOWN_THRESH_MASK || + desc->idle_clocks > CPR3_CPR_CTL_IDLE_CLOCKS_MASK || + desc->count_mode > CPR3_CPR_CTL_COUNT_MODE_MASK || + desc->count_repeat > CPR3_CPR_CTL_COUNT_REPEAT_MASK) + return -EINVAL; + + /* + * Read the CPR version register only from CPR3 onwards: + * this is needed to get the additional register offsets. + * + * Note: When threaded, even if multi-controller, there + * is no chance to have different versions at the + * same time in the same domain, so it is safe to + * check this only on the first controller/thread. + */ + drv->cpr_hw_rev = cpr_read(&drv->threads[0], + CPR3_REG_CPR_VERSION); + dev_dbg(drv->dev, "CPR hardware revision: 0x%x\n", drv->cpr_hw_rev); + + if (drv->cpr_hw_rev >= CPRH_CPR_VERSION_4P5) { + drv->reg_corner = 0x3500; + drv->reg_corner_tid = 0xa0; + drv->reg_ctl = 0x3a80; + drv->reg_status = 0x3a84; + } else { + drv->reg_corner = 0x3a00; + drv->reg_corner_tid = 0; + drv->reg_ctl = 0x3aa0; + drv->reg_status = 0x3aa4; + } + + dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n", + desc->up_threshold, desc->down_threshold); + + return 0; +} + +/** + * cpr3_find_initial_corner() - Finds boot-up p-state and enables CPR + * @thread: Structure holding CPR thread-specific parameters + * + * Differently from CPRv1, from CPRv3 onwards when we successfully find + * the target boot-up performance state, we must refresh the HW + * immediately to guarantee system stability and to avoid overheating + * during the boot process, thing that would more likely happen without + * this driver doing its job. + * + * Return: Zero for success, negative number on error + */ +static int cpr3_find_initial_corner(struct cpr_thread *thread) +{ + struct cpr_drv *drv = thread->drv; + struct corner *corner; + int uV, idx; + + idx = cpr_find_initial_corner(drv->dev, thread->cpu_clk, + thread->corners, + thread->num_corners); + if (idx < 0) + return idx; + + cpr_ctl_disable(thread); + + corner = &thread->corners[idx]; + cpr_corner_restore(thread, corner); + + uV = regulator_get_voltage(drv->vreg); + uV = clamp(uV, corner->min_uV, corner->max_uV); + + corner->last_uV = uV; + if (!drv->last_uV) + drv->last_uV = uV; + + cpr_commit_state(thread); + thread->enabled = true; + cpr_switch(drv); + + return 0; +} + +static const int msm8998_gold_scaling_factor[][CPR3_RO_COUNT] = { + /* Fuse Corner 0 */ + { + 2857, 3057, 2828, 2952, 2699, 2798, 2446, 2631, + 2629, 2578, 2244, 3344, 3289, 3137, 3164, 2655 + }, + /* Fuse Corner 1 */ + { + 2857, 3057, 2828, 2952, 2699, 2798, 2446, 2631, + 2629, 2578, 2244, 3344, 3289, 3137, 3164, 2655 + }, + /* Fuse Corner 2 */ + { + 2603, 2755, 2676, 2777, 2573, 2685, 2465, 2610, + 2312, 2423, 2243, 3104, 3022, 3036, 2740, 2303 + }, + /* Fuse Corner 3 */ + { + 1901, 2016, 2096, 2228, 2034, 2161, 2077, 2188, + 1565, 1870, 1925, 2235, 2205, 2413, 1762, 1478 + } +}; + +static const int msm8998_silver_scaling_factor[][CPR3_RO_COUNT] = { + /* Fuse Corner 0 */ + { + 2595, 2794, 2577, 2762, 2471, 2674, 2199, 2553, + 3189, 3255, 3192, 2962, 3054, 2982, 2042, 2945 + }, + /* Fuse Corner 1 */ + { + 2595, 2794, 2577, 2762, 2471, 2674, 2199, 2553, + 3189, 3255, 3192, 2962, 3054, 2982, 2042, 2945 + }, + /* Fuse Corner 2 */ + { + 2391, 2550, 2483, 2638, 2382, 2564, 2259, 2555, + 2766, 3041, 2988, 2935, 2873, 2688, 2013, 2784 + }, + /* Fuse Corner 3 */ + { + 2066, 2153, 2300, 2434, 2220, 2386, 2288, 2465, + 2028, 2511, 2487, 2734, 2554, 2117, 1892, 2377 + } +}; + +static const struct cpr_thread_desc msm8998_thread_gold = { + .controller_id = 1, + .hw_tid = 0, + .ro_scaling_factor = msm8998_gold_scaling_factor, + .ro_avail_corners = ARRAY_SIZE(msm8998_gold_scaling_factor), + .sensor_range_start = 0, + .sensor_range_end = 9, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 9, + .step_quot_init_max = 14, + .num_fuse_corners = 4, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 756000, + .max_uV = 828000, + .min_uV = 568000, + .range_uV = 32000, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 8000, + .max_volt_scale = 4, + .max_quot_scale = 10, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 756000, + .max_uV = 900000, + .min_uV = 624000, + .range_uV = 32000, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 320, + .max_quot_scale = 350, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 828000, + .max_uV = 952000, + .min_uV = 632000, + .range_uV = 32000, + .volt_cloop_adjust = 12000, + .volt_oloop_adjust = 12000, + .max_volt_scale = 620, + .max_quot_scale = 750, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 3 */ + { + .ref_uV = 1056000, + .max_uV = 1136000, + .min_uV = 772000, + .range_uV = 40000, + .volt_cloop_adjust = 50000, + .volt_oloop_adjust = 52000, + .max_volt_scale = 580, + .max_quot_scale = 1040, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_thread_desc msm8998_thread_silver = { + .controller_id = 0, + .hw_tid = 0, + .ro_scaling_factor = msm8998_silver_scaling_factor, + .ro_avail_corners = ARRAY_SIZE(msm8998_silver_scaling_factor), + .sensor_range_start = 0, + .sensor_range_end = 6, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 11, + .step_quot_init_max = 12, + .num_fuse_corners = 4, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 688000, + .max_uV = 828000, + .min_uV = 568000, + .range_uV = 32000, + .volt_cloop_adjust = 20000, + .volt_oloop_adjust = 40000, + .max_volt_scale = 4, + .max_quot_scale = 10, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 756000, + .max_uV = 900000, + .min_uV = 632000, + .range_uV = 32000, + .volt_cloop_adjust = 26000, + .volt_oloop_adjust = 24000, + .max_volt_scale = 500, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 828000, + .max_uV = 952000, + .min_uV = 664000, + .range_uV = 32000, + .volt_cloop_adjust = 12000, + .volt_oloop_adjust = 12000, + .max_volt_scale = 280, + .max_quot_scale = 650, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + + }, + /* fuse corner 3 */ + { + .ref_uV = 1056000, + .max_uV = 1056000, + .min_uV = 772000, + .range_uV = 40000, + .volt_cloop_adjust = 30000, + .volt_oloop_adjust = 30000, + .max_volt_scale = 430, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_desc msm8998_cpr_desc = { + .cpr_type = CTRL_TYPE_CPRH, + .num_threads = 2, + .mem_acc_threshold = 852000, + .apm_threshold = 800000, + .apm_crossover = 880000, + .apm_hysteresis = 0, + .cpr_base_voltage = 352000, + .cpr_max_voltage = 1200000, + .timer_delay_us = 5000, + .timer_cons_up = 0, + .timer_cons_down = 2, + .up_threshold = 2, + .down_threshold = 2, + .idle_clocks = 15, + .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN, + .count_repeat = 14, + .gcnt_us = 1, + .vreg_step_fixed = 4000, + .vreg_step_up_limit = 1, + .vreg_step_down_limit = 1, + .vdd_settle_time_us = 34, + .corner_settle_time_us = 6, + .reduce_to_corner_uV = true, + .hw_closed_loop_en = true, + .threads = (const struct cpr_thread_desc *[]) { + &msm8998_thread_silver, + &msm8998_thread_gold, + }, +}; + +static const struct cpr_acc_desc msm8998_cpr_acc_desc = { + .cpr_desc = &msm8998_cpr_desc, +}; + +static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = { + /* Same RO factors for all fuse corners */ + { + 4040, 3230, 0, 2210, 2560, 2450, 2230, 2220, + 2410, 2300, 2560, 2470, 1600, 3120, 2620, 2280 + } +}; + +static const int sdm630_silver_scaling_factor[][CPR3_RO_COUNT] = { + /* Same RO factors for all fuse corners */ + { + 3600, 3600, 3830, 2430, 2520, 2700, 1790, 1760, + 1970, 1880, 2110, 2010, 2510, 4900, 4370, 4780, + } +}; + +static const struct cpr_thread_desc sdm630_thread_gold = { + .controller_id = 0, + .hw_tid = 0, + .ro_scaling_factor = sdm630_gold_scaling_factor, + .ro_avail_corners = ARRAY_SIZE(sdm630_gold_scaling_factor), + .sensor_range_start = 0, + .sensor_range_end = 6, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 12, + .step_quot_init_max = 14, + .num_fuse_corners = 5, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 644000, + .max_uV = 724000, + .min_uV = 588000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 15000, + .max_volt_scale = 10, + .max_quot_scale = 300, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 788000, + .max_uV = 788000, + .min_uV = 652000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 5000, + .max_volt_scale = 320, + .max_quot_scale = 275, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 868000, + .max_uV = 868000, + .min_uV = 712000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 5000, + .max_volt_scale = 350, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 3 */ + { + .ref_uV = 988000, + .max_uV = 988000, + .min_uV = 784000, + .range_uV = 66000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 0, + .max_volt_scale = 868, + .max_quot_scale = 980, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 4 */ + { + .ref_uV = 1068000, + .max_uV = 1068000, + .min_uV = 844000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 0, + .max_volt_scale = 868, + .max_quot_scale = 980, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_thread_desc sdm630_thread_silver = { + .controller_id = 1, + .hw_tid = 0, + .ro_scaling_factor = sdm630_silver_scaling_factor, + .ro_avail_corners = ARRAY_SIZE(sdm630_silver_scaling_factor), + .sensor_range_start = 0, + .sensor_range_end = 6, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 12, + .step_quot_init_max = 14, + .num_fuse_corners = 3, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 644000, + .max_uV = 724000, + .min_uV = 588000, + .range_uV = 32000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 0, + .max_volt_scale = 10, + .max_quot_scale = 360, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 788000, + .max_uV = 788000, + .min_uV = 652000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 0, + .max_volt_scale = 500, + .max_quot_scale = 550, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 1068000, + .max_uV = 1068000, + .min_uV = 800000, + .range_uV = 40000, + .volt_cloop_adjust = -30000, + .volt_oloop_adjust = 0, + .max_volt_scale = 2370, + .max_quot_scale = 550, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_desc sdm630_cpr_desc = { + .cpr_type = CTRL_TYPE_CPRH, + .num_threads = 2, + .apm_threshold = 872000, + .apm_crossover = 872000, + .apm_hysteresis = 20000, + .cpr_base_voltage = 400000, + .cpr_max_voltage = 1300000, + .timer_delay_us = 5000, + .timer_cons_up = 0, + .timer_cons_down = 2, + .up_threshold = 2, + .down_threshold = 2, + .idle_clocks = 15, + .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN, + .count_repeat = 14, + .gcnt_us = 1, + .vreg_step_fixed = 4000, + .vreg_step_up_limit = 1, + .vreg_step_down_limit = 1, + .vdd_settle_time_us = 34, + .corner_settle_time_us = 5, + .reduce_to_corner_uV = true, + .hw_closed_loop_en = true, + .threads = (const struct cpr_thread_desc *[]) { + &sdm630_thread_gold, + &sdm630_thread_silver, + }, +}; + +static const struct cpr_acc_desc sdm630_cpr_acc_desc = { + .cpr_desc = &sdm630_cpr_desc, +}; + +static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + +static int cpr_power_off(struct generic_pm_domain *domain) +{ + struct cpr_thread *thread = container_of(domain, struct cpr_thread, pd); + + return cpr_disable(thread); +} + +static int cpr_power_on(struct generic_pm_domain *domain) +{ + struct cpr_thread *thread = container_of(domain, struct cpr_thread, pd); + + return cpr_enable(thread); +} + +static void cpr_pd_detach_dev(struct generic_pm_domain *domain, + struct device *dev) +{ + struct cpr_thread *thread = container_of(domain, struct cpr_thread, pd); + struct cpr_drv *drv = thread->drv; + + mutex_lock(&drv->lock); + + dev_dbg(drv->dev, "detach callback for: %s\n", dev_name(dev)); + thread->attached_cpu_dev = NULL; + + mutex_unlock(&drv->lock); +} + +static int cpr_pd_attach_dev(struct generic_pm_domain *domain, + struct device *dev) +{ + struct cpr_thread *thread = container_of(domain, struct cpr_thread, pd); + struct cpr_drv *drv = thread->drv; + const struct acc_desc *acc_desc = drv->acc_desc; + bool cprh_opp_remove_table = false; + int ret = 0; + + mutex_lock(&drv->lock); + + dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev)); + + /* + * This driver only supports scaling voltage for a CPU cluster + * where all CPUs in the cluster share a single regulator. + * Therefore, save the struct device pointer only for the first + * CPU device that gets attached. There is no need to do any + * additional initialization when further CPUs get attached. + * This is not an error condition. + */ + if (thread->attached_cpu_dev) + goto unlock; + + /* + * cpr_scale_voltage() requires the direction (if we are changing + * to a higher or lower OPP). The first time + * cpr_set_performance_state() is called, there is no previous + * performance state defined. Therefore, we call + * cpr_find_initial_corner() that gets the CPU clock frequency + * set by the bootloader, so that we can determine the direction + * the first time cpr_set_performance_state() is called. + */ + thread->cpu_clk = devm_clk_get(dev, NULL); + if (drv->desc->cpr_type < CTRL_TYPE_CPRH && IS_ERR(thread->cpu_clk)) { + ret = PTR_ERR(thread->cpu_clk); + if (ret != -EPROBE_DEFER) + dev_err(drv->dev, "could not get cpu clk: %d\n", ret); + goto unlock; + } + thread->attached_cpu_dev = dev; + + /* + * We are exporting the APM and MEM-ACC thresholds to the caller; + * while APM is necessary in the CPU CPR case, MEM-ACC may not be, + * depending on the SoC and on fuses. + * Initialize both to an invalid value, so that the caller can check + * if they got calculated or read from fuses in this driver. + */ + thread->ext_data.apm_threshold_uV = -1; + thread->ext_data.mem_acc_threshold_uV = -1; + dev_set_drvdata(thread->attached_cpu_dev, &thread->ext_data); + + dev_dbg(drv->dev, "using cpu clk from: %s\n", + dev_name(thread->attached_cpu_dev)); + + /* + * Everything related to (virtual) corners has to be initialized + * here, when attaching to the power domain, since we need to know + * the maximum frequency for each fuse corner, and this is only + * available after the cpufreq driver has attached to us. + * The reason for this is that we need to know the highest + * frequency associated with each fuse corner. + */ + ret = dev_pm_opp_get_opp_count(&thread->pd.dev); + if (ret < 0) { + dev_err(drv->dev, "could not get OPP count\n"); + thread->attached_cpu_dev = NULL; + goto unlock; + } + thread->num_corners = ret; + + thread->corners = devm_kcalloc(drv->dev, + thread->num_corners + + drv->extra_corners, + sizeof(*thread->corners), + GFP_KERNEL); + if (!thread->corners) { + ret = -ENOMEM; + goto unlock; + } + + /* + * If we are on CPR-Hardened we have to make sure that the attached + * device has a OPP table installed, as we're going to modify it here + * with our calculations based on qfprom values. + */ + if (drv->desc->cpr_type == CTRL_TYPE_CPRH) { + ret = dev_pm_opp_of_add_table(dev); + if (ret && ret != -EEXIST) { + dev_err(drv->dev, "Cannot add table: %d\n", ret); + goto unlock; + } + cprh_opp_remove_table = true; + } + + ret = cpr3_corner_init(thread); + if (ret) + goto exit; + + if (drv->desc->cpr_type < CTRL_TYPE_CPRH) { + ret = cpr3_find_initial_corner(thread); + if (ret) + goto exit; + + if (acc_desc->config) + regmap_multi_reg_write(drv->tcsr, acc_desc->config, + acc_desc->num_regs_per_fuse); + + /* Enable ACC if required */ + if (acc_desc->enable_mask) + regmap_update_bits(drv->tcsr, acc_desc->enable_reg, + acc_desc->enable_mask, + acc_desc->enable_mask); + } + dev_info(drv->dev, "thread %d initialized with %u OPPs\n", + thread->id, thread->num_corners); +exit: + /* + * If we are on CPRh and we reached an error condition, we installed + * the OPP table but we haven't done any setup on it, nor we ever will. + * In order to leave a clean state, remove the table. + */ + if (ret && cprh_opp_remove_table) + dev_pm_opp_of_remove_table(thread->attached_cpu_dev); +unlock: + mutex_unlock(&drv->lock); + + return ret; +} + +static int cpr3_debug_info_show(struct seq_file *s, void *unused) +{ + u32 ro_sel, ctl, irq_status, reg, quot; + struct cpr_thread *thread = s->private; + struct corner *corner = thread->corners; + struct fuse_corner *fuse = thread->fuse_corners; + unsigned int i; + + const struct { + const char *name; + uint32_t mask; + uint8_t shift; + } result0_fields[] = { + { "busy", 1, 0 }, + { "step_dn", 1, 1 }, + { "step_up", 1, 2 }, + { "error_steps", CPR3_RESULT0_ERROR_STEPS_MASK, + CPR3_RESULT0_ERROR_STEPS_SHIFT }, + { "error", CPR3_RESULT0_ERROR_MASK, CPR3_RESULT0_ERROR_SHIFT }, + { "negative", 1, 20 }, + }, result1_fields[] = { + { "quot_min", CPR3_RESULT1_QUOT_MIN_MASK, + CPR3_RESULT1_QUOT_MIN_SHIFT }, + { "quot_max", CPR3_RESULT1_QUOT_MAX_MASK, + CPR3_RESULT1_QUOT_MAX_SHIFT }, + { "ro_min", CPR3_RESULT1_RO_MIN_MASK, + CPR3_RESULT1_RO_MIN_SHIFT }, + { "ro_max", CPR3_RESULT1_RO_MAX_MASK, + CPR3_RESULT1_RO_MAX_SHIFT }, + }, result2_fields[] = { + { "qout_step_min", CPR3_RESULT2_STEP_QUOT_MIN_MASK, + CPR3_RESULT2_STEP_QUOT_MIN_SHIFT }, + { "qout_step_max", CPR3_RESULT2_STEP_QUOT_MAX_MASK, + CPR3_RESULT2_STEP_QUOT_MAX_SHIFT }, + { "sensor_min", CPR3_RESULT2_SENSOR_MIN_MASK, + CPR3_RESULT2_SENSOR_MIN_SHIFT }, + { "sensor_max", CPR3_RESULT2_SENSOR_MAX_MASK, + CPR3_RESULT2_SENSOR_MAX_SHIFT }, + }; + + if (thread->drv->desc->cpr_type < CTRL_TYPE_CPRH) + seq_printf(s, "current_volt = %d uV\n", thread->drv->last_uV); + + irq_status = cpr_read(thread, CPR3_REG_IRQ_STATUS); + seq_printf(s, "irq_status = %#02X\n", irq_status); + + ctl = cpr_read(thread, CPR3_REG_CPR_CTL); + seq_printf(s, "cpr_ctl = %#02X\n", ctl); + + seq_printf(s, "thread %d - hw tid: %u - enabled: %d:\n", + thread->id, thread->desc->hw_tid, thread->enabled); + seq_printf(s, "%d corners, derived from %d fuse corners\n", + thread->num_corners, thread->desc->num_fuse_corners); + + for (i = 0; i < thread->num_corners; i++, corner++) + seq_printf(s, "corner %d - uV=[%d %d %d] quot=%d freq=%lu\n", + i, corner->min_uV, corner->uV, corner->max_uV, + corner->quot_adjust, corner->freq); + + for (i = 0; i < thread->desc->num_fuse_corners; i++, fuse++) + seq_printf(s, "fuse %d - uV=[%d %d %d] quot=%d freq=%lu\n", + i, fuse->min_uV, fuse->uV, fuse->max_uV, + fuse->quot, corner->freq); + + seq_printf(s, "requested voltage: %d uV\n", thread->corner->last_uV); + + ro_sel = corner->fuse_corner->ring_osc_idx; + quot = cpr_read(thread, CPR3_REG_TARGET_QUOT(i, ro_sel)); + seq_printf(s, "quot_target (%u) = %#02X\n", ro_sel, quot); + + reg = cpr_read(thread, CPR3_REG_RESULT0(i)); + seq_printf(s, "cpr_result_0 = %#02X\n [", reg); + for (i = 0; i < ARRAY_SIZE(result0_fields); i++) + seq_printf(s, "%s%s = %u", + i ? ", " : "", + result0_fields[i].name, + (reg >> result0_fields[i].shift) & + result0_fields[i].mask); + seq_puts(s, "]\n"); + reg = cpr_read(thread, CPR3_REG_RESULT1(i)); + seq_printf(s, "cpr_result_1 = %#02X\n [", reg); + for (i = 0; i < ARRAY_SIZE(result1_fields); i++) + seq_printf(s, "%s%s = %u", + i ? ", " : "", + result1_fields[i].name, + (reg >> result1_fields[i].shift) & + result1_fields[i].mask); + seq_puts(s, "]\n"); + reg = cpr_read(thread, CPR3_REG_RESULT2(i)); + seq_printf(s, "cpr_result_2 = %#02X\n [", reg); + for (i = 0; i < ARRAY_SIZE(result2_fields); i++) + seq_printf(s, "%s%s = %u", + i ? ", " : "", + result2_fields[i].name, + (reg >> result2_fields[i].shift) & + result2_fields[i].mask); + seq_puts(s, "]\n"); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(cpr3_debug_info); + +static void cpr3_debugfs_init(struct cpr_drv *drv) +{ + int i; + + drv->debugfs = debugfs_create_dir("qcom_cpr3", NULL); + + for (i = 0; i < drv->desc->num_threads; i++) { + char buf[50]; + + snprintf(buf, sizeof(buf), "thread%d", i); + + debugfs_create_file(buf, 0444, drv->debugfs, &drv->threads[i], + &cpr3_debug_info_fops); + } +} + +/** + * cpr_thread_init() - Initialize CPR thread related parameters + * @drv: Main driver structure + * @tid: Thread ID + * + * Return: Zero for success, negative number on error + */ +static int cpr_thread_init(struct cpr_drv *drv, int tid) +{ + const struct cpr_desc *desc = drv->desc; + const struct cpr_thread_desc *tdesc = desc->threads[tid]; + struct cpr_thread *thread = &drv->threads[tid]; + int ret; + + if (tdesc->step_quot_init_min > CPR3_CPR_STEP_QUOT_MIN_MASK || + tdesc->step_quot_init_max > CPR3_CPR_STEP_QUOT_MAX_MASK) + return -EINVAL; + + thread->id = tid; + thread->drv = drv; + thread->desc = tdesc; + thread->fuse_corners = devm_kcalloc(drv->dev, + tdesc->num_fuse_corners + + drv->extra_corners, + sizeof(*thread->fuse_corners), + GFP_KERNEL); + if (!thread->fuse_corners) + return -ENOMEM; + + thread->cpr_fuses = cpr_get_fuses(drv->dev, tid, + tdesc->num_fuse_corners); + if (IS_ERR(thread->cpr_fuses)) + return PTR_ERR(thread->cpr_fuses); + + ret = cpr_populate_ring_osc_idx(thread->drv->dev, thread->fuse_corners, + thread->cpr_fuses, + tdesc->num_fuse_corners); + if (ret) + return ret; + + ret = cpr_fuse_corner_init(thread); + if (ret) + return ret; + + thread->pd.name = devm_kasprintf(drv->dev, GFP_KERNEL, + "%s_thread%d", + drv->dev->of_node->full_name, + thread->id); + if (!thread->pd.name) + return -EINVAL; + + thread->pd.power_off = cpr_power_off; + thread->pd.power_on = cpr_power_on; + thread->pd.opp_to_performance_state = cpr_get_performance_state; + thread->pd.attach_dev = cpr_pd_attach_dev; + thread->pd.detach_dev = cpr_pd_detach_dev; + + /* CPR-Hardened performance states are managed in firmware */ + if (desc->cpr_type == CTRL_TYPE_CPRH) { + thread->pd.set_performance_state = cprh_dummy_set_performance_state; + } else { + thread->pd.set_performance_state = cpr_set_performance_state; + } + + /* Anything later than CPR1 must be always-on for now */ + thread->pd.flags = GENPD_FLAG_ALWAYS_ON; + + drv->cell_data.domains[tid] = &thread->pd; + + ret = pm_genpd_init(&thread->pd, NULL, false); + if (ret) + return ret; + + /* On CPRhardened, the interrupts are managed in firmware */ + if (desc->cpr_type < CTRL_TYPE_CPRH) { + INIT_WORK(&thread->restart_work, cpr_restart_worker); + + ret = devm_request_threaded_irq(drv->dev, drv->irq, + NULL, cpr_irq_handler, + IRQF_ONESHOT | + IRQF_TRIGGER_RISING, + "cpr", drv); + if (ret) + return ret; + } + + return 0; +} + +/** + * cpr3_resources_init() - Initialize resources used by this driver + * @pdev: Platform device + * @drv: Main driver structure + * + * Return: Zero for success, negative number on error + */ +static int cpr3_resources_init(struct platform_device *pdev, + struct cpr_drv *drv) +{ + const struct cpr_desc *desc = drv->desc; + struct cpr_thread *threads = drv->threads; + unsigned int i; + u8 cid_mask = 0; + + /* + * Here, we are accounting for the following usecases: + * - One controller + * - One or multiple threads on the same iospace + * + * - Multiple controllers + * - Each controller has its own iospace and each + * may have one or multiple threads in their + * parent controller's iospace + * + * Then, to avoid complicating the code for no reason, + * this also needs a mandatory order in the list of + * threads which implies that all of them from the same + * controllers are specified sequentially. As an example: + * + * C0-T0, C0-T1...C0-Tn, C1-T0, C1-T1...C1-Tn + */ + for (i = 0; i < desc->num_threads; i++) { + u8 cid = desc->threads[i]->controller_id; + + if (cid_mask & BIT(cid)) { + if (desc->threads[i - 1]->controller_id != cid) { + dev_err(drv->dev, "Bad threads order. Please fix!\n"); + return -EINVAL; + } + threads[i].base = threads[i - 1].base; + continue; + } + threads[i].base = devm_platform_ioremap_resource(pdev, cid); + if (IS_ERR(threads[i].base)) + return PTR_ERR(threads[i].base); + cid_mask |= BIT(cid); + } + return 0; +} + +static int cpr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cpr_drv *drv; + const struct cpr_desc *desc; + const struct cpr_acc_desc *data; + struct device_node *np; + unsigned int i; + int ret; + + data = of_device_get_match_data(dev); + if (!data || !data->cpr_desc) + return -EINVAL; + + desc = data->cpr_desc; + + /* CPRh disallows MEM-ACC access from the HLOS */ + if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH) + return -EINVAL; + + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + drv->dev = dev; + drv->desc = desc; + drv->threads = devm_kcalloc(dev, desc->num_threads, + sizeof(*drv->threads), GFP_KERNEL); + if (!drv->threads) + return -ENOMEM; + + drv->cell_data.num_domains = desc->num_threads; + drv->cell_data.domains = devm_kcalloc(drv->dev, + drv->cell_data.num_domains, + sizeof(*drv->cell_data.domains), + GFP_KERNEL); + if (!drv->cell_data.domains) + return -ENOMEM; + + if (data->acc_desc) + drv->acc_desc = data->acc_desc; + + mutex_init(&drv->lock); + + if (desc->cpr_type < CTRL_TYPE_CPRH) { + np = of_parse_phandle(dev->of_node, "acc-syscon", 0); + if (!np) + return -ENODEV; + + drv->tcsr = syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(drv->tcsr)) + return PTR_ERR(drv->tcsr); + } + + ret = cpr3_resources_init(pdev, drv); + if (ret) + return ret; + + drv->irq = platform_get_irq_optional(pdev, 0); + if ((desc->cpr_type != CTRL_TYPE_CPRH) && (drv->irq < 0)) + return -EINVAL; + + /* On CPRhardened, vreg access it not allowed */ + drv->vreg = devm_regulator_get_optional(dev, "vdd"); + if (desc->cpr_type != CTRL_TYPE_CPRH && IS_ERR(drv->vreg)) + return PTR_ERR(drv->vreg); + + /* + * On at least CPRhardened, vreg is unaccessible and there is no + * way to read linear step from that regulator, hence it is hardcoded + * in the driver; + * When the vreg_step is not declared in the cpr data (or is zero), + * then having access to the vreg regulator is mandatory, as this + * will be retrieved through the regulator API. + */ + if (desc->vreg_step_fixed) + drv->vreg_step = desc->vreg_step_fixed; + else + drv->vreg_step = regulator_get_linear_step(drv->vreg); + + if (!drv->vreg_step) + return -EINVAL; + + /* + * Initialize fuse corners, since it simply depends + * on data in efuses. + * Everything related to (virtual) corners has to be + * initialized after attaching to the power domain, + * since it depends on the CPU's OPP table. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "cpr_fuse_revision", &drv->fusing_rev); + if (ret) + return ret; + + ret = nvmem_cell_read_variable_le_u32(dev, "cpr_speed_bin", &drv->speed_bin); + if (ret) + return ret; + + /* + * Some SoCs require extra corners for MEM-ACC or APM: if + * the related parameters have been specified, then reserve + * a corner for the APM and/or MEM-ACC crossover, used by + * OSM and CPRh HW to set the supply voltage during the APM + * and/or MEM-ACC switch routine. + */ + if (desc->cpr_type == CTRL_TYPE_CPRH) { + if (desc->apm_crossover && desc->apm_hysteresis >= 0) + drv->extra_corners++; + + if (desc->mem_acc_threshold) + drv->extra_corners++; + } + + /* Initialize all threads */ + for (i = 0; i < desc->num_threads; i++) { + ret = cpr_thread_init(drv, i); + if (ret) + return ret; + } + + /* Initialize global parameters */ + ret = cpr3_init_parameters(drv); + if (ret) + return ret; + + /* Write initial configuration on all threads */ + for (i = 0; i < desc->num_threads; i++) { + ret = cpr_configure(&drv->threads[i]); + if (ret) + return ret; + } + + ret = of_genpd_add_provider_onecell(dev->of_node, &drv->cell_data); + if (ret) + return ret; + + platform_set_drvdata(pdev, drv); + cpr3_debugfs_init(drv); + + return 0; +} + +static int cpr_remove(struct platform_device *pdev) +{ + struct cpr_drv *drv = platform_get_drvdata(pdev); + int i; + + of_genpd_del_provider(pdev->dev.of_node); + + for (i = 0; i < drv->desc->num_threads; i++) { + cpr_ctl_disable(&drv->threads[i]); + cpr_irq_set(&drv->threads[i], 0); + pm_genpd_remove(&drv->threads[i].pd); + } + + debugfs_remove_recursive(drv->debugfs); + + return 0; +} + +static const struct of_device_id cpr3_match_table[] = { + { .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc }, + { .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc }, + { } +}; +MODULE_DEVICE_TABLE(of, cpr3_match_table); + +static struct platform_driver cpr3_driver = { + .probe = cpr_probe, + .remove = cpr_remove, + .driver = { + .name = "qcom-cpr3", + .of_match_table = cpr3_match_table, + }, +}; +module_platform_driver(cpr3_driver) + +MODULE_DESCRIPTION("Core Power Reduction (CPR) v3/v4 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/qcom/cpr.h b/include/soc/qcom/cpr.h new file mode 100644 index 000000000000..2ba4324d18f6 --- /dev/null +++ b/include/soc/qcom/cpr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019 Linaro Limited + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +#ifndef __CPR_H__ +#define __CPR_H__ + +struct cpr_ext_data { + int mem_acc_threshold_uV; + int apm_threshold_uV; +}; + +#endif /* __CPR_H__ */ From 174914a5446ebab6f22081416913eb14a32d6a9c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 25 Nov 2020 20:40:26 +0100 Subject: [PATCH 067/174] MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver. Signed-off-by: AngeloGioacchino Del Regno --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 13dae1deb655..e90a6ef1445d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15970,6 +15970,12 @@ S: Maintained F: Documentation/devicetree/bindings/soc/qcom/qcom,cpr.yaml F: drivers/soc/qcom/cpr.c +QUALCOMM CORE POWER REDUCTION v3/v4/Hardened AVS DRIVER +M: AngeloGioacchino Del Regno +S: Maintained +F: Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml +F: drivers/soc/qcom/cpr3.c + QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 M: Ilia Lin L: linux-pm@vger.kernel.org From 5ef890581993ef9b07cb3cc8048eb932537c4b00 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 25 Nov 2020 20:31:49 +0100 Subject: [PATCH 068/174] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Add the bindings for the CPR3 driver to the documentation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring --- .../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++++++++++++++++++ 1 file changed, 241 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml new file mode 100644 index 000000000000..e2753740c86b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -0,0 +1,241 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) + +description: | + CPR (Core Power Reduction) is a technology to reduce core power on a CPU + or other device. Each OPP of a device corresponds to a "corner" that has + a range of valid voltages for a particular frequency. While the device is + running at a particular frequency, CPR monitors dynamic factors such as + temperature, etc. and suggests or, in the CPR-Hardened case performs, + adjustments to the voltage to save power and meet silicon characteristic + requirements. + +maintainers: + - AngeloGioacchino Del Regno + +properties: + compatible: + oneOf: + - description: CPRv3 controller + items: + - const: qcom,cpr3 + - description: CPRv4 controller + items: + - const: qcom,cpr4 + - description: CPRv4-Hardened controller + items: + - enum: + - qcom,msm8998-cprh + - qcom,sdm630-cprh + - const: qcom,cprh + + reg: + description: Base address and size of the CPR controller(s) + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: "ref" + + clocks: + items: + - description: CPR reference clock + + vdd-supply: + description: Autonomous Phase Control (APC) or other power supply + + '#power-domain-cells': + const: 1 + + acc-syscon: + description: phandle to syscon for writing ACC settings + + nvmem-cells: + description: Cells containing the fuse corners and revision data + minItems: 10 + maxItems: 32 + + nvmem-cell-names: + minItems: 10 + maxItems: 32 + + operating-points-v2: true + +required: + - compatible + - reg + - clock-names + - clocks + - "#power-domain-cells" + - nvmem-cells + - nvmem-cell-names + - operating-points-v2 + +additionalProperties: false + +examples: + - | + #include + #include + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + }; + + cpu@100 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + }; + }; + + cpu_silver_opp_table: cpu-silver-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + required-opps = <&cprh_opp3>; + }; + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cprh_opp2>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cpu_gold_opp_table: cpu-gold-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cprh_opp3>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + required-opps = <&cprh_opp2>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cprh_opp_table: cpr-hardened-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp1: opp1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + }; + cprh_opp2: opp2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + }; + cprh_opp3: opp3 { + opp-level = <3>; + qcom,opp-fuse-level = <2 3>; + }; + }; + + apc_cprh: power-controller@179c8000 { + compatible = "qcom,msm8998-cprh", "qcom,cprh"; + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "ref"; + + #power-domain-cells = <1>; + operating-points-v2 = <&cprh_opp_table>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>, + <&cpr_quot0_perfcl>, + <&cpr_quot1_perfcl>, + <&cpr_quot2_perfcl>, + <&cpr_quot3_perfcl>, + <&cpr_quot_offset1_perfcl>, + <&cpr_quot_offset2_perfcl>, + <&cpr_quot_offset3_perfcl>, + <&cpr_init_voltage0_perfcl>, + <&cpr_init_voltage1_perfcl>, + <&cpr_init_voltage2_perfcl>, + <&cpr_init_voltage3_perfcl>, + <&cpr_ro_sel0_perfcl>, + <&cpr_ro_sel1_perfcl>, + <&cpr_ro_sel2_perfcl>, + <&cpr_ro_sel3_perfcl>; + + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4", + "cpr1_quotient1", + "cpr1_quotient2", + "cpr1_quotient3", + "cpr1_quotient4", + "cpr1_quotient_offset2", + "cpr1_quotient_offset3", + "cpr1_quotient_offset4", + "cpr1_init_voltage1", + "cpr1_init_voltage2", + "cpr1_init_voltage3", + "cpr1_init_voltage4", + "cpr1_ring_osc1", + "cpr1_ring_osc2", + "cpr1_ring_osc3", + "cpr1_ring_osc4"; + }; +... From ebdfc5be8728e2776b96c58b166263a6bdd1d58a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 5 Dec 2020 17:53:51 +0100 Subject: [PATCH 069/174] arm64: dts: qcom: Enable panel etc. on MSM8998 Sony Yoshino platform (JAMI: fixup for 5.16) --- .../msm8998-sony-xperia-yoshino-maple.dts | 57 ++++++ .../msm8998-sony-xperia-yoshino-poplar.dts | 12 ++ .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 193 +++++++++++++++++- 3 files changed, 261 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 978495a8a6b9..9e6b06c9c157 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -26,6 +26,28 @@ }; }; +&dsi0 { + qcom,dual-dsi-mode; + qcom,master-dsi; +}; + +&dsi1 { + vdd-supply = <&vreg_l1a_0p875>; + vdda-supply = <&vreg_l2a_1p2>; + qcom,dual-dsi-mode; + status = "ok"; +}; + +&dsi1_out { + remote-endpoint = <&panel_in1>; + data-lanes = <0 1 2 3>; +}; + +&dsi1_phy { + vdds-supply = <&vreg_l1a_0p875>; + status = "ok"; +}; + &ibb { regulator-min-microvolt = <5600000>; regulator-max-microvolt = <5600000>; @@ -37,6 +59,32 @@ qcom,soft-start-us = <200>; }; +&panel { + compatible = "sharp,ls055d1sx04"; + + dvdd-supply = <&disp_dvdd_vreg>; + ports { + port@1 { + reg = <1>; + panel_in1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; +}; + +&pm8005_gpio { + ear_en_default: ear-en-active { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = <1>; + }; +}; + &pmi8998_gpio { disp_dvdd_en: disp-dvdd-en-active { pins = "gpio10"; @@ -53,3 +101,12 @@ regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + + +&pmi8998_wled { + status = "okay"; + + qcom,num-strings = <3>; + qcom,enabled-strings = <0 1 2>; +}; + diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts index 4a1f98a21031..84911139a7d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -25,6 +25,18 @@ qcom,soft-start-us = <800>; }; +&pm8005_gpio { + ear_en_default: ear-en-active { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = <1>; + }; +}; + &vreg_l18a_2p85 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 47488a1aecae..a149a642ea48 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -20,6 +20,10 @@ qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ qcom,board-id = <8 0>; + chosen { + bootargs = "clk_ignore_unused root=/dev/mmcblk0p1"; + }; + clocks { compatible = "simple-bus"; @@ -84,6 +88,15 @@ pinctrl-0 = <&ts_vddio_en>; }; + /* The gpio-vibrator driver enforces requiring a regulator */ + vib_vreg: vib-regulator { + compatible = "regulator-fixed"; + regulator-name = "vib"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -184,11 +197,28 @@ vibrator { compatible = "gpio-vibrator"; enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + vcc-supply = <&vib_vreg>; pinctrl-names = "default"; pinctrl-0 = <&vib_default>; }; }; +&adreno_gpu { + status = "ok"; + + zap-shader { + memory-region = <&zap_shader_region>; + }; +}; + +&adreno_smmu { + status = "ok"; +}; + +&apc_cprh { + status = "ok"; +}; + &blsp1_i2c5 { status = "okay"; clock-frequency = <355000>; @@ -241,10 +271,79 @@ }; }; +&blsp2_i2c1 { + tof-sensor@29 { + compatible = "st,vl53l0x"; + reg = <0x29>; + interrupt-parent = <&tlmm>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + #io-channel-cells = <1>; + label = "back_camera_tof"; + pinctrl-names = "default"; + pinctrl-0 = <&tof_int_n &tof_rst_n>; + }; +}; + &blsp2_uart1 { status = "okay"; }; +&cpufreq_hw { + status = "ok"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-supply = <&vreg_l2a_1p2>; + + panel: panel@0 { + reg = <0>; + + backlight = <&pmi8998_wled>; + disp-te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&lab>; + avee-supply = <&ibb>; + vddio-supply = <&vreg_l14a_1p85>; + tavdd-supply = <&vreg_l28_3p0>; + tvddio-supply = <&touch_vddio_vreg>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_n &mdp_vsync_n>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in0>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + +&gpucc { + status = "ok"; +}; + &ibb { regulator-min-microamp = <800000>; regulator-max-microamp = <800000>; @@ -278,6 +377,18 @@ status = "ok"; }; +&mdss { + status = "okay"; +}; + +&mmcc { + status = "ok"; +}; + +&mmss_smmu { + status = "ok"; +}; + &pm8005_lsid1 { pm8005-regulators { compatible = "qcom,pm8005-regulators"; @@ -286,7 +397,12 @@ /* VDD_GFX supply */ pm8005_s1: s1 { - regulator-min-microvolt = <524000>; + /* + * HACK: Set enough voltage for max GPU frequency + * and set the regulator always on until the + * GPU Core Power Reduction gets available + */ + regulator-min-microvolt = <988000>; regulator-max-microvolt = <1088000>; regulator-enable-ramp-delay = <500>; regulator-always-on; @@ -324,6 +440,13 @@ function = "func2"; power-source = <0>; }; + + nfc_clk_req_pin: nfc-clk-req-active { + pins = "gpio21"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + power-source = <1>; + }; }; &pmi8998_gpio { @@ -358,6 +481,18 @@ }; }; +&pmi8998_wled { + status = "okay"; + + default-brightness = <3000>; + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <25000>; + qcom,num-strings = <2>; + qcom,enabled-strings = <0 1>; +}; + &qusb2phy { status = "okay"; @@ -365,6 +500,18 @@ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; }; +&remoteproc_adsp { + firmware-name = "adsp.mdt"; +}; + +&remoteproc_mss { + status = "disabled"; +}; + +&remoteproc_slpi { + firmware-name = "slpi.mdt"; +}; + &rpm_requests { pm8998-regulators { compatible = "qcom,rpm-pm8998-regulators"; @@ -606,6 +753,14 @@ drive-strength = <2>; }; + tof_int_n: tof-int-n { + pins = "gpio22"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + input-enable; + }; + cam1_vdig_default: cam1-vdig-default { pins = "gpio25"; function = "gpio"; @@ -613,6 +768,42 @@ drive-strength = <2>; }; + tof_rst_n: tof-rst-n { + pins = "gpio27"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + + cam1_rst_default: cam1-rst-n { + pins = "gpio28"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cam0_rst_default: cam0-rst-n { + pins = "gpio30"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ts_reset_n: ts-reset-n { + pins = "gpio89"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; + + panel_reset_n: panel-rst-n { + pins = "gpio94"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + hall_sensor0_default: acc-cover-open { pins = "gpio124"; function = "gpio"; From df70e2d821f650a767b12e0ad1c1643777bc101d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 5 Dec 2020 12:45:50 +0100 Subject: [PATCH 070/174] arm64: dts: msm8998: Add disabled configuration for DPU1/DSI This SoC supports both the MDP5 and DPU1 drivers, but the latter was chosen as it's more feature-complete; Configure the DPU1, DSI and related phy and pll in order to achieve display functionality and keep it disabled. Enabling it will be done on board specific DT when needed, as not all boards have a usable display attached to them. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 264 +++++++++++++++++++++++++- 1 file changed, 260 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f273bc1ff629..085061c570c6 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2459,16 +2459,272 @@ "core_bi_pll_test_se"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, - <0>, - <0>, - <0>, - <0>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, <0>, <0>, <0>, <0>; }; + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + + mdss: mdss@c900000 { + compatible = "qcom,sdm845-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&mmcc MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + interrupts = ; + interrupt-controller; + iommus = <&mmss_smmu 0>; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + ranges; + status = "disabled"; + + mdss_mdp: mdp@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", "regdma", "vbif", + "vbif_nrt"; + + assigned-clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <412500000>, + <19200000>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "mnoc", + "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-330000000 { + opp-hz = /bits/ 64 <330000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-412500000 { + opp-hz = /bits/ 64 <412500000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + dsi0: dsi@c994000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + clock-names = "byte", + "byte_intf", + "mnoc", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&dsi_opp_table>; + phys = <&dsi0_phy>; + phy-names = "dsi"; + power-domains = <&rpmpd MSM8998_VDDCX>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@c994400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1c0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + power-domains = <&rpmpd MSM8998_VDDMX>; + + status = "disabled"; + }; + + dsi1: dsi@c996000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "mnoc", + "iface_mmss", + "pixel", + "core", + "iface", + "bus"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&dsi_opp_table>; + phys = <&dsi1_phy>; + phy-names = "dsi"; + power-domains = <&rpmpd MSM8998_VDDCX>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@c996400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + power-domains = <&rpmpd MSM8998_VDDMX>; + + status = "disabled"; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; From bd9e161cf012553ad27321fc89a64d72d55f94c3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 4 Jan 2021 18:17:58 +0100 Subject: [PATCH 071/174] arm64: dts: msm8998: Add interconnect nodes This SoC features Network-on-Chip (NoC) and Bus Integrated Memory Controller (BIMC) interconnects: add the required nodes now that the driver is present. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 68 +++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 085061c570c6..fafe63ccdeda 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -882,6 +883,15 @@ }; }; + bimc: interconnect@1008000 { + compatible = "qcom,msm8998-bimc"; + reg = <0x01008000 0x78000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + tsens0: thermal@10ab000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x010ab000 0x1000>, /* TM */ @@ -904,6 +914,33 @@ #thermal-sensor-cells = <1>; }; + cnoc: interconnect@1500000 { + compatible = "qcom,msm8998-cnoc"; + reg = <0x01500000 0x10000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@1625000 { + compatible = "qcom,msm8998-snoc"; + reg = <0x01625000 0x6100>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a1noc: interconnect@1669000 { + compatible = "qcom,msm8998-a1noc"; + reg = <0x01669000 0x5020>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + anoc1_smmu: iommu@1680000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x01680000 0x10000>; @@ -938,6 +975,25 @@ ; }; + a2noc: interconnect@1705000 { + compatible = "qcom,msm8998-a2noc"; + reg = <0x01705000 0xa090>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mnoc: interconnect@1744000 { + compatible = "qcom,msm8998-mnoc"; + reg = <0x01744000 0xb010>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>, + <&mmcc AHB_CLK_SRC>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-msm8996"; reg = <0x01c00000 0x2000>, @@ -2795,6 +2851,18 @@ }; }; + gnoc: interconnect@17900000 { + compatible = "qcom,msm8998-gnoc"; + reg = <0x17900000 0xe000>; + #interconnect-cells = <1>; + /* + * This one apparently features no clocks, + * so let's not mess with the driver needlessly + */ + clock-names = "bus", "bus_a"; + clocks = <&xo>, <&xo>; + }; + apcs_glb: mailbox@17911000 { compatible = "qcom,msm8998-apcs-hmss-global"; reg = <0x17911000 0x1000>; From 6fc76bf25207984fb77ebade332684cbe7c62a38 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 20 Jan 2021 15:27:42 +0100 Subject: [PATCH 072/174] arm64: dts: msm8998: Wire up interconnects and OPPs to sdhci port 2 Wire up the OPP table and interconnects to the SDHCI port 2 to improve performance and power consumption. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index fafe63ccdeda..9af8c7b44690 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2193,6 +2193,7 @@ reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; reg-names = "hc_mem", "core_mem"; + interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -2203,6 +2204,26 @@ <&xo>; bus-width = <4>; status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-peak-kBps = <400000>; + opp-avg-kBps = <200000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <800000>; + opp-avg-kBps = <400000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-peak-kBps = <800000>; + opp-avg-kBps = <800000>; + }; + }; }; blsp1_dma: dma-controller@c144000 { From 4c86b1ef95403012711ad17d1767a3a0449cd19b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 14 Dec 2020 17:19:11 +0100 Subject: [PATCH 073/174] arm64: dts: qcom: pm8998: Add VREF_1P25 and REF_GND VADC channels Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index d09f2954b6f9..ed68f44a7f11 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -78,6 +78,16 @@ #size-cells = <0>; #io-channel-cells = <1>; + adc-chan@0 { + reg = ; + label = "ref_gnd"; + }; + + adc-chan@1 { + reg = ; + label = "vref_1p25"; + }; + adc-chan@6 { reg = ; label = "die_temp"; From e372ac89aa993f221f96a4f9c6ef5d6aef4a7e46 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 4 Dec 2020 23:04:52 +0100 Subject: [PATCH 074/174] arm64: dts: qcom: Enable panel etc. on MSM8998 F(x)tec Pro1 QX1000 (JAMI: fixup for 5.16) --- .../boot/dts/qcom/msm8998-fxtec-pro1.dts | 283 ++++++++++++++++++ 1 file changed, 283 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index dc5b9b274df3..737bcabf1a21 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -18,6 +18,15 @@ chassis-type = "handset"; qcom,board-id = <0x02000b 0x10>; + /* This part enables graphical output via bootloader-enabled display */ + chosen { + bootargs = "earlycon=tty0 console=tty0 clk_ignore_unused"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + /* * Until we hook up type-c detection, we * have to stick with this. But it works. @@ -46,6 +55,8 @@ gpio-kb-extra-keys { compatible = "gpio-keys"; label = "Keyboard extra keys"; + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&gpio_kb_pins_extra>; @@ -98,6 +109,39 @@ }; }; + gpio_keyboard: gpio-keyboard { + compatible = "gpio-fastmatrix-keyboard"; + label = "F(x)Tec Pro1 Hardware Keyboard"; + row-gpios = + <&gpioext0 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 4 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 6 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + col-gpios = + <&gpioext0 8 GPIO_ACTIVE_LOW>, + <&gpioext0 9 GPIO_ACTIVE_LOW>, + <&gpioext0 10 GPIO_ACTIVE_LOW>, + <&gpioext0 11 GPIO_ACTIVE_LOW>, + <&gpioext0 12 GPIO_ACTIVE_LOW>, + <&gpioext0 13 GPIO_ACTIVE_LOW>, + <&gpioext0 14 GPIO_ACTIVE_LOW>, + <&gpioext0 15 GPIO_ACTIVE_LOW>; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins_col>, <&keyboard_pins_row>; + + autorescan-ms = <5>; + debounce-delay-ms = <1>; + col-scan-delay-us = <1500>; + }; + gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; @@ -177,6 +221,53 @@ }; }; + disp_vcc_vreg: disp-vcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "disp_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + disp_vddio_vreg: disp-vddio-regulator { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-allow-set-load; + }; + + disp_vci_vreg: disp-vci-regulator { + compatible = "regulator-fixed"; + regulator-name = "disp_vci"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + regulator-allow-set-load; + }; + + disp_elvdd_vreg: disp-elvdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "disp_elvdd"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <4600000>; + regulator-boot-on; + regulator-always-on; + }; + + disp_elvss_vreg: disp-elvss-regulator { + compatible = "regulator-fixed"; + regulator-name = "disp_elvss"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2400000>; + regulator-boot-on; + regulator-always-on; + }; + ts_vio_vreg: ts-vio-vreg { compatible = "regulator-fixed"; regulator-name = "ts_vio_reg"; @@ -189,8 +280,61 @@ }; }; +&adreno_gpu { + status = "ok"; + + zap-shader { + memory-region = <&zap_shader_region>; + }; +}; + +&adreno_smmu { + status = "ok"; +}; + +&apc_cprh { + status = "ok"; +}; + +&blsp1_i2c6 { + status = "ok"; + + gpioext0: gpio-expander@58 { + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpioext0 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-0 = <&gpio_expander_int_n>, <&gpio_expander_rst_n>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + keyboard_pins_col: keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + output-low; + }; + keyboard_pins_row: keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-open-drain; + input-enable; + }; + }; +}; + &blsp2_i2c1 { status = "ok"; + qcom,noise-reject-scl = <3>; + qcom,noise-reject-sda = <3>; touchscreen@14 { compatible = "goodix,gt9286"; @@ -205,6 +349,104 @@ }; }; +&cpufreq_hw { + status = "ok"; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-supply = <&vreg_l2a_1p2>; + + panel: panel@0 { + compatible = "boe,bf060y8m-aj0"; + reg = <0>; + + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + disp-te-gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + no-hpd; + + vcc-supply = <&disp_vcc_vreg>; + vddio-supply = <&disp_vddio_vreg>; + vci-supply = <&disp_vci_vreg>; + elvdd-supply = <&disp_elvdd_vreg>; + elvss-supply = <&disp_elvss_vreg>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_n &disp_en_default &mdp_vsync_n>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_phy { + status = "ok"; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&gcc { + status = "ok"; +}; + +&gpucc { + status = "ok"; +}; + +&gpio_keyboard { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_F1) MATRIX_KEY(1, 0, KEY_H) + MATRIX_KEY(2, 0, KEY_B) MATRIX_KEY(3, 0, KEY_7) + MATRIX_KEY(4, 0, KEY_UP) MATRIX_KEY(5, 0, KEY_ENTER) + MATRIX_KEY(6, 0, KEY_Y) MATRIX_KEY(7, 0, KEY_COMMA) + MATRIX_KEY(0, 1, KEY_3) MATRIX_KEY(1, 1, KEY_S) + MATRIX_KEY(2, 1, KEY_Z) MATRIX_KEY(3, 1, KEY_M) + MATRIX_KEY(4, 1, KEY_I) MATRIX_KEY(5, 1, KEY_9) + MATRIX_KEY(6, 1, KEY_W) MATRIX_KEY(7, 1, KEY_J) + MATRIX_KEY(0, 2, KEY_LEFT) MATRIX_KEY(1, 2, KEY_G) + MATRIX_KEY(2, 2, KEY_V) MATRIX_KEY(3, 2, KEY_6) + MATRIX_KEY(4, 2, KEY_RIGHT) MATRIX_KEY(5, 2, KEY_DELETE) + MATRIX_KEY(6, 2, KEY_T) MATRIX_KEY(7, 2, KEY_DOT) + MATRIX_KEY(0, 3, KEY_SLASH) MATRIX_KEY(1, 3, KEY_A) + MATRIX_KEY(2, 3, KEY_RIGHTBRACE) MATRIX_KEY(3, 3, KEY_HOMEPAGE) + MATRIX_KEY(4, 3, KEY_P) MATRIX_KEY(5, 3, KEY_MINUS) + MATRIX_KEY(6, 3, KEY_Q) MATRIX_KEY(7, 3, KEY_L) + MATRIX_KEY(0, 4, KEY_BACKSPACE) MATRIX_KEY(1, 4, KEY_D) + MATRIX_KEY(2, 4, KEY_X) MATRIX_KEY(3, 4, KEY_K) + MATRIX_KEY(4, 4, KEY_SEMICOLON) MATRIX_KEY(5, 4, KEY_EQUAL) + MATRIX_KEY(6, 4, KEY_E) MATRIX_KEY(7, 4, KEY_APOSTROPHE) + MATRIX_KEY(0, 5, KEY_CAPSLOCK) MATRIX_KEY(1, 5, KEY_BACKSLASH) + MATRIX_KEY(2, 5, KEY_LEFTBRACE) MATRIX_KEY(3, 5, KEY_DOWN) + MATRIX_KEY(4, 5, KEY_O) MATRIX_KEY(5, 5, KEY_0) + MATRIX_KEY(6, 5, KEY_GRAVE) MATRIX_KEY(7, 5, KEY_K) + MATRIX_KEY(0, 6, KEY_SPACE) MATRIX_KEY(1, 6, KEY_F) + MATRIX_KEY(2, 6, KEY_C) MATRIX_KEY(3, 6, KEY_N) + MATRIX_KEY(4, 6, KEY_U) MATRIX_KEY(5, 6, KEY_8) + MATRIX_KEY(6, 6, KEY_R) MATRIX_KEY(7, 6, KEY_5) + MATRIX_KEY(0, 7, KEY_ESC) MATRIX_KEY(1, 7, KEY_1) + MATRIX_KEY(2, 7, KEY_RESERVED) MATRIX_KEY(3, 7, KEY_RESERVED) + MATRIX_KEY(4, 7, KEY_2) MATRIX_KEY(5, 7, KEY_4) + MATRIX_KEY(6, 7, KEY_TAB) MATRIX_KEY(7, 7, KEY_RESERVED) + >; +}; + +&mdss { + status = "ok"; +}; + +&mdss_mdp { + status = "ok"; +}; + &mmcc { status = "ok"; }; @@ -213,7 +455,21 @@ status = "ok"; }; +/* HACK! Push GPU voltage high until GPU CPR is hooked up */ +&pm8005_s1 { + regulator-min-microvolt = <988000>; + regulator-max-microvolt = <1100000>; +}; + &pm8998_gpio { + unknown_pin_a: unk-active { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; @@ -267,6 +523,26 @@ bias-pull-up; }; + gpio_expander_int_n: gpio-exp-intn-def { + pins = "gpio50"; + function = "gpio"; + drive-strength = <2>; + input-enable; + }; + + gpio_expander_rst_n: gpio-exp-rst-def { + pins = "gpio51"; + function = "gpio"; + drive-strength = <8>; + }; + + disp_en_default: disp-en { + pins = "gpio62"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + ts_vio_default: ts-vio-def { pins = "gpio81"; function = "gpio"; @@ -295,6 +571,13 @@ bias-disable; drive-strength = <8>; }; + + panel_reset_n: panel-rst-n { + pins = "gpio94"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; &ufshc { From 3e04d1024d187c34244b5e34467d1a72abdf3c06 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 21 Jan 2021 20:05:15 +0100 Subject: [PATCH 075/174] arm64: dts: msm8998: Wire up interconnects to MDP and GPU Wire up the interconnects to both the MDP and the Adreno GPU in order to get the right balance between performance and power consumption of both devices. --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 9af8c7b44690..2abcf8e16725 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1498,6 +1498,8 @@ "rbcpr", "core"; + interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; + interconnect-names = "gfx-mem"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; @@ -1509,42 +1511,55 @@ opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = ; + opp-peak-kBps = <14432000>; + opp-avg-kBps = <14400000>; opp-supported-hw = <0xFF>; }; opp-670000048 { opp-hz = /bits/ 64 <670000048>; opp-level = ; + opp-peak-kBps = <14432000>; + opp-avg-kBps = <14390000>; opp-supported-hw = <0xFF>; }; - opp-596000097 { opp-hz = /bits/ 64 <596000097>; opp-level = ; + opp-peak-kBps = <14432000>; + opp-avg-kBps = <12440000>; opp-supported-hw = <0xFF>; }; opp-515000097 { opp-hz = /bits/ 64 <515000097>; opp-level = ; + opp-peak-kBps = <14432000>; + opp-avg-kBps = <10368000>; opp-supported-hw = <0xFF>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = ; + opp-peak-kBps = <12440000>; + opp-avg-kBps = <8136000>; opp-supported-hw = <0xFF>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = ; + opp-peak-kBps = <8136000>; + opp-avg-kBps = <6144000>; opp-supported-hw = <0xFF>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-peak-kBps = <6144000>; + opp-avg-kBps = <3296000>; opp-supported-hw = <0xFF>; }; }; @@ -2577,6 +2592,10 @@ assigned-clocks = <&mmcc MDSS_MDP_CLK>; assigned-clock-rates = <300000000>; + interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>, + <&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>; + interconnect-names = "mdp0-mem", + "mdp1-mem"; interrupts = ; interrupt-controller; iommus = <&mmss_smmu 0>; From ddb7db6e7e66ee5f3f88084d3d84803c55ce1fc7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Dec 2020 12:10:53 +0100 Subject: [PATCH 076/174] arm64: dts: msm8998: Add SAW, CPRh and CPUFREQ to enable CPU scaling Add the SAW (SPM), CPR-Hardened, CPUFREQ-HW nodes and relative OPP tables (and also assign them to the CPU nodes, as required) in order to enable CPU scaling on the MSM8998 SoC. The CPR-Hardened and CPUFREQ-HW nodes are disabled by default as to not change the previous default behavior. Since the drivers are not yet accounting for speed-binning, these OPPs are referred to the most common binning for this chip, which I have found on six phones from Sony and one from FxTec (silver bin0, perf bin2). At least until speed-binning gets done in the cpufreq-hw and CPR drivers, users should enable CPR-Hardened and CPUFREQ in their own board DT. This is done like that because these drivers are really big, so the idea is to keep the "base" version easier (but perfectly working), before adding speed-binning "complications", which may... or may not be necessary. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 721 +++++++++++++++++++++++++- 1 file changed, 720 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 2abcf8e16725..471372e573e8 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -10,6 +10,15 @@ #include #include +/* Macro for CPR-Hardened OPP entries - Example phandle: cprh_opp0 */ +#define CPRH_OPP_ENTRY(lvl, _fuselevel, _oadj, _cadj) \ + cprh_opp##lvl##: opp-##lvl { \ + opp-level = ; \ + qcom,opp-fuse-level = <_fuselevel>; \ + qcom,opp-oloop-vadj = <_oadj>; \ + qcom,opp-cloop-vadj = <_cadj>; \ + } + / { interrupt-parent = <&intc>; @@ -136,8 +145,13 @@ reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + clocks = <&xo>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -156,8 +170,13 @@ reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + clocks = <&xo>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; }; @@ -172,8 +191,13 @@ reg = <0x0 0x2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + clocks = <&xo>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; }; @@ -188,8 +212,13 @@ reg = <0x0 0x3>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + clocks = <&xo>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; }; @@ -204,8 +233,13 @@ reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1536>; + clocks = <&xo>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 1>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -224,8 +258,13 @@ reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1536>; + clocks = <&xo>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; }; @@ -240,8 +279,13 @@ reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1536>; + clocks = <&xo>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; }; @@ -256,8 +300,13 @@ reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1536>; + clocks = <&xo>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + qcom,freq-domain = <&cpufreq_hw 1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; }; @@ -351,6 +400,378 @@ }; }; + cpu_gold_opp_table: cpu-gold-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + required-opps = <&cprh_opp30>; + qcom,pll-override = <0x0a620062>; + qcom,spare-data = <3>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + required-opps = <&cprh_opp29>; + qcom,pll-override = <0x0a620062>; + qcom,spare-data = <3>; + }; + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + required-opps = <&cprh_opp28>; + qcom,pll-override = <0x0a610061>; + qcom,spare-data = <3>; + }; + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + required-opps = <&cprh_opp27>; + qcom,pll-override = <0x0a5e005e>; + qcom,spare-data = <3>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cprh_opp26>; + qcom,pll-override = <0x0a5c005c>; + qcom,spare-data = <3>; + }; + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + required-opps = <&cprh_opp25>; + qcom,pll-override = <0x0a580058>; + qcom,spare-data = <3>; + }; + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + required-opps = <&cprh_opp24>; + qcom,pll-override = <0x09550055>; + qcom,spare-data = <3>; + }; + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + required-opps = <&cprh_opp23>; + qcom,pll-override = <0x09520052>; + qcom,spare-data = <2>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + required-opps = <&cprh_opp22>; + qcom,pll-override = <0x094e004e>; + qcom,spare-data = <2>; + }; + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + required-opps = <&cprh_opp21>; + qcom,pll-override = <0x084b004b>; + qcom,spare-data = <2>; + }; + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + required-opps = <&cprh_opp20>; + qcom,pll-override = <0x08480048>; + qcom,spare-data = <2>; + }; + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + required-opps = <&cprh_opp19>; + qcom,pll-override = <0x07450045>; + qcom,spare-data = <2>; + }; + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + required-opps = <&cprh_opp18>; + qcom,pll-override = <0x07420042>; + qcom,spare-data = <2>; + }; + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&cprh_opp17>; + qcom,pll-override = <0x073e003e>; + qcom,spare-data = <2>; + }; + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + required-opps = <&cprh_opp16>; + qcom,pll-override = <0x063b003b>; + qcom,spare-data = <2>; + }; + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + required-opps = <&cprh_opp15>; + qcom,pll-override = <0x06380038>; + qcom,spare-data = <2>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + required-opps = <&cprh_opp14>; + qcom,pll-override = <0x06350035>; + qcom,spare-data = <2>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + required-opps = <&cprh_opp13>; + qcom,pll-override = <0x05320032>; + qcom,spare-data = <2>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + required-opps = <&cprh_opp12>; + qcom,pll-override = <0x052f002f>; + qcom,spare-data = <1>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + required-opps = <&cprh_opp11>; + qcom,pll-override = <0x052c002c>; + qcom,spare-data = <1>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + required-opps = <&cprh_opp10>; + qcom,pll-override = <0x4290029>; + qcom,spare-data = <1>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + required-opps = <&cprh_opp9>; + qcom,pll-override = <0x4260026>; + qcom,spare-data = <1>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + required-opps = <&cprh_opp8>; + qcom,pll-override = <0x3200022>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + required-opps = <&cprh_opp7>; + qcom,pll-override = <0x3200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + required-opps = <&cprh_opp6>; + qcom,pll-override = <0x3200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&cprh_opp5>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + required-opps = <&cprh_opp4>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + required-opps = <&cprh_opp3>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&cprh_opp2>; + qcom,pll-override = <0x1200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + qcom,pll-override = <0x1200020>; + qcom,spare-data = <1>; + }; + }; + + cpu_silver_opp_table: cpu-silver-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + required-opps = <&cprh_opp22>; + qcom,pll-override = <0x094f004f>; + qcom,spare-data = <3>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + required-opps = <&cprh_opp21>; + qcom,pll-override = <0x084c004c>; + qcom,spare-data = <3>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + required-opps = <&cprh_opp20>; + qcom,pll-override = <0x08490049>; + qcom,spare-data = <2>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + required-opps = <&cprh_opp19>; + qcom,pll-override = <0x08460046>; + qcom,spare-data = <2>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + required-opps = <&cprh_opp18>; + qcom,pll-override = <0x07410041>; + qcom,spare-data = <2>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + required-opps = <&cprh_opp17>; + qcom,pll-override = <0x073e003e>; + qcom,spare-data = <2>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cprh_opp16>; + qcom,pll-override = <0x063a003a>; + qcom,spare-data = <2>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + required-opps = <&cprh_opp15>; + qcom,pll-override = <0x06370037>; + qcom,spare-data = <2>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cprh_opp14>; + qcom,pll-override = <0x05340034>; + qcom,spare-data = <2>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + required-opps = <&cprh_opp13>; + qcom,pll-override = <0x05310031>; + qcom,spare-data = <2>; + }; + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cprh_opp12>; + qcom,pll-override = <0x052e002e>; + qcom,spare-data = <2>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + required-opps = <&cprh_opp11>; + qcom,pll-override = <0x042b002b>; + qcom,spare-data = <1>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + required-opps = <&cprh_opp10>; + qcom,pll-override = <0x4280028>; + qcom,spare-data = <1>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + required-opps = <&cprh_opp9>; + qcom,pll-override = <0x4250025>; + qcom,spare-data = <1>; + }; + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + required-opps = <&cprh_opp8>; + qcom,pll-override = <0x3200022>; + qcom,spare-data = <1>; + }; + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + required-opps = <&cprh_opp7>; + qcom,pll-override = <0x3200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&cprh_opp6>; + qcom,pll-override = <0x3200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + required-opps = <&cprh_opp5>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-518400000 { + opp-hz = /bits/ 64 <518400000>; + required-opps = <&cprh_opp4>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + required-opps = <&cprh_opp3>; + qcom,pll-override = <0x2200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-364800000 { + opp-hz = /bits/ 64 <364800000>; + required-opps = <&cprh_opp2>; + qcom,pll-override = <0x1200020>; + qcom,pll-div = <1>; + qcom,spare-data = <1>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + qcom,pll-override = <0x1200020>; + }; + }; + + cprh_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + CPRH_OPP_ENTRY(1, 1, 0, 0); + CPRH_OPP_ENTRY(2, 1, 0, 0); + CPRH_OPP_ENTRY(3, 1, 0, 0); + CPRH_OPP_ENTRY(4, 1, 0, 0); + CPRH_OPP_ENTRY(5, 1, 0, 0); + CPRH_OPP_ENTRY(6, 1, 0, 0); + CPRH_OPP_ENTRY(7, 1, 0, 0); + CPRH_OPP_ENTRY(8, 1, 0, 0); + CPRH_OPP_ENTRY(9, 2, 0, 0); + CPRH_OPP_ENTRY(10, 2, 0, 0); + CPRH_OPP_ENTRY(11, 2, 0, 0); + CPRH_OPP_ENTRY(12, 3 2, (-12000) (-8000), (-10000) (-10000)); + CPRH_OPP_ENTRY(13, 3, (-16000) (-16000), (-11000) (-10000)); + CPRH_OPP_ENTRY(14, 3, (-16000) (-12000), (-12000) (-11000)); + CPRH_OPP_ENTRY(15, 3, (-12000) (-16000), (-13000) (-12000)); + CPRH_OPP_ENTRY(16, 3, (-12000) (-16000), (-14000) (-12000)); + CPRH_OPP_ENTRY(17, 3, (-16000) (-12000), (-14000) (-13000)); + CPRH_OPP_ENTRY(18, 3, (-16000) (-16000), (-15000) (-14000)); + CPRH_OPP_ENTRY(19, 4 3, (-20000) (-16000), (-21000) (-14000)); + CPRH_OPP_ENTRY(20, 4 3, (-24000) (-16000), (-24000) (-15000)); + CPRH_OPP_ENTRY(21, 4, (-28000) (-24000), (-26000) (-16000)); + CPRH_OPP_ENTRY(22, 4, (-28000) (-16000), (-28000) (-16000)); + CPRH_OPP_ENTRY(23, 4, 0 (-20000), 0 (-17000)); + CPRH_OPP_ENTRY(24, 4, 0 (-16000), 0 (-15000)); + CPRH_OPP_ENTRY(25, 4, 0 (-12000), 0 (-14000)); + CPRH_OPP_ENTRY(26, 4, 0 (-28000), 0 (-27000)); + CPRH_OPP_ENTRY(27, 4, 0 (-28000), 0 (-27000)); + CPRH_OPP_ENTRY(28, 4, 0 (-28000), 0 (-28000)); + CPRH_OPP_ENTRY(29, 4, 0 (-28000), 0 (-28000)); + CPRH_OPP_ENTRY(30, 4, 0 (-28000), 0 (-28000)); + }; + firmware { scm { compatible = "qcom,scm-msm8998", "qcom,scm"; @@ -873,7 +1294,7 @@ qfprom: qfprom@784000 { compatible = "qcom,qfprom"; - reg = <0x00784000 0x621c>; + reg = <0x00784000 0x221c>; #address-cells = <1>; #size-cells = <1>; @@ -881,6 +1302,186 @@ reg = <0x23a 0x1>; bits = <0 4>; }; + + cpr_efuse_speedbin: speedbin@133 { + reg = <0x133 0x2>; + bits = <5 3>; + }; + + cpr_fuse_revision: cpr_fusing_rev@13e { + reg = <0x13E 0x1>; + bits = <3 3>; + }; + + /* CPR Ring Oscillator: Power Cluster */ + cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 { + reg = <0x219 0x2>; + bits = <4 4>; + }; + + cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 { + reg = <0x219 0x1>; + bits = <0 4>; + }; + + cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 { + reg = <0x218 0x2>; + bits = <4 4>; + }; + + cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 { + reg = <0x218 0x1>; + bits = <0 4>; + }; + + /* CPR Init Voltage: Power Cluster */ + cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c { + reg = <0x21C 0x2>; + bits = <2 6>; + }; + + cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b { + reg = <0x21B 0x2>; + bits = <4 6>; + }; + + cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a { + reg = <0x21A 0x2>; + bits = <6 6>; + }; + + cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a { + reg = <0x21A 0x1>; + bits = <0 6>; + }; + + /* CPR Target Quotients: Power Cluster */ + cpr_quot0_pwrcl: quot0_pwrcl@222 { + reg = <0x222 0x3>; + bits = <2 12>; + }; + + cpr_quot1_pwrcl: quot1_pwrcl@220 { + reg = <0x220 0x3>; + bits = <6 12>; + }; + + cpr_quot2_pwrcl: quot2_pwrcl@21f { + reg = <0x21F 0x2>; + bits = <2 11>; + }; + + cpr_quot3_pwrcl: quot3_pwrcl@21d { + reg = <0x21D 0x3>; + bits = <6 12>; + }; + + /* CPR Quotient Offsets: Power Cluster */ + cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 { + reg = <0x227 0x2>; + bits = <7 6>; + }; + + cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 { + reg = <0x227 0x1>; + bits = <0 7>; + }; + + cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 { + reg = <0x226 0x2>; + bits = <1 7>; + }; + + /* CPR Aging Quotient Offsets: Power Cluster */ + cpr_aging_quot_off_pwrcl: qoff_aging_pwrcl@228 { + reg = <0x228 0x2>; + bits = <6 8>; + }; + + /* CPR Ring Oscillator: Performance Cluster */ + cpr_ro_sel0_perfcl: rosel0_perfcl@22b { + reg = <0x22B 0x1>; + bits = <2 4>; + }; + + cpr_ro_sel1_perfcl: rosel1_perfcl@22a { + reg = <0x22A 0x2>; + bits = <6 4>; + }; + + cpr_ro_sel2_perfcl: rosel2_perfcl@22a { + reg = <0x22A 0x1>; + bits = <2 4>; + }; + + cpr_ro_sel3_perfcl: rosel3_perfcl@229 { + reg = <0x229 0x2>; + bits = <6 4>; + }; + + /* CPR Init Voltage: Performance Cluster */ + cpr_init_voltage0_perfcl: ivolt0_perfcl@22e { + reg = <0x22E 0x1>; + bits = <0 6>; + }; + + cpr_init_voltage1_perfcl: ivolt1_perfcl@22d { + reg = <0x22D 0x2>; + bits = <2 6>; + }; + + cpr_init_voltage2_perfcl: ivolt2_perfcl@22c { + reg = <0x22C 0x2>; + bits = <4 6>; + }; + + cpr_init_voltage3_perfcl: ivolt3_perfcl@22b { + reg = <0x22B 0x2>; + bits = <6 6>; + }; + + /* CPR Target Quotients: Performance Cluster */ + cpr_quot0_perfcl: quot0_perfcl@234 { + reg = <0x234 0x2>; + bits = <0 12>; + }; + + cpr_quot1_perfcl: quot1_perfcl@232 { + reg = <0x232 0x2>; + bits = <4 12>; + }; + + cpr_quot2_perfcl: quot2_perfcl@231 { + reg = <0x231 0x2>; + bits = <0 12>; + }; + + cpr_quot3_perfcl: quot3_perfcl@22f { + reg = <0x22F 0x2>; + bits = <4 11>; + }; + + /* CPR Quotient Offsets: Performance Cluster */ + cpr_quot_offset1_perfcl: qoff1_perfcl@239 { + reg = <0x239 0x2>; + bits = <5 3>; + }; + + cpr_quot_offset2_perfcl: qoff2_perfcl@238 { + reg = <0x238 0x2>; + bits = <6 7>; + }; + + cpr_quot_offset3_perfcl: qoff3_perfcl@237 { + reg = <0x237 0x2>; + bits = <7 7>; + }; + + /* CPR Aging Quotient Offsets: Performance Cluster */ + cpr_aging_quot_off_perfcl: qoff_aging_perfcl@23b { + reg = <0x23b 0x2>; + bits = <1 8>; + }; }; bimc: interconnect@1008000 { @@ -2903,6 +3504,38 @@ clocks = <&xo>, <&xo>; }; + power-controller@17812000 { + compatible = "qcom,msm8998-gold-saw2-v4.1-l2", + "qcom,saw2"; + reg = <0x017812000 0x1000>; + }; + + power-controller@17912000 { + compatible = "qcom,msm8998-silver-saw2-v4.1-l2", + "qcom,saw2"; + reg = <0x017912000 0x1000>; + }; + + cpufreq_hw: cpufreq_hw@17814800 { + compatible = "qcom,cpufreq-hw-8998"; + reg = <0x017914800 0x100>, <0x017814800 0x100>, + <0x0179c0000 0x1000>, <0x0179c1000 0x1000>, + <0x0179c2000 0x1000>, <0x0179c3000 0x1000>; + reg-names = "osm-acd0", "osm-acd1", + "osm-domain0", "freq-domain0", + "osm-domain1", "freq-domain1"; + + assigned-clocks = <&gcc HMSS_GPLL0_CLK_SRC>; + assigned-clock-rates = <300000000>; + + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc HMSS_GPLL0_CLK_SRC>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + status = "disabled"; + }; + apcs_glb: mailbox@17911000 { compatible = "qcom,msm8998-apcs-hmss-global"; reg = <0x17911000 0x1000>; @@ -2968,6 +3601,92 @@ }; }; + /* Gold and Silver cluster */ + apc_cprh: power-controller@179c8000 { + compatible = "qcom,msm8998-cprh"; + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; + + assigned-clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + assigned-clock-rates = <19200000>; + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "ref"; + + operating-points-v2 = <&cprh_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX_AO>; + #power-domain-cells = <1>; + status = "disabled"; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>, + <&cpr_aging_quot_off_pwrcl>, + <&cpr_quot0_perfcl>, + <&cpr_quot1_perfcl>, + <&cpr_quot2_perfcl>, + <&cpr_quot3_perfcl>, + <&cpr_quot_offset1_perfcl>, + <&cpr_quot_offset2_perfcl>, + <&cpr_quot_offset3_perfcl>, + <&cpr_init_voltage0_perfcl>, + <&cpr_init_voltage1_perfcl>, + <&cpr_init_voltage2_perfcl>, + <&cpr_init_voltage3_perfcl>, + <&cpr_ro_sel0_perfcl>, + <&cpr_ro_sel1_perfcl>, + <&cpr_ro_sel2_perfcl>, + <&cpr_ro_sel3_perfcl>, + <&cpr_aging_quot_off_perfcl>; + + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4", + "cpr0_aging_quotient", + "cpr1_quotient1", + "cpr1_quotient2", + "cpr1_quotient3", + "cpr1_quotient4", + "cpr1_quotient_offset2", + "cpr1_quotient_offset3", + "cpr1_quotient_offset4", + "cpr1_init_voltage1", + "cpr1_init_voltage2", + "cpr1_init_voltage3", + "cpr1_init_voltage4", + "cpr1_ring_osc1", + "cpr1_ring_osc2", + "cpr1_ring_osc3", + "cpr1_ring_osc4", + "cpr1_aging_quotient"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x17a00000 0x10000>, /* GICD */ From 4d6bf1ecf51b56f9afd5b1961c11c804ded6c530 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 9 Jan 2021 14:37:35 +0100 Subject: [PATCH 077/174] drm/msm/dpu: Add a function to retrieve the current CTL status Add a function that returns whether the requested CTL is active or not: this will be used in a later commit to fix command mode panel issues. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 02da9ecf71f1..3584f5ee6bb3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -92,6 +92,11 @@ static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); } +static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx) +{ + return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0)); +} + static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) { trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, @@ -587,6 +592,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_pending_flush = dpu_hw_ctl_get_pending_flush; ops->get_flush_register = dpu_hw_ctl_get_flush_register; ops->trigger_start = dpu_hw_ctl_trigger_start; + ops->is_started = dpu_hw_ctl_is_started; ops->trigger_pending = dpu_hw_ctl_trigger_pending; ops->reset = dpu_hw_ctl_reset_control; ops->wait_reset_status = dpu_hw_ctl_wait_reset_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..ac1544474022 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -61,6 +61,13 @@ struct dpu_hw_ctl_ops { */ void (*trigger_start)(struct dpu_hw_ctl *ctx); + /** + * check if the ctl is started + * @ctx : ctl path ctx pointer + * @Return: true if started, false if stopped + */ + bool (*is_started)(struct dpu_hw_ctl *ctx); + /** * kickoff prepare is in progress hw operation for sw * controlled interfaces: DSI cmd mode and WB interface From 9b043633d20488b0314d87de3c03a2ee747d6359 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 9 Jan 2021 14:37:36 +0100 Subject: [PATCH 078/174] drm/msm/dpu: Fix timeout issues on command mode panels In function dpu_encoder_phys_cmd_wait_for_commit_done we are always checking if the relative CTL is started by waiting for an interrupt to fire: it is fine to do that, but then sometimes we call this function while the CTL is up and has never been put down, but that interrupt gets raised only when the CTL gets a state change from 0 to 1 (disabled to enabled), so we're going to wait for something that will never happen on its own. Solving this while avoiding to restart the CTL is actually possible and can be done by just checking if it is already up and running when the wait_for_commit_done function is called: in this case, so, if the CTL was already running, we can say that the commit is done if the command transmission is complete (in other terms, if the interface has been flushed). Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 34a6940d12c5..72f06aa46a64 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -682,6 +682,9 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; + if (phys_enc->hw_ctl->ops.is_started) + return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc); + return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); } From 666c6e98513830a12fce248125c0935de5e9ca41 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Dec 2020 19:24:41 +0100 Subject: [PATCH 079/174] clk: qcom: smd: Add missing MSM8998 RPM clocks Signed-off-by: Konrad Dybcio JAMI: fixed for a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") JAMI: fixed for 36354c32bd76 ("clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_ops") --- drivers/clk/qcom/clk-smd-rpm.c | 68 ++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 27 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ea28e45ca371..31ec583c40b4 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -805,15 +805,20 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, - 3, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8998, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, + 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000); + static struct clk_smd_rpm *msm8998_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, @@ -826,12 +831,22 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -844,10 +859,14 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin, }; @@ -857,14 +876,9 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .num_clks = ARRAY_SIZE(msm8998_clks), }; -DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, - 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000); - static struct clk_smd_rpm *sdm660_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, @@ -891,16 +905,16 @@ static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, - [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, + [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, + [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { @@ -909,8 +923,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { }; static struct clk_smd_rpm *mdm9607_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, @@ -931,8 +945,8 @@ static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { }; static struct clk_smd_rpm *msm8953_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, @@ -980,8 +994,8 @@ DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, QCOM_SMD_RPM_BUS_CLK, 5); static struct clk_smd_rpm *sm6125_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, @@ -1002,8 +1016,8 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, @@ -1023,8 +1037,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { /* SM6115 */ static struct clk_smd_rpm *sm6115_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, @@ -1075,8 +1089,8 @@ DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); static struct clk_smd_rpm *qcm2290_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &msm8998_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &msm8998_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, From d330c5bc8cc5672ebf4a6bec2e7d788bebc0c6f2 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 10 Dec 2020 17:27:40 +0100 Subject: [PATCH 080/174] drm/msm/dpu1: Add MSM8998 to hw catalog Bringup functionality for MSM8998 in the DPU, driver which is mostly the same as SDM845 (just a few variations). Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for 5.17) --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 329 +++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 2 files changed, 319 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index aa75991903a6..2b662da31255 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -16,6 +16,9 @@ BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) +#define VIG_MSM8998_MASK \ + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) + #define VIG_SDM845_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) @@ -25,6 +28,11 @@ #define VIG_SM8250_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) +#define DMA_MSM8998_MASK \ + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ + BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -33,6 +41,9 @@ #define DMA_CURSOR_SDM845_MASK \ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_CURSOR_MSM8998_MASK \ + (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) + #define MIXER_SDM845_MASK \ (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) @@ -49,6 +60,8 @@ #define MERGE_3D_SM8150_MASK (0) +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) + #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) #define INTF_SDM845_MASK (0) @@ -181,6 +194,22 @@ static const uint32_t plane_formats_yuv[] = { * DPU sub blocks config *************************************************************/ /* DPU top level caps */ +static const struct dpu_caps msm8998_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, + .ubwc_version = DPU_HW_UBWC_VER_10, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, @@ -251,6 +280,35 @@ static const struct dpu_caps sc7280_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_mdp_cfg msm8998_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x458, + .features = 0, + .highest_bank_bit = 0x2, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { + .reg_off = 0x2B4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { + .reg_off = 0x2BC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { + .reg_off = 0x2C4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { + .reg_off = 0x2C4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { + .reg_off = 0x2C4, .bit_off = 12}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x3A8, .bit_off = 15}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x3B0, .bit_off = 15}, + }, +}; + static const struct dpu_mdp_cfg sdm845_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -339,6 +397,39 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { /************************************************************* * CTL sub blocks config *************************************************************/ +static const struct dpu_ctl_cfg msm8998_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + static const struct dpu_ctl_cfg sdm845_ctl[] = { { .name = "ctl_0", .id = CTL_0, @@ -497,6 +588,15 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { .virt_num_formats = ARRAY_SIZE(plane_formats), \ } +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = + _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = + _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = + _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = + _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = @@ -523,6 +623,25 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); .clk_ctrl = _clkctrl \ } +static const struct dpu_sspp_cfg msm8998_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, + msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, + msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, + msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, + msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg sdm845_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -599,17 +718,6 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { * MIXER sub blocks config *************************************************************/ -/* SDM845 */ - -static const struct dpu_lm_sub_blks sdm845_lm_sblk = { - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .maxblendstages = 11, /* excluding base layer */ - .blendstage_base = { /* offsets relative to mixer base */ - 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, - 0xb0, 0xc8, 0xe0, 0xf8, 0x110 - }, -}; - #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ { \ .name = _name, .id = _id, \ @@ -621,6 +729,43 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { .dspp = _dspp \ } +/* MSM8998 */ + +static const struct dpu_lm_sub_blks msm8998_lm_sblk = { + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages = 7, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x50, 0x80, 0xb0, 0x230, + 0x260, 0x290 + }, +}; + +static const struct dpu_lm_cfg msm8998_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), +}; + +/* SDM845 */ + +static const struct dpu_lm_sub_blks sdm845_lm_sblk = { + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages = 11, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, + 0xb0, 0xc8, 0xe0, 0xf8, 0x110 + }, +}; + static const struct dpu_lm_cfg sdm845_lm[] = { LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), @@ -682,6 +827,13 @@ static const struct dpu_lm_cfg sc7280_lm[] = { /************************************************************* * DSPP sub blocks config *************************************************************/ +static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { + .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .len = 0x90, .version = 0x10007}, + .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, + .len = 0x90, .version = 0x10007}, +}; + static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10000}, @@ -700,6 +852,13 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { .sblk = _sblk \ } +static const struct dpu_dspp_cfg msm8998_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), +}; + static const struct dpu_dspp_cfg sc7180_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, &sc7180_dspp_sblk), @@ -836,6 +995,13 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ } +static const struct dpu_intf_cfg msm8998_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + static const struct dpu_intf_cfg sdm845_intf[] = { INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), @@ -865,9 +1031,55 @@ static const struct dpu_intf_cfg sc7280_intf[] = { * VBIF sub blocks config *************************************************************/ /* VBIF QOS remap */ +static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; +static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; +static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { + { + .pps = 1088 * 1920 * 30, + .ot_limit = 2, + }, + { + .pps = 1088 * 1920 * 60, + .ot_limit = 6, + }, + { + .pps = 3840 * 2160 * 30, + .ot_limit = 16, + }, +}; + +static const struct dpu_vbif_cfg msm8998_vbif[] = { + { + .name = "vbif_0", .id = VBIF_0, + .base = 0, .len = 0x1040, + .default_ot_rd_limit = 32, + .default_ot_wr_limit = 32, + .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), + .xin_halt_timeout = 0x4000, + .dynamic_ot_rd_tbl = { + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg = msm8998_ot_rdwr_cfg, + }, + .dynamic_ot_wr_tbl = { + .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg = msm8998_ot_rdwr_cfg, + }, + .qos_rt_tbl = { + .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), + .priority_lvl = msm8998_rt_pri_lvl, + }, + .qos_nrt_tbl = { + .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), + .priority_lvl = msm8998_nrt_pri_lvl, + }, + .memtype_count = 14, + .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, + }, +}; + static const struct dpu_vbif_cfg sdm845_vbif[] = { { .name = "vbif_0", .id = VBIF_0, @@ -908,6 +1120,22 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { *************************************************************/ /* SSPP QOS LUTs */ +static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { + {.fl = 4, .lut = 0x1b}, + {.fl = 5, .lut = 0x5b}, + {.fl = 6, .lut = 0x15b}, + {.fl = 7, .lut = 0x55b}, + {.fl = 8, .lut = 0x155b}, + {.fl = 9, .lut = 0x555b}, + {.fl = 10, .lut = 0x1555b}, + {.fl = 11, .lut = 0x5555b}, + {.fl = 12, .lut = 0x15555b}, + {.fl = 13, .lut = 0x55555b}, + {.fl = 14, .lut = 0}, + {.fl = 1, .lut = 0x1b}, + {.fl = 0, .lut = 0} +}; + static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { {.fl = 4, .lut = 0x357}, {.fl = 5, .lut = 0x3357}, @@ -923,6 +1151,15 @@ static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { {.fl = 0, .lut = 0x11222222223357} }; +static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { + {.fl = 10, .lut = 0x1aaff}, + {.fl = 11, .lut = 0x5aaff}, + {.fl = 12, .lut = 0x15aaff}, + {.fl = 13, .lut = 0x55aaff}, + {.fl = 1, .lut = 0x1aaff}, + {.fl = 0, .lut = 0}, +}; + static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { {.fl = 0, .lut = 0x0011222222335777}, }; @@ -944,6 +1181,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { {.fl = 0, .lut = 0x0011223344556677}, }; +static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { + {.fl = 0, .lut = 0x0}, +}; + static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; @@ -952,6 +1193,42 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; +static const struct dpu_perf_cfg msm8998_perf_data = { + .max_bw_low = 6700000, + .max_bw_high = 6700000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 25, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(msm8998_qos_linear), + .entries = msm8998_qos_linear + }, + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), + .entries = msm8998_qos_macrotile + }, + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), + .entries = msm8998_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 200, + .bw_inefficiency_factor = 120, +}; + static const struct dpu_perf_cfg sdm845_perf_data = { .max_bw_low = 6800000, .max_bw_high = 6800000, @@ -1106,6 +1383,34 @@ static const struct dpu_perf_cfg sc7280_perf_data = { * Hardware catalog init *************************************************************/ +/* + * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets + * and instance counts. + */ +static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) +{ + *dpu_cfg = (struct dpu_mdss_cfg){ + .caps = &msm8998_dpu_caps, + .mdp_count = ARRAY_SIZE(msm8998_mdp), + .mdp = msm8998_mdp, + .ctl_count = ARRAY_SIZE(msm8998_ctl), + .ctl = msm8998_ctl, + .sspp_count = ARRAY_SIZE(msm8998_sspp), + .sspp = msm8998_sspp, + .mixer_count = ARRAY_SIZE(msm8998_lm), + .mixer = msm8998_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .intf_count = ARRAY_SIZE(msm8998_intf), + .intf = msm8998_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .reg_dma_count = 0, + .perf = msm8998_perf_data, + .mdss_irqs = IRQ_SM8250_MASK, + }; +} + /* * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets * and instance counts. @@ -1256,6 +1561,8 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) } static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { + { .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init}, + { .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init}, { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 47fe11a84a77..83a19bfe5f9c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1348,6 +1348,7 @@ static const struct dev_pm_ops dpu_pm_ops = { }; const struct of_device_id dpu_dt_match[] = { + { .compatible = "qcom,msm8998-dpu", }, { .compatible = "qcom,sdm845-dpu", }, { .compatible = "qcom,sc7180-dpu", }, { .compatible = "qcom,sc7280-dpu", }, From 1d6a05921e54c34394a3b382bad224f7cf2310ae Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Jan 2021 18:56:29 +0100 Subject: [PATCH 081/174] dt-bindings: i2c: qcom,i2c-qup: Convert txt to YAML schema Convert the qcom,i2c-qup binding to YAML schema. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 --------- .../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 87 +++++++++++++++++++ 2 files changed, 87 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt create mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt deleted file mode 100644 index dc71754a56af..000000000000 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Universal Peripheral (QUP) I2C controller - -Required properties: - - compatible: Should be: - * "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064. - * "qcom,i2c-qup-v2.1.1" for 8974 v1. - * "qcom,i2c-qup-v2.2.1" for 8974 v2 and later. - - reg: Should contain QUP register address and length. - - interrupts: Should contain I2C interrupt. - - - clocks: A list of phandles + clock-specifiers, one for each entry in - clock-names. - - clock-names: Should contain: - * "core" for the core clock - * "iface" for the AHB clock - - - #address-cells: Should be <1> Address cells for i2c device address - - #size-cells: Should be <0> as i2c addresses have no size component - -Optional properties: - - clock-frequency: Should specify the desired i2c bus clock frequency in Hz, - defaults to 100kHz if omitted. - -Child nodes should conform to i2c bus binding. - -Example: - - i2c@f9924000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9924000 0x1000>; - interrupts = <0 96 0>; - - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - - clock-frequency = <355000>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml new file mode 100644 index 000000000000..c5c7db3ac2a6 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Peripheral (QUP) I2C controller + +maintainers: + - Andy Gross + - Bjorn Andersson + +description: Binding for Qualcomm "QUP" I2C controllers + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - qcom,i2c-qup-v1.1.1 + - qcom,i2c-qup-v2.1.1 + - qcom,i2c-qup-v2.2.1 + + reg: + items: + - description: QUP I2C register iospace + + clocks: + items: + - description: Core QUP I2C clock + - description: AHB clock + + clock-names: + items: + - const: core + - const: iface + + clock-frequency: + minimum: 100000 + maximum: 1000000 + default: 100000 + + dmas: + items: + - description: RX DMA Channel phandle + - description: TX DMA Channel phandle + + dma-names: + items: + - const: rx + - const: tx + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - clocks + - clock-names + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + i2c@c175000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + }; From f7acfd9853586b93d61da61adb0ffac55c13d65e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Jan 2021 19:22:24 +0100 Subject: [PATCH 082/174] i2c: qup: Introduce SCL/SDA noise rejection Some I2C devices may be glitchy due to electrical noise coming from the device itself or because of possible board design issues. To overcome this issue, the QUP's I2C in Qualcomm SoCs supports a noise rejection setting for both SCL and SDA lines. Introduce a setting for noise rejection through device properties, "qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will be used to set the level of noise rejection sensitivity. If the properties are not specified, noise rejection will not be enabled. Signed-off-by: AngeloGioacchino Del Regno --- drivers/i2c/busses/i2c-qup.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c index 69e9f3ecf87d..f64f7e0d2620 100644 --- a/drivers/i2c/busses/i2c-qup.c +++ b/drivers/i2c/busses/i2c-qup.c @@ -39,6 +39,8 @@ #define QUP_MX_READ_CNT 0x208 #define QUP_IN_FIFO_BASE 0x218 #define QUP_I2C_CLK_CTL 0x400 +#define QUP_I2C_CLK_CTL_SDA_NR GENMASK(27, 26) +#define QUP_I2C_CLK_CTL_SCL_NR GENMASK(25, 24) #define QUP_I2C_STATUS 0x404 #define QUP_I2C_MASTER_GEN 0x408 @@ -1663,6 +1665,7 @@ static int qup_i2c_probe(struct platform_device *pdev) int ret, fs_div, hs_div; u32 src_clk_freq = DEFAULT_SRC_CLK; u32 clk_freq = DEFAULT_CLK_FREQ; + u32 noise_reject_scl = 0, noise_reject_sda = 0; int blocks; bool is_qup_v1; @@ -1860,6 +1863,19 @@ nodma: qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); } + /* SCL/SDA Noise rejection (optional) */ + ret = device_property_read_u32(qup->dev, "qcom,noise-reject-scl", + &noise_reject_scl); + if (ret == 0) + qup->clk_ctl |= FIELD_PREP(QUP_I2C_CLK_CTL_SCL_NR, + noise_reject_scl); + + ret = device_property_read_u32(qup->dev, "qcom,noise-reject-sda", + &noise_reject_sda); + if (ret == 0) + qup->clk_ctl |= FIELD_PREP(QUP_I2C_CLK_CTL_SDA_NR, + noise_reject_sda); + /* * Time it takes for a byte to be clocked out on the bus. * Each byte takes 9 clock cycles (8 bits + 1 ack). From 728bffed0b35f226f4e2a7f0801d89aaa29505fa Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Jan 2021 19:24:33 +0100 Subject: [PATCH 083/174] dt-bindings: i2c: qcom,i2c-qup: Document noise rejection properties Document the new noise rejection properties "qcom,noise-reject-sda" and "qcom,noise-reject-scl". Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml index c5c7db3ac2a6..3f14dd65c6b9 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml @@ -58,6 +58,20 @@ properties: '#size-cells': const: 0 + qcom,noise-reject-sda: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Noise rejection level for the SDA line. + minimum: 0 + maximum: 3 + default: 0 + + qcom,noise-reject-scl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Noise rejection level for the SCL line. + minimum: 0 + maximum: 3 + default: 0 + required: - compatible - clocks From d4148f80f94a083118ef5edb854c5ed3ee745fee Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 20 Jan 2021 13:32:32 +0100 Subject: [PATCH 084/174] dt-bindings: interconnect: Add bindings for Qualcomm MSM8998 NoC Add the bindings for the Qualcomm MSM8998 NoC interconnects. Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/interconnect/qcom,msm8998.yaml | 158 ++++++++++++++++++ .../dt-bindings/interconnect/qcom,msm8998.h | 128 ++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml create mode 100644 include/dt-bindings/interconnect/qcom,msm8998.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml new file mode 100644 index 000000000000..3bea90cbe053 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8998.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8998 Network-On-Chip interconnect + +maintainers: + - AngeloGioacchino Del Regno + - Konrad Dybcio + +description: | + The Qualcomm MSM8998 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + reg: + maxItems: 1 + + compatible: + enum: + - qcom,msm8998-a1noc + - qcom,msm8998-a2noc + - qcom,msm8998-bimc + - qcom,msm8998-cnoc + - qcom,msm8998-gnoc + - qcom,msm8998-mnoc + - qcom,msm8998-snoc + + '#interconnect-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + +required: + - compatible + - reg + - '#interconnect-cells' + - clock-names + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-mnoc + then: + properties: + clocks: + items: + - description: Bus Clock. + - description: Bus A Clock. + - description: CPU-NoC High-performance Bus Clock. + clock-names: + items: + - const: bus + - const: bus_a + - const: iface + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-a2noc + - qcom,msm8998-bimc + - qcom,msm8998-cnoc + - qcom,msm8998-gnoc + - qcom,msm8998-snoc + then: + properties: + clocks: + items: + - description: Bus Clock. + - description: Bus A Clock. + clock-names: + items: + - const: bus + - const: bus_a + +examples: + - | + #include + #include + + bimc: interconnect@1008000 { + compatible = "qcom,msm8998-bimc"; + reg = <0x01008000 0x78000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + cnoc: interconnect@1500000 { + compatible = "qcom,msm8998-cnoc"; + reg = <0x01500000 0x10000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@1625000 { + compatible = "qcom,msm8998-snoc"; + reg = <0x01625000 0x6100>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a1noc: interconnect@1669000 { + compatible = "qcom,msm8998-a1noc"; + reg = <0x01669000 0x5020>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + + a2noc: interconnect@1705000 { + compatible = "qcom,msm8998-a2noc"; + reg = <0x01705000 0xa090>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mnoc: interconnect@1744000 { + compatible = "qcom,msm8998-mnoc"; + reg = <0x01744000 0xb010>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>, + <&mmcc AHB_CLK_SRC>; + }; + + gnoc: interconnect@17900000 { + compatible = "qcom,msm8998-gnoc"; + reg = <0x17900000 0xe000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&xo_board>, <&xo_board>; + }; diff --git a/include/dt-bindings/interconnect/qcom,msm8998.h b/include/dt-bindings/interconnect/qcom,msm8998.h new file mode 100644 index 000000000000..5b94403ef178 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8998.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* MSM8998 interconnect IDs */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8998_H + +/* A1NOC */ +#define MASTER_PCIE_0 0 +#define MASTER_USB3 1 +#define MASTER_UFS 2 +#define MASTER_BLSP_2 3 +#define SLAVE_A1NOC_SNOC 4 + +/* A2NOC */ +#define MASTER_IPA 0 +#define MASTER_CNOC_A2NOC 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_TSIF 4 +#define MASTER_BLSP_1 5 +#define MASTER_CRVIRT_A2NOC 6 +#define MASTER_CRYPTO_C0 7 +#define SLAVE_A2NOC_SNOC 8 +#define SLAVE_CRVIRT_A2NOC 9 + +/* BIMC */ +#define MASTER_GNOC_BIMC 0 +#define MASTER_OXILI 1 +#define MASTER_MNOC_BIMC 2 +#define MASTER_SNOC_BIMC 3 +#define SLAVE_EBI 4 +#define SLAVE_HMSS_L3 5 +#define SLAVE_BIMC_SNOC_0 6 +#define SLAVE_BIMC_SNOC_1 7 + +/* CNOC */ +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_CNOC_A2NOC 2 +#define SLAVE_SSC_CFG 3 +#define SLAVE_MPM 4 +#define SLAVE_PMIC_ARB 5 +#define SLAVE_TLMM_NORTH 6 +#define SLAVE_PIMEM_CFG 7 +#define SLAVE_IMEM_CFG 8 +#define SLAVE_MESSAGE_RAM 9 +#define SLAVE_SKL 10 +#define SLAVE_BIMC_CFG 11 +#define SLAVE_PRNG 12 +#define SLAVE_A2NOC_CFG 13 +#define SLAVE_IPA 14 +#define SLAVE_TCSR 15 +#define SLAVE_SNOC_CFG 16 +#define SLAVE_CLK_CTL 17 +#define SLAVE_GLM 18 +#define SLAVE_SPDM 19 +#define SLAVE_GPUSS_CFG 20 +#define SLAVE_CNOC_MNOC_CFG 21 +#define SLAVE_QM_CFG 22 +#define SLAVE_MSS_CFG 23 +#define SLAVE_UFS_CFG 24 +#define SLAVE_TLMM_WEST 25 +#define SLAVE_A1NOC_CFG 26 +#define SLAVE_AHB2PHY 27 +#define SLAVE_BLSP_2 28 +#define SLAVE_PDM 29 +#define SLAVE_USB3_0 30 +#define SLAVE_A1NOC_SMMU_CFG 31 +#define SLAVE_BLSP_1 32 +#define SLAVE_SDCC_2 33 +#define SLAVE_SDCC_4 34 +#define SLAVE_TSIF 35 +#define SLAVE_QDSS_CFG 36 +#define SLAVE_TLMM_EAST 37 +#define SLAVE_CNOC_MNOC_MMSS_CFG 38 +#define SLAVE_SRVC_CNOC 39 + +/* GNOC */ +#define MASTER_APSS_PROC 0 +#define SLAVE_GNOC_BIMC 1 + +/* MNOC */ +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CPP 1 +#define MASTER_JPEG 2 +#define MASTER_MDP_P0 3 +#define MASTER_MDP_P1 4 +#define MASTER_ROTATOR 5 +#define MASTER_VENUS 6 +#define MASTER_VFE 7 +#define MASTER_VENUS_VMEM 8 +#define SLAVE_MNOC_BIMC 9 +#define SLAVE_VMEM 10 +#define SLAVE_SRVC_MNOC 11 +#define MASTER_CNOC_MNOC_MMSS_CFG 12 +#define SLAVE_CAMERA_CFG 13 +#define SLAVE_CAMERA_THROTTLE_CFG 14 +#define SLAVE_MISC_CFG 15 +#define SLAVE_VENUS_THROTTLE_CFG 16 +#define SLAVE_VENUS_CFG 17 +#define SLAVE_VMEM_CFG 18 +#define SLAVE_MMSS_CLK_XPU_CFG 19 +#define SLAVE_MMSS_CLK_CFG 20 +#define SLAVE_DISPLAY_CFG 21 +#define SLAVE_DISPLAY_THROTTLE_CFG 22 +#define SLAVE_SMMU_CFG 23 + +/* SNOC */ +#define MASTER_HMSS 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_SNOC_CFG 2 +#define MASTER_BIMC_SNOC_0 3 +#define MASTER_BIMC_SNOC_1 4 +#define MASTER_A1NOC_SNOC 5 +#define MASTER_A2NOC_SNOC 6 +#define MASTER_QDSS_ETR 7 +#define SLAVE_HMSS 8 +#define SLAVE_LPASS 9 +#define SLAVE_WLAN 10 +#define SLAVE_SNOC_BIMC 11 +#define SLAVE_SNOC_CNOC 12 +#define SLAVE_IMEM 13 +#define SLAVE_PIMEM 14 +#define SLAVE_QDSS_STM 15 +#define SLAVE_PCIE_0 16 +#define SLAVE_SRVC_SNOC 17 + +#endif From c1fcb53c21cccd45c36d6ea7ed5f6e3eaf83a99b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 20 Jan 2021 13:33:59 +0100 Subject: [PATCH 085/174] interconnect: qcom: Add MSM8998 interconnect provider driver Introduce a driver for the Qualcomm interconnect busses found in the MSM/APQ8998 SoCs. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. On a note, these chips are managing the "bus QoS" in a "hybrid" fashion: some of the paths in the topology are managed through and by, of course) the RPM uC, while some others are "AP Owned", meaning that the AP shall do direct writes to the appropriate QoS registers for the specific paths and ports, instead of sending an indication to the RPM and leaving the job to that one. Co-authored-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for 5.17) --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8998.c | 981 ++++++++++++++++++++++++++++ 3 files changed, 992 insertions(+) create mode 100644 drivers/interconnect/qcom/msm8998.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 91353e651a52..75f5f9ad7b0a 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -44,6 +44,15 @@ config INTERCONNECT_QCOM_MSM8996 This is a driver for the Qualcomm Network-on-Chip on msm8996-based platforms. +config INTERCONNECT_QCOM_MSM8998 + tristate "Qualcomm MSM8998 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8998-based + platforms. + config INTERCONNECT_QCOM_OSM_L3 tristate "Qualcomm OSM L3 interconnect driver" depends on INTERCONNECT_QCOM || COMPILE_TEST diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index ceae9bb566c6..aaa82e07b197 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -5,6 +5,7 @@ qnoc-msm8916-objs := msm8916.o qnoc-msm8939-objs := msm8939.o qnoc-msm8974-objs := msm8974.o qnoc-msm8996-objs := msm8996.o +qnoc-msm8998-objs := msm8998.o icc-osm-l3-objs := osm-l3.o qnoc-qcm2290-objs := qcm2290.o qnoc-qcs404-objs := qcs404.o @@ -26,6 +27,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8998) += qnoc-msm8998.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o diff --git a/drivers/interconnect/qcom/msm8998.c b/drivers/interconnect/qcom/msm8998.c new file mode 100644 index 000000000000..764c2fc18a62 --- /dev/null +++ b/drivers/interconnect/qcom/msm8998.c @@ -0,0 +1,981 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm MSM8998 Network-on-Chip (NoC) QoS driver + * Copyright (c) 2020, AngeloGioacchino Del Regno + * + * Copyright (C) 2020, Konrad Dybcio + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "smd-rpm.h" + +#define RPM_BUS_MASTER_REQ 0x73616d62 +#define RPM_BUS_SLAVE_REQ 0x766c7362 + +/* BIMC QoS */ +#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) +#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) +#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i)) + +#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000 +#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300 +#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3 +#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8 +#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f + +#define M_BKE_EN_EN_BMASK 0x1 + +/* Valid for both NoC and BIMC */ +#define NOC_QOS_MODE_FIXED 0x0 +#define NOC_QOS_MODE_LIMITER 0x1 +#define NOC_QOS_MODE_BYPASS 0x2 + +/* NoC QoS */ +#define NOC_PERM_MODE_FIXED 1 +#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS) + +#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000)) +#define NOC_QOS_PRIORITY_MASK 0xf +#define NOC_QOS_PRIORITY_P1_SHIFT 0x2 +#define NOC_QOS_PRIORITY_P0_SHIFT 0x3 + +#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) +#define NOC_QOS_MODEn_MASK 0x3 + +enum { + MSM8998_MASTER_IPA = 1, + MSM8998_MASTER_CNOC_A2NOC, + MSM8998_MASTER_SDCC_2, + MSM8998_MASTER_SDCC_4, + MSM8998_MASTER_BLSP_1, + MSM8998_MASTER_BLSP_2, + MSM8998_MASTER_UFS, + MSM8998_MASTER_USB_HS, + MSM8998_MASTER_USB3, + MSM8998_MASTER_CRYPTO_C0, + MSM8998_MASTER_GNOC_BIMC, + MSM8998_MASTER_OXILI, + MSM8998_MASTER_MNOC_BIMC, + MSM8998_MASTER_SNOC_BIMC, + MSM8998_MASTER_PIMEM, + MSM8998_MASTER_SNOC_CNOC, + MSM8998_MASTER_QDSS_DAP, + MSM8998_MASTER_APPS_PROC, + MSM8998_MASTER_CNOC_MNOC_MMSS_CFG, + MSM8998_MASTER_CNOC_MNOC_CFG, + MSM8998_MASTER_CPP, + MSM8998_MASTER_JPEG, + MSM8998_MASTER_MDP_P0, + MSM8998_MASTER_MDP_P1, + MSM8998_MASTER_VENUS, + MSM8998_MASTER_VFE, + MSM8998_MASTER_QDSS_ETR, + MSM8998_MASTER_QDSS_BAM, + MSM8998_MASTER_SNOC_CFG, + MSM8998_MASTER_BIMC_SNOC, + MSM8998_MASTER_A1NOC_SNOC, + MSM8998_MASTER_A2NOC_SNOC, + MSM8998_MASTER_GNOC_SNOC, + MSM8998_MASTER_PCIE_0, + MSM8998_MASTER_A2NOC_TSIF, + MSM8998_MASTER_CRVIRT_A2NOC, + MSM8998_MASTER_ROTATOR, + MSM8998_MASTER_VENUS_VMEM, + MSM8998_MASTER_HMSS, + MSM8998_MASTER_BIMC_SNOC_0, + MSM8998_MASTER_BIMC_SNOC_1, + + MSM8998_SLAVE_A1NOC_SNOC, + MSM8998_SLAVE_A2NOC_SNOC, + MSM8998_SLAVE_EBI, + MSM8998_SLAVE_HMSS_L3, + MSM8998_SLAVE_CNOC_A2NOC, + MSM8998_SLAVE_MPM, + MSM8998_SLAVE_PMIC_ARB, + MSM8998_SLAVE_TLMM_NORTH, + MSM8998_SLAVE_TCSR, + MSM8998_SLAVE_PIMEM_CFG, + MSM8998_SLAVE_IMEM_CFG, + MSM8998_SLAVE_MESSAGE_RAM, + MSM8998_SLAVE_GLM, + MSM8998_SLAVE_BIMC_CFG, + MSM8998_SLAVE_PRNG, + MSM8998_SLAVE_SPDM, + MSM8998_SLAVE_QDSS_CFG, + MSM8998_SLAVE_CNOC_MNOC_CFG, + MSM8998_SLAVE_SNOC_CFG, + MSM8998_SLAVE_QM_CFG, + MSM8998_SLAVE_CLK_CTL, + MSM8998_SLAVE_MSS_CFG, + MSM8998_SLAVE_UFS_CFG, + MSM8998_SLAVE_A2NOC_CFG, + MSM8998_SLAVE_A2NOC_SMMU_CFG, + MSM8998_SLAVE_GPUSS_CFG, + MSM8998_SLAVE_AHB2PHY, + MSM8998_SLAVE_BLSP_1, + MSM8998_SLAVE_SDCC_2, + MSM8998_SLAVE_SDCC_4, + MSM8998_SLAVE_BLSP_2, + MSM8998_SLAVE_PDM, + MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG, + MSM8998_SLAVE_USB_HS, + MSM8998_SLAVE_USB3_0, + MSM8998_SLAVE_SRVC_CNOC, + MSM8998_SLAVE_GNOC_BIMC, + MSM8998_SLAVE_GNOC_SNOC, + MSM8998_SLAVE_CAMERA_CFG, + MSM8998_SLAVE_CAMERA_THROTTLE_CFG, + MSM8998_SLAVE_MISC_CFG, + MSM8998_SLAVE_VENUS_THROTTLE_CFG, + MSM8998_SLAVE_VENUS_CFG, + MSM8998_SLAVE_MMSS_CLK_XPU_CFG, + MSM8998_SLAVE_MMSS_CLK_CFG, + MSM8998_SLAVE_MNOC_MPU_CFG, + MSM8998_SLAVE_DISPLAY_CFG, + MSM8998_SLAVE_CSI_PHY_CFG, + MSM8998_SLAVE_DISPLAY_THROTTLE_CFG, + MSM8998_SLAVE_SMMU_CFG, + MSM8998_SLAVE_MNOC_BIMC, + MSM8998_SLAVE_SRVC_MNOC, + MSM8998_SLAVE_HMSS, + MSM8998_SLAVE_LPASS, + MSM8998_SLAVE_WLAN, + MSM8998_SLAVE_CDSP, + MSM8998_SLAVE_IPA, + MSM8998_SLAVE_SNOC_BIMC, + MSM8998_SLAVE_SNOC_CNOC, + MSM8998_SLAVE_IMEM, + MSM8998_SLAVE_PIMEM, + MSM8998_SLAVE_QDSS_STM, + MSM8998_SLAVE_SRVC_SNOC, + MSM8998_SLAVE_BIMC_SNOC_0, + MSM8998_SLAVE_BIMC_SNOC_1, + MSM8998_SLAVE_SSC_CFG, + MSM8998_SLAVE_SKL, + MSM8998_SLAVE_TLMM_WEST, + MSM8998_SLAVE_A1NOC_CFG, + MSM8998_SLAVE_A1NOC_SMMU_CFG, + MSM8998_SLAVE_TSIF, + MSM8998_SLAVE_TLMM_EAST, + MSM8998_SLAVE_CRVIRT_A2NOC, + MSM8998_SLAVE_VMEM_CFG, + MSM8998_SLAVE_VMEM, + MSM8998_SLAVE_PCIE_0, +}; + +#define to_qcom_provider(_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +static const struct clk_bulk_data bus_clocks[] = { + { .id = "bus" }, + { .id = "bus_a" }, +}; + +static const struct clk_bulk_data bus_mm_clocks[] = { + { .id = "bus" }, + { .id = "bus_a" }, + { .id = "iface" }, +}; + +/** + * struct qcom_icc_provider - Qualcomm specific interconnect provider + * @provider: generic interconnect provider + * @bus_clks: the clk_bulk_data table of bus clocks + * @num_clks: the total number of clk_bulk_data entries + * @is_bimc_node: indicates whether to use bimc specific setting + * @mmio: NoC base iospace + */ +struct qcom_icc_provider { + struct icc_provider provider; + struct clk_bulk_data *bus_clks; + int num_clks; + bool is_bimc_node; + struct regmap *regmap; + void __iomem *mmio; +}; + +#define MSM8998_MAX_LINKS 38 + +/** + * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters + * @areq_prio: node requests priority + * @prio_level: priority level for bus communication + * @limit_commands: activate/deactivate limiter mode during runtime + * @ap_owned: indicates if the node is owned by the AP or by the RPM + * @qos_mode: default qos mode for this node + * @qos_port: qos port number for finding qos registers of this node + */ +struct qcom_icc_qos { + u32 areq_prio; + u32 prio_level; + bool limit_commands; + bool ap_owned; + int qos_mode; + int qos_port; +}; + +/** + * struct qcom_icc_node - Qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @buswidth: width of the interconnect between a node and the bus (bytes) + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @qos: NoC QoS setting parameters + * @rate: current bus clock rate in Hz + */ +struct qcom_icc_node { + unsigned char *name; + u16 id; + u16 links[MSM8998_MAX_LINKS]; + u16 num_links; + u16 buswidth; + int mas_rpm_id; + int slv_rpm_id; + struct qcom_icc_qos qos; + u64 rate; +}; + +struct qcom_icc_desc { + struct qcom_icc_node **nodes; + size_t num_nodes; + const struct regmap_config *regmap_cfg; +}; + +#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ + _ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \ + static struct qcom_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .qos.ap_owned = _ap_owned, \ + .qos.qos_mode = _qos_mode, \ + .qos.areq_prio = _qos_prio, \ + .qos.prio_level = _qos_prio, \ + .qos.qos_port = _qos_port, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ + } + +/* masters */ +DEFINE_QNODE(mas_pcie_0, MSM8998_MASTER_PCIE_0, 16, 45, -1, true, NOC_QOS_MODE_FIXED, 1, 1, MSM8998_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(mas_usb3, MSM8998_MASTER_USB3, 16, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, MSM8998_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(mas_ufs, MSM8998_MASTER_UFS, 16, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 2, MSM8998_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(mas_blsp_2, MSM8998_MASTER_BLSP_2, 16, 39, -1, false, NOC_QOS_MODE_FIXED, 0, 4, MSM8998_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(mas_cnoc_a2noc, MSM8998_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_ipa, MSM8998_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 1, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_sdcc_2, MSM8998_MASTER_SDCC_2, 8, 35, -1, false, NOC_QOS_MODE_FIXED, 0, 6, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_sdcc_4, MSM8998_MASTER_SDCC_4, 8, 36, -1, false, NOC_QOS_MODE_FIXED, 0, 7, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_tsif, MSM8998_MASTER_A2NOC_TSIF, 4, 37, -1, true, -1, 0, -1, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_blsp_1, MSM8998_MASTER_BLSP_1, 16, 41, -1, false, NOC_QOS_MODE_FIXED, 0, 8, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_crvirt_a2noc, MSM8998_MASTER_CRVIRT_A2NOC, 8, 145, -1, false, NOC_QOS_MODE_FIXED, 0, 9, MSM8998_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_gnoc_bimc, MSM8998_MASTER_GNOC_BIMC, 8, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, MSM8998_SLAVE_EBI, MSM8998_SLAVE_BIMC_SNOC_0); +DEFINE_QNODE(mas_oxili, MSM8998_MASTER_OXILI, 8, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, MSM8998_SLAVE_BIMC_SNOC_1, MSM8998_SLAVE_HMSS_L3, MSM8998_SLAVE_EBI, MSM8998_SLAVE_BIMC_SNOC_0); +DEFINE_QNODE(mas_mnoc_bimc, MSM8998_MASTER_MNOC_BIMC, 8, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, MSM8998_SLAVE_BIMC_SNOC_1, MSM8998_SLAVE_HMSS_L3, MSM8998_SLAVE_EBI, MSM8998_SLAVE_BIMC_SNOC_0); +DEFINE_QNODE(mas_snoc_bimc, MSM8998_MASTER_SNOC_BIMC, 8, 3, -1, false, NOC_QOS_MODE_BYPASS, 0, 3, MSM8998_SLAVE_HMSS_L3, MSM8998_SLAVE_EBI); +DEFINE_QNODE(mas_snoc_cnoc, MSM8998_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, MSM8998_SLAVE_SKL, MSM8998_SLAVE_BLSP_2, MSM8998_SLAVE_MESSAGE_RAM, MSM8998_SLAVE_TLMM_WEST, MSM8998_SLAVE_TSIF, MSM8998_SLAVE_MPM, MSM8998_SLAVE_BIMC_CFG, MSM8998_SLAVE_TLMM_EAST, MSM8998_SLAVE_SPDM, MSM8998_SLAVE_PIMEM_CFG, MSM8998_SLAVE_A1NOC_SMMU_CFG, MSM8998_SLAVE_BLSP_1, MSM8998_SLAVE_CLK_CTL, MSM8998_SLAVE_PRNG, MSM8998_SLAVE_USB3_0, MSM8998_SLAVE_QDSS_CFG, MSM8998_SLAVE_QM_CFG, MSM8998_SLAVE_A2NOC_CFG, MSM8998_SLAVE_PMIC_ARB, MSM8998_SLAVE_UFS_CFG, MSM8998_SLAVE_SRVC_CNOC, MSM8998_SLAVE_AHB2PHY, MSM8998_SLAVE_IPA, MSM8998_SLAVE_GLM, MSM8998_SLAVE_SNOC_CFG, MSM8998_SLAVE_SSC_CFG, MSM8998_SLAVE_SDCC_2, MSM8998_SLAVE_SDCC_4, MSM8998_SLAVE_PDM, MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG, MSM8998_SLAVE_CNOC_MNOC_CFG, MSM8998_SLAVE_MSS_CFG, MSM8998_SLAVE_IMEM_CFG, MSM8998_SLAVE_A1NOC_CFG, MSM8998_SLAVE_GPUSS_CFG, MSM8998_SLAVE_TCSR, MSM8998_SLAVE_TLMM_NORTH); +DEFINE_QNODE(mas_qdss_dap, MSM8998_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, MSM8998_SLAVE_SKL, MSM8998_SLAVE_BLSP_2, MSM8998_SLAVE_MESSAGE_RAM, MSM8998_SLAVE_TLMM_WEST, MSM8998_SLAVE_TSIF, MSM8998_SLAVE_MPM, MSM8998_SLAVE_BIMC_CFG, MSM8998_SLAVE_TLMM_EAST, MSM8998_SLAVE_SPDM, MSM8998_SLAVE_PIMEM_CFG, MSM8998_SLAVE_A1NOC_SMMU_CFG, MSM8998_SLAVE_BLSP_1, MSM8998_SLAVE_CLK_CTL, MSM8998_SLAVE_PRNG, MSM8998_SLAVE_USB3_0, MSM8998_SLAVE_QDSS_CFG, MSM8998_SLAVE_QM_CFG, MSM8998_SLAVE_A2NOC_CFG, MSM8998_SLAVE_PMIC_ARB, MSM8998_SLAVE_UFS_CFG, MSM8998_SLAVE_SRVC_CNOC, MSM8998_SLAVE_AHB2PHY, MSM8998_SLAVE_IPA, MSM8998_SLAVE_GLM, MSM8998_SLAVE_SNOC_CFG, MSM8998_SLAVE_SDCC_2, MSM8998_SLAVE_SDCC_4, MSM8998_SLAVE_PDM, MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG, MSM8998_SLAVE_CNOC_MNOC_CFG, MSM8998_SLAVE_MSS_CFG, MSM8998_SLAVE_IMEM_CFG, MSM8998_SLAVE_A1NOC_CFG, MSM8998_SLAVE_GPUSS_CFG, MSM8998_SLAVE_SSC_CFG, MSM8998_SLAVE_TCSR, MSM8998_SLAVE_TLMM_NORTH, MSM8998_SLAVE_CNOC_A2NOC); +DEFINE_QNODE(mas_crypto, MSM8998_MASTER_CRYPTO_C0, 650, 23, -1, false, -1, 0, -1, MSM8998_MASTER_CRVIRT_A2NOC); +DEFINE_QNODE(mas_apss_proc, MSM8998_MASTER_APPS_PROC, 32, 0, -1, true, -1, 0, -1, MSM8998_SLAVE_GNOC_BIMC); +DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, MSM8998_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, MSM8998_SLAVE_CAMERA_THROTTLE_CFG, MSM8998_SLAVE_VENUS_CFG, MSM8998_SLAVE_MISC_CFG, MSM8998_SLAVE_CAMERA_CFG, MSM8998_SLAVE_DISPLAY_THROTTLE_CFG, MSM8998_SLAVE_VENUS_THROTTLE_CFG, MSM8998_SLAVE_DISPLAY_CFG, MSM8998_SLAVE_MMSS_CLK_CFG, MSM8998_SLAVE_VMEM_CFG, MSM8998_SLAVE_MMSS_CLK_XPU_CFG, MSM8998_SLAVE_SMMU_CFG); +DEFINE_QNODE(mas_cnoc_mnoc_cfg, MSM8998_MASTER_CNOC_MNOC_CFG, 8, 5, -1, true, -1, 0, -1, MSM8998_SLAVE_SRVC_MNOC); +DEFINE_QNODE(mas_cpp, MSM8998_MASTER_CPP, 32, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, MSM8998_SLAVE_MNOC_BIMC); +DEFINE_QNODE(mas_jpeg, MSM8998_MASTER_JPEG, 32, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 7, MSM8998_SLAVE_MNOC_BIMC); +DEFINE_QNODE(mas_mdp_p0, MSM8998_MASTER_MDP_P0, 32, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, MSM8998_SLAVE_MNOC_BIMC); /* vrail-comp???? */ +DEFINE_QNODE(mas_mdp_p1, MSM8998_MASTER_MDP_P1, 32, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, MSM8998_SLAVE_MNOC_BIMC); /* vrail-comp??? */ +DEFINE_QNODE(mas_rotator, MSM8998_MASTER_ROTATOR, 32, 120, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, MSM8998_SLAVE_MNOC_BIMC); +DEFINE_QNODE(mas_venus, MSM8998_MASTER_VENUS, 32, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 3, MSM8998_SLAVE_MNOC_BIMC); +DEFINE_QNODE(mas_vfe, MSM8998_MASTER_VFE, 32, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, MSM8998_SLAVE_MNOC_BIMC); +DEFINE_QNODE(mas_venus_vmem, MSM8998_MASTER_VENUS_VMEM, 32, 121, -1, true, -1, 0, -1, MSM8998_SLAVE_VMEM); +DEFINE_QNODE(mas_hmss, MSM8998_MASTER_HMSS, 16, 118, -1, true, NOC_QOS_MODE_FIXED, 1, 3, MSM8998_SLAVE_PIMEM, MSM8998_SLAVE_IMEM, MSM8998_SLAVE_SNOC_BIMC); +DEFINE_QNODE(mas_qdss_bam, MSM8998_MASTER_QDSS_BAM, 16, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 1, MSM8998_SLAVE_IMEM, MSM8998_SLAVE_PIMEM, MSM8998_SLAVE_SNOC_CNOC, MSM8998_SLAVE_SNOC_BIMC); +DEFINE_QNODE(mas_snoc_cfg, MSM8998_MASTER_SNOC_CFG, 16, 20, -1, false, -1, 0, -1, MSM8998_SLAVE_SRVC_SNOC); +DEFINE_QNODE(mas_bimc_snoc_0, MSM8998_MASTER_BIMC_SNOC_0, 16, 21, -1, false, -1, 0, -1, MSM8998_SLAVE_PIMEM, MSM8998_SLAVE_LPASS, MSM8998_SLAVE_HMSS, MSM8998_SLAVE_WLAN, MSM8998_SLAVE_SNOC_CNOC, MSM8998_SLAVE_IMEM, MSM8998_SLAVE_QDSS_STM); +DEFINE_QNODE(mas_bimc_snoc_1, MSM8998_MASTER_BIMC_SNOC_1, 16, 109, -1, true, -1, 0, -1, MSM8998_SLAVE_PCIE_0); +DEFINE_QNODE(mas_a1noc_snoc, MSM8998_MASTER_A1NOC_SNOC, 16, 111, -1, false, -1, 0, -1, MSM8998_SLAVE_PIMEM, MSM8998_SLAVE_PCIE_0, MSM8998_SLAVE_LPASS, MSM8998_SLAVE_HMSS, MSM8998_SLAVE_SNOC_BIMC, MSM8998_SLAVE_SNOC_CNOC, MSM8998_SLAVE_IMEM, MSM8998_SLAVE_QDSS_STM); +DEFINE_QNODE(mas_a2noc_snoc, MSM8998_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, MSM8998_SLAVE_PIMEM, MSM8998_SLAVE_PCIE_0, MSM8998_SLAVE_LPASS, MSM8998_SLAVE_HMSS, MSM8998_SLAVE_SNOC_BIMC, MSM8998_SLAVE_WLAN, MSM8998_SLAVE_SNOC_CNOC, MSM8998_SLAVE_IMEM, MSM8998_SLAVE_QDSS_STM); +DEFINE_QNODE(mas_qdss_etr, MSM8998_MASTER_QDSS_ETR, 16, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 2, MSM8998_SLAVE_IMEM, MSM8998_MASTER_PIMEM, MSM8998_SLAVE_SNOC_CNOC, MSM8998_SLAVE_SNOC_BIMC); + +/* slaves */ +DEFINE_QNODE(slv_a1noc_snoc, MSM8998_SLAVE_A1NOC_SNOC, 16, -1, 142, false, -1, 0, -1, MSM8998_MASTER_A1NOC_SNOC); +DEFINE_QNODE(slv_a2noc_snoc, MSM8998_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, MSM8998_MASTER_A2NOC_SNOC); +DEFINE_QNODE(slv_ebi, MSM8998_SLAVE_EBI, 8, -1, 0, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_hmss_l3, MSM8998_SLAVE_HMSS_L3, 8, -1, 160, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_bimc_snoc_0, MSM8998_SLAVE_BIMC_SNOC_0, 8, -1, 2, false, -1, 0, -1, MSM8998_MASTER_BIMC_SNOC_0); +DEFINE_QNODE(slv_bimc_snoc_1, MSM8998_SLAVE_BIMC_SNOC_1, 8, -1, 138, true, -1, 0, -1, MSM8998_MASTER_BIMC_SNOC_1); +DEFINE_QNODE(slv_cnoc_a2noc, MSM8998_SLAVE_CNOC_A2NOC, 4, -1, 208, true, -1, 0, -1, MSM8998_MASTER_CNOC_A2NOC); +DEFINE_QNODE(slv_ssc_cfg, MSM8998_SLAVE_SSC_CFG, 4, -1, 177, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_mpm, MSM8998_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_pmic_arb, MSM8998_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_tlmm_north, MSM8998_SLAVE_TLMM_NORTH, 4, -1, 214, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_pimem_cfg, MSM8998_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_imem_cfg, MSM8998_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_message_ram, MSM8998_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_skl, MSM8998_SLAVE_SKL, 4, -1, 196, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_bimc_cfg, MSM8998_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_prng, MSM8998_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_a2noc_cfg, MSM8998_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_ipa, MSM8998_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_tcsr, MSM8998_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_snoc_cfg, MSM8998_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_clk_ctl, MSM8998_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_glm, MSM8998_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_spdm, MSM8998_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_gpuss_cfg, MSM8998_SLAVE_GPUSS_CFG, 4, -1, 11, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8998_SLAVE_BLSP_1, 4, -1, 66, true, -1, 0, -1, MSM8998_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE(slv_qm_cfg, MSM8998_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_mss_cfg, MSM8998_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_ufs_cfg, MSM8998_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_tlmm_west, MSM8998_SLAVE_TLMM_WEST, 4, -1, 215, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_a1noc_cfg, MSM8998_SLAVE_A1NOC_CFG, 4, -1, 147, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_ahb2phy, MSM8998_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_blsp_2, MSM8998_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_pdm, MSM8998_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_usb3_0, MSM8998_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_a1noc_smmu_cfg, MSM8998_SLAVE_A1NOC_SMMU_CFG, 8, -1, 149, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_blsp_1, MSM8998_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_sdcc_2, MSM8998_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_sdcc_4, MSM8998_SLAVE_SDCC_4, 4, -1, 34, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_tsif, MSM8998_SLAVE_TSIF, 4, -1, 35, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_qdss_cfg, MSM8998_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_tlmm_east, MSM8998_SLAVE_TLMM_EAST, 4, -1, 213, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8998_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, MSM8998_MASTER_CNOC_MNOC_MMSS_CFG); +DEFINE_QNODE(slv_srvc_cnoc, MSM8998_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_crvirt_a2noc, MSM8998_SLAVE_CRVIRT_A2NOC, 8, -1, 207, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_gnoc_bimc, MSM8998_SLAVE_GNOC_BIMC, 32, -1, 210, true, -1, 0, -1, MSM8998_MASTER_GNOC_BIMC); +DEFINE_QNODE(slv_camera_cfg, MSM8998_SLAVE_CAMERA_CFG, 8, -1, 3, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_camera_throttle_cfg, MSM8998_SLAVE_CAMERA_THROTTLE_CFG, 8, -1, 154, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_misc_cfg, MSM8998_SLAVE_MISC_CFG, 8, -1, 8, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_venus_throttle_cfg, MSM8998_SLAVE_VENUS_THROTTLE_CFG, 8, -1, 178, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_venus_cfg, MSM8998_SLAVE_VENUS_CFG, 8, -1, 10, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_vmem_cfg, MSM8998_SLAVE_VMEM_CFG, 8, -1, 180, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8998_SLAVE_MMSS_CLK_XPU_CFG, 8, -1, 13, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_mmss_clk_cfg, MSM8998_SLAVE_MMSS_CLK_CFG, 8, -1, 12, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_display_cfg, MSM8998_SLAVE_DISPLAY_CFG, 8, -1, 4, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_display_throttle_cfg, MSM8998_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_smmu_cfg, MSM8998_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_mnoc_bimc, MSM8998_SLAVE_MNOC_BIMC, 32, -1, 16, true, -1, 0, -1, MSM8998_MASTER_MNOC_BIMC); +DEFINE_QNODE(slv_vmem, MSM8998_SLAVE_VMEM, 32, -1, 179, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_srvc_mnoc, MSM8998_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_hmss, MSM8998_SLAVE_HMSS, 16, -1, 20, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_lpass, MSM8998_SLAVE_LPASS, 16, -1, 21, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_wlan, MSM8998_SLAVE_WLAN, 16, -1, 206, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_snoc_bimc, MSM8998_SLAVE_SNOC_BIMC, 32, -1, 24, false, -1, 0, -1, MSM8998_MASTER_SNOC_BIMC); +DEFINE_QNODE(slv_snoc_cnoc, MSM8998_SLAVE_SNOC_CNOC, 16, -1, 25, false, -1, 0, -1, MSM8998_MASTER_SNOC_CNOC); +DEFINE_QNODE(slv_imem, MSM8998_SLAVE_IMEM, 16, -1, 26, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_pimem, MSM8998_SLAVE_PIMEM, 16, -1, 166, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_qdss_stm, MSM8998_SLAVE_QDSS_STM, 16, -1, 30, false, -1, 0, -1, 0); +DEFINE_QNODE(slv_pcie_0, MSM8998_SLAVE_PCIE_0, 16, -1, 84, true, -1, 0, -1, 0); +DEFINE_QNODE(slv_srvc_snoc, MSM8998_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0); + +static struct qcom_icc_node *msm8998_a1noc_nodes[] = { + [MASTER_PCIE_0] = &mas_pcie_0, + [MASTER_USB3] = &mas_usb3, + [MASTER_UFS] = &mas_ufs, + [MASTER_BLSP_2] = &mas_blsp_2, + [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc, +}; + +static const struct regmap_config msm8998_a1noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x60000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_a1noc = { + .nodes = msm8998_a1noc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_a1noc_nodes), + .regmap_cfg = &msm8998_a1noc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_a2noc_nodes[] = { + [MASTER_IPA] = &mas_ipa, + [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, + [MASTER_SDCC_2] = &mas_sdcc_2, + [MASTER_SDCC_4] = &mas_sdcc_4, + [MASTER_TSIF] = &mas_tsif, + [MASTER_BLSP_1] = &mas_blsp_1, + [MASTER_CRVIRT_A2NOC] = &mas_crvirt_a2noc, + [MASTER_CRYPTO_C0] = &mas_crypto, + [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, + [SLAVE_CRVIRT_A2NOC] = &slv_crvirt_a2noc, +}; + +static const struct regmap_config msm8998_a2noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x60000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_a2noc = { + .nodes = msm8998_a2noc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_a2noc_nodes), + .regmap_cfg = &msm8998_a2noc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_bimc_nodes[] = { + [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, + [MASTER_OXILI] = &mas_oxili, + [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, + [MASTER_SNOC_BIMC] = &mas_snoc_bimc, + [SLAVE_EBI] = &slv_ebi, + [SLAVE_HMSS_L3] = &slv_hmss_l3, + [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0, + [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1, +}; + +static const struct regmap_config msm8998_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x80000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_bimc = { + .nodes = msm8998_bimc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_bimc_nodes), + .regmap_cfg = &msm8998_bimc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_cnoc_nodes[] = { + [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, + [MASTER_QDSS_DAP] = &mas_qdss_dap, + [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, + [SLAVE_SSC_CFG] = &slv_ssc_cfg, + [SLAVE_MPM] = &slv_mpm, + [SLAVE_PMIC_ARB] = &slv_pmic_arb, + [SLAVE_TLMM_NORTH] = &slv_tlmm_north, + [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, + [SLAVE_IMEM_CFG] = &slv_imem_cfg, + [SLAVE_MESSAGE_RAM] = &slv_message_ram, + [SLAVE_SKL] = &slv_skl, + [SLAVE_BIMC_CFG] = &slv_bimc_cfg, + [SLAVE_PRNG] = &slv_prng, + [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, + [SLAVE_IPA] = &slv_ipa, + [SLAVE_TCSR] = &slv_tcsr, + [SLAVE_SNOC_CFG] = &slv_snoc_cfg, + [SLAVE_CLK_CTL] = &slv_clk_ctl, + [SLAVE_GLM] = &slv_glm, + [SLAVE_SPDM] = &slv_spdm, + [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg, + [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, + [SLAVE_QM_CFG] = &slv_qm_cfg, + [SLAVE_MSS_CFG] = &slv_mss_cfg, + [SLAVE_UFS_CFG] = &slv_ufs_cfg, + [SLAVE_TLMM_WEST] = &slv_tlmm_west, + [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg, + [SLAVE_AHB2PHY] = &slv_ahb2phy, + [SLAVE_BLSP_2] = &slv_blsp_2, + [SLAVE_PDM] = &slv_pdm, + [SLAVE_USB3_0] = &slv_usb3_0, + [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg, + [SLAVE_BLSP_1] = &slv_blsp_1, + [SLAVE_SDCC_2] = &slv_sdcc_2, + [SLAVE_SDCC_4] = &slv_sdcc_4, + [SLAVE_TSIF] = &slv_tsif, + [SLAVE_QDSS_CFG] = &slv_qdss_cfg, + [SLAVE_TLMM_EAST] = &slv_tlmm_east, + [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, + [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc, +}; + +static const struct regmap_config msm8998_cnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_cnoc = { + .nodes = msm8998_cnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_cnoc_nodes), + .regmap_cfg = &msm8998_cnoc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_gnoc_nodes[] = { + [MASTER_APSS_PROC] = &mas_apss_proc, + [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, +}; + +static const struct regmap_config msm8998_gnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_gnoc = { + .nodes = msm8998_gnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_gnoc_nodes), + .regmap_cfg = &msm8998_gnoc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_mnoc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, + [MASTER_CPP] = &mas_cpp, + [MASTER_JPEG] = &mas_jpeg, + [MASTER_MDP_P0] = &mas_mdp_p0, + [MASTER_MDP_P1] = &mas_mdp_p1, + [MASTER_ROTATOR] = &mas_rotator, + [MASTER_VENUS] = &mas_venus, + [MASTER_VFE] = &mas_vfe, + [MASTER_VENUS_VMEM] = &mas_venus_vmem, + [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, + [SLAVE_VMEM] = &slv_vmem, + [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc, + [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, + [SLAVE_CAMERA_CFG] = &slv_camera_cfg, + [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, + [SLAVE_MISC_CFG] = &slv_misc_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, + [SLAVE_VENUS_CFG] = &slv_venus_cfg, + [SLAVE_VMEM_CFG] = &slv_vmem_cfg, + [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, + [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, + [SLAVE_DISPLAY_CFG] = &slv_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, + [SLAVE_SMMU_CFG] = &slv_smmu_cfg, +}; + +static const struct regmap_config msm8998_mnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_mnoc = { + .nodes = msm8998_mnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_mnoc_nodes), + .regmap_cfg = &msm8998_mnoc_regmap_config, +}; + +static struct qcom_icc_node *msm8998_snoc_nodes[] = { + [MASTER_HMSS] = &mas_hmss, + [MASTER_QDSS_BAM] = &mas_qdss_bam, + [MASTER_SNOC_CFG] = &mas_snoc_cfg, + [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0, + [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1, + [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc, + [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, + [MASTER_QDSS_ETR] = &mas_qdss_etr, + [SLAVE_HMSS] = &slv_hmss, + [SLAVE_LPASS] = &slv_lpass, + [SLAVE_WLAN] = &slv_wlan, + [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, + [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, + [SLAVE_IMEM] = &slv_imem, + [SLAVE_PIMEM] = &slv_pimem, + [SLAVE_QDSS_STM] = &slv_qdss_stm, + [SLAVE_PCIE_0] = &slv_pcie_0, + [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, +}; + +static const struct regmap_config msm8998_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + +static struct qcom_icc_desc msm8998_snoc = { + .nodes = msm8998_snoc_nodes, + .num_nodes = ARRAY_SIZE(msm8998_snoc_nodes), + .regmap_cfg = &msm8998_snoc_regmap_config, +}; + +static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, + struct qcom_icc_qos *qos, + int regnum) +{ + u32 val; + u32 mask; + + val = qos->prio_level; + mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK; + + val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT; + mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK; + + /* LIMITCMDS is not present on M_BKE_HEALTH_3 */ + if (regnum != 3) { + val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT; + mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; + } + + return regmap_update_bits(rmap, + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + mask, val); +} + +static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, + bool bypass_mode) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + u32 mode = NOC_QOS_MODE_BYPASS; + u32 val = 0; + int i, rc = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + /* + * QoS Priority: The QoS Health parameters are getting considered + * only if we are NOT in Bypass Mode. + */ + if (mode != NOC_QOS_MODE_BYPASS) { + for (i = 3; i >= 0; i--) { + rc = qcom_icc_bimc_set_qos_health(qp->regmap, + &qn->qos, i); + if (rc) + return rc; + } + + /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ + val = 1; + } + + return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + M_BKE_EN_EN_BMASK, val); +} + +static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, + struct qcom_icc_qos *qos) +{ + u32 val; + int rc; + + /* Must be updated one at a time, P1 first, P0 last */ + val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; + rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_MASK, val); + if (rc) + return rc; + + val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT; + return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_MASK, val); +} + +static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + u32 mode = NOC_QOS_MODE_BYPASS; + int rc = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + if (qn->qos.qos_port < 0) { + dev_dbg(src->provider->dev, + "NoC QoS: Skipping %s: vote aggregated on parent.\n", + qn->name); + return 0; + } + + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + if (mode == NOC_QOS_MODE_FIXED) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", + qn->name); + rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + if (rc) + return rc; + } else if (mode == NOC_QOS_MODE_BYPASS) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", + qn->name); + } + + return regmap_update_bits(qp->regmap, + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + NOC_QOS_MODEn_MASK, mode); +} + +static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) +{ + struct qcom_icc_provider *qp = to_qcom_provider(node->provider); + struct qcom_icc_node *qn = node->data; + + dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); + + if (qp->is_bimc_node) + return qcom_icc_set_bimc_qos(node, sum_bw, + (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS)); + + return qcom_icc_set_noc_qos(node, sum_bw); +} + +static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) +{ + int ret = 0; + + if (mas_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_MASTER_REQ, + mas_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", + mas_rpm_id, ret); + return ret; + } + } + + if (slv_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_SLAVE_REQ, + slv_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", + slv_rpm_id, ret); + return ret; + } + } + + return ret; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + struct icc_node *n; + u64 sum_bw; + u64 max_peak_bw; + u64 rate; + u32 agg_avg = 0; + u32 agg_peak = 0; + int ret, i; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + provider->aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + if (!qn->qos.ap_owned) { + /* send bandwidth request message to the RPM processor */ + ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); + if (ret) + return ret; + } else if (qn->qos.qos_mode != -1) { + /* set bandwidth directly from the AP */ + ret = qcom_icc_qos_set(src, sum_bw); + if (ret) + return ret; + } + + rate = max(sum_bw, max_peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate == rate) + return 0; + + for (i = 0; i < qp->num_clks; i++) { + ret = clk_set_rate(qp->bus_clks[i].clk, rate); + if (ret) { + pr_err("%s clk_set_rate error: %d\n", + qp->bus_clks[i].id, ret); + return ret; + } + } + + qn->rate = rate; + + return 0; +} + +static int qnoc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct qcom_icc_desc *desc; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct qcom_icc_node **qnodes; + struct qcom_icc_provider *qp; + struct icc_node *node; + struct resource *res; + size_t num_nodes, i; + int ret; + + /* wait for the RPM proxy */ + if (!qcom_icc_rpm_smd_available()) + return -EPROBE_DEFER; + + desc = of_device_get_match_data(dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (of_device_is_compatible(dev->of_node, "qcom,msm8998-mnoc")) { + qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks, + sizeof(bus_mm_clocks), GFP_KERNEL); + qp->num_clks = ARRAY_SIZE(bus_mm_clocks); + } else { + if (of_device_is_compatible(dev->of_node, "qcom,msm8998-bimc")) + qp->is_bimc_node = true; + + qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks), + GFP_KERNEL); + qp->num_clks = ARRAY_SIZE(bus_clocks); + } + if (!qp->bus_clks) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + qp->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(qp->mmio)) { + dev_err(dev, "Cannot ioremap interconnect bus resource\n"); + return PTR_ERR(qp->mmio); + } + + qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg); + if (IS_ERR(qp->regmap)) { + dev_err(dev, "Cannot regmap interconnect bus resource\n"); + return PTR_ERR(qp->regmap); + } + + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); + if (ret) + return ret; + + provider = &qp->provider; + INIT_LIST_HEAD(&provider->nodes); + provider->dev = dev; + provider->set = qcom_icc_set; + provider->aggregate = icc_std_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(dev, "error adding interconnect provider: %d\n", ret); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + platform_set_drvdata(pdev, qp); + + return 0; +err: + icc_nodes_remove(provider); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + icc_provider_del(provider); + + return ret; +} + +static int qnoc_remove(struct platform_device *pdev) +{ + struct qcom_icc_provider *qp = platform_get_drvdata(pdev); + + icc_nodes_remove(&qp->provider); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + return icc_provider_del(&qp->provider); +} + +static const struct of_device_id msm8998_noc_of_match[] = { + { .compatible = "qcom,msm8998-a1noc", .data = &msm8998_a1noc }, + { .compatible = "qcom,msm8998-a2noc", .data = &msm8998_a2noc }, + { .compatible = "qcom,msm8998-bimc", .data = &msm8998_bimc }, + { .compatible = "qcom,msm8998-cnoc", .data = &msm8998_cnoc }, + { .compatible = "qcom,msm8998-gnoc", .data = &msm8998_gnoc }, + { .compatible = "qcom,msm8998-mnoc", .data = &msm8998_mnoc }, + { .compatible = "qcom,msm8998-snoc", .data = &msm8998_snoc }, + { }, +}; +MODULE_DEVICE_TABLE(of, msm8998_noc_of_match); + +static struct platform_driver msm8998_noc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-msm8998", + .of_match_table = msm8998_noc_of_match, + .sync_state = icc_sync_state, + }, +}; +module_platform_driver(msm8998_noc_driver); +MODULE_DESCRIPTION("Qualcomm msm8998 NoC driver"); +MODULE_LICENSE("GPL v2"); From 96e86abbb4db8a87585ee336c95b39184d8e6a77 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 4 Dec 2020 22:34:58 +0100 Subject: [PATCH 086/174] pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander The Awinic AW9523(B) is a multi-function I2C gpio expander in a TQFN-24L package, featuring PWM (max 37mA per pin, or total max power 3.2Watts) for LED driving capability. It has two ports with 8 pins per port (for a total of 16 pins), configurable as either PWM with 1/256 stepping or GPIO input/output, 1.8V logic input; each GPIO can be configured as input or output independently from each other. This IC also has an internal interrupt controller, which is capable of generating an interrupt for each GPIO, depending on the configuration, and will raise an interrupt on the INTN pin to advertise this to an external interrupt controller. Signed-off-by: AngeloGioacchino Del Regno --- drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++ 3 files changed, 1140 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-aw9523.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6fc56d6598e2..7712559fa835 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -127,6 +127,23 @@ config PINCTRL_AXP209 selected. Say Y to enable pinctrl and GPIO support for the AXP209 PMIC. +config PINCTRL_AW9523 + bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver" + depends on OF && I2C + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP + help + The Awinic AW9523/AW9523B is a multi-function I2C GPIO + expander with PWM functionality. This driver bundles a + pinctrl driver to select the function muxing and a GPIO + driver to handle GPIO, when the GPIO function is selected. + + Say yes to enable pinctrl and GPIO support for the AW9523(B). + config PINCTRL_BM1880 bool "Bitmain BM1880 Pinctrl driver" depends on OF && (ARCH_BITMAIN || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f64d29f614ec..31fdf914babf 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o +obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c new file mode 100644 index 000000000000..bc8e1e9d6876 --- /dev/null +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -0,0 +1,1122 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Awinic AW9523B i2c pin controller driver + * Copyright (c) 2020, AngeloGioacchino Del Regno + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +#define AW9523_MAX_FUNCS 2 +#define AW9523_NUM_PORTS 2 +#define AW9523_PINS_PER_PORT 8 + +/* + * HW needs at least 20uS for reset and at least 1-2uS to recover from + * reset, but we have to account for eventual board quirks, if any: + * for this reason, keep reset asserted for 50uS and wait for 20uS + * to recover from the reset. + */ +#define AW9523_HW_RESET_US 50 +#define AW9523_HW_RESET_RECOVERY_US 20 + +/* Port 0: P0_0...P0_7 - Port 1: P1_0...P1_7 */ +#define AW9523_PIN_TO_PORT(pin) (pin >> 3) +#define AW9523_REG_IN_STATE(pin) (0x00 + AW9523_PIN_TO_PORT(pin)) +#define AW9523_REG_OUT_STATE(pin) (0x02 + AW9523_PIN_TO_PORT(pin)) +#define AW9523_REG_CONF_STATE(pin) (0x04 + AW9523_PIN_TO_PORT(pin)) +#define AW9523_REG_INTR_DIS(pin) (0x06 + AW9523_PIN_TO_PORT(pin)) +#define AW9523_REG_CHIPID 0x10 +#define AW9523_VAL_EXPECTED_CHIPID 0x23 + +#define AW9523_REG_GCR 0x11 +#define AW9523_GCR_ISEL_MASK GENMASK(0, 1) +#define AW9523_GCR_GPOMD_MASK BIT(4) + +#define AW9523_REG_PORT_MODE(pin) (0x12 + AW9523_PIN_TO_PORT(pin)) +#define AW9523_REG_SOFT_RESET 0x7f +#define AW9523_VAL_RESET 0x00 + +/* + * struct aw9523_irq - Interrupt controller structure + * @lock: mutex locking for the irq bus + * @irqchip: structure holding irqchip params + * @cached_gpio: stores the previous gpio status for bit comparison + */ +struct aw9523_irq { + struct mutex lock; + struct irq_chip *irqchip; + u16 cached_gpio; +}; + +/* + * struct aw9523_pinmux - Pin mux params + * @name: Name of the mux + * @grps: Groups of the mux + * @num_grps: Number of groups (sizeof array grps) + */ +struct aw9523_pinmux { + const char *name; + const char * const *grps; + const u8 num_grps; +}; + +/* + * struct aw9523 - Main driver structure + * @dev: device handle + * @regmap: regmap handle for current device + * @i2c_lock: Mutex lock for i2c operations + * @reset_gpio: Hardware reset (RSTN) signal GPIO + * @vio_vreg: VCC regulator (Optional) + * @pctl: pinctrl handle for current device + * @gpio: structure holding gpiochip params + * @irq: Interrupt controller structure + */ +struct aw9523 { + struct device *dev; + struct regmap *regmap; + struct mutex i2c_lock; + struct gpio_desc *reset_gpio; + struct regulator *vio_vreg; + struct pinctrl_dev *pctl; + struct gpio_chip gpio; + struct aw9523_irq *irq; +}; + +static const struct pinctrl_pin_desc aw9523_pins[] = { + /* Port 0 */ + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + + /* Port 1 */ + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), +}; + +static int aw9523_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(aw9523_pins); +} + +static const char *aw9523_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return aw9523_pins[selector].name; +} + +static int aw9523_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = &aw9523_pins[selector].number; + *num_pins = 1; + return 0; +} + +static const struct pinctrl_ops aw9523_pinctrl_ops = { + .get_groups_count = aw9523_pinctrl_get_groups_count, + .get_group_pins = aw9523_pinctrl_get_group_pins, + .get_group_name = aw9523_pinctrl_get_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static const char * const gpio_pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15" +}; + +/* Warning: Do NOT reorder this array */ +static const struct aw9523_pinmux aw9523_pmx[] = { + { + .name = "pwm", + .grps = gpio_pwm_groups, + .num_grps = ARRAY_SIZE(gpio_pwm_groups), + }, + { + .name = "gpio", + .grps = gpio_pwm_groups, + .num_grps = ARRAY_SIZE(gpio_pwm_groups), + }, +}; + +static int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl) +{ + return ARRAY_SIZE(aw9523_pmx); +} + +static const char *aw9523_pmx_get_fname(struct pinctrl_dev *pctl, + unsigned int sel) +{ + return aw9523_pmx[sel].name; +} + +static int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = aw9523_pmx[sel].grps; + *num_groups = aw9523_pmx[sel].num_grps; + return 0; +} + +static int aw9523_pmx_set_mux(struct pinctrl_dev *pctl, unsigned int fsel, + unsigned int grp) +{ + struct aw9523 *awi = pinctrl_dev_get_drvdata(pctl); + int ret, pin = aw9523_pins[grp].number % AW9523_PINS_PER_PORT; + + if (fsel >= ARRAY_SIZE(aw9523_pmx)) + return -EINVAL; + + /* + * This maps directly to the aw9523_pmx array: programming a + * high bit means "gpio" and a low bit means "pwm". + */ + mutex_lock(&awi->i2c_lock); + ret = regmap_update_bits(awi->regmap, AW9523_REG_PORT_MODE(pin), + BIT(pin), (fsel ? BIT(pin) : 0)); + mutex_unlock(&awi->i2c_lock); + return ret; +} + +static const struct pinmux_ops aw9523_pinmux_ops = { + .get_functions_count = aw9523_pmx_get_funcs_count, + .get_function_name = aw9523_pmx_get_fname, + .get_function_groups = aw9523_pmx_get_groups, + .set_mux = aw9523_pmx_set_mux, +}; + +static int aw9523_pcfg_param_to_reg(enum pin_config_param pcp, int pin, u8 *r) +{ + u8 reg; + + switch (pcp) { + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + reg = AW9523_REG_IN_STATE(pin); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + reg = AW9523_REG_GCR; + break; + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: + reg = AW9523_REG_CONF_STATE(pin); + break; + case PIN_CONFIG_OUTPUT: + reg = AW9523_REG_OUT_STATE(pin); + break; + default: + return -ENOTSUPP; + } + *r = reg; + + return 0; +} + +static int aw9523_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + int regbit = pin % AW9523_PINS_PER_PORT; + unsigned int val; + u8 reg; + int rc; + + rc = aw9523_pcfg_param_to_reg(param, pin, ®); + if (rc) + return rc; + + mutex_lock(&awi->i2c_lock); + rc = regmap_read(awi->regmap, reg, &val); + mutex_unlock(&awi->i2c_lock); + if (rc) + return rc; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + val &= BIT(regbit); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_OUTPUT_ENABLE: + val &= BIT(regbit); + val = !val; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (pin >= AW9523_PINS_PER_PORT) + val = 0; + else + val = !FIELD_GET(AW9523_GCR_GPOMD_MASK, val); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (pin >= AW9523_PINS_PER_PORT) + val = 1; + else + val = FIELD_GET(AW9523_GCR_GPOMD_MASK, val); + break; + default: + return -ENOTSUPP; + } + if (val < 1) + return -EINVAL; + + *config = pinconf_to_config_packed(param, !!val); + + return rc; +} + +static int aw9523_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + int regbit = pin % AW9523_PINS_PER_PORT; + u32 arg; + u8 reg; + unsigned int mask, val; + int i, rc; + + mutex_lock(&awi->i2c_lock); + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + rc = aw9523_pcfg_param_to_reg(param, pin, ®); + if (rc) + goto end; + + switch (param) { + case PIN_CONFIG_OUTPUT: + /* First, enable pin output */ + rc = regmap_update_bits(awi->regmap, + AW9523_REG_CONF_STATE(pin), + BIT(regbit), 0); + if (rc) + goto end; + + /* Then, fall through to config output level */ + fallthrough; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = !arg; + fallthrough; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_INPUT_ENABLE: + mask = BIT(regbit); + val = arg ? BIT(regbit) : 0; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + /* Open-Drain is supported only on port 0 */ + if (pin >= AW9523_PINS_PER_PORT) { + rc = -ENOTSUPP; + goto end; + } + mask = AW9523_GCR_GPOMD_MASK; + val = 0; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + /* Port 1 is always Push-Pull */ + if (pin >= AW9523_PINS_PER_PORT) { + mask = 0; + val = 0; + continue; + } + mask = AW9523_GCR_GPOMD_MASK; + val = AW9523_GCR_GPOMD_MASK; + break; + default: + rc = -ENOTSUPP; + goto end; + } + + rc = regmap_update_bits(awi->regmap, reg, mask, val); + if (rc) + goto end; + } +end: + mutex_unlock(&awi->i2c_lock); + return rc; +} + +static const struct pinconf_ops aw9523_pinconf_ops = { + .pin_config_get = aw9523_pconf_get, + .pin_config_set = aw9523_pconf_set, + .is_generic = true, +}; + +/* + * aw9523_get_pin_direction - Get pin direction + * @regmap: Regmap structure + * @pin: gpiolib pin number + * @n: pin index in port register + * + * Return: Pin direction for success or negative number for error + */ +static int aw9523_get_pin_direction(struct regmap *regmap, u8 pin, u8 n) +{ + int ret; + + ret = regmap_test_bits(regmap, AW9523_REG_CONF_STATE(pin), BIT(n)); + if (ret < 0) + return ret; + + return ret ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +/* + * aw9523_get_port_state - Get input or output state for entire port + * @regmap: Regmap structure + * @pin: gpiolib pin number + * @regbit: hw pin index, used to retrieve port number + * @state: returned port state + * + * Return: Zero for success or negative number for error + */ +static int aw9523_get_port_state(struct regmap *regmap, u8 pin, + u8 regbit, unsigned int *state) +{ + u8 reg; + int dir; + + dir = aw9523_get_pin_direction(regmap, pin, regbit); + if (dir < 0) + return dir; + + if (dir == GPIO_LINE_DIRECTION_IN) + reg = AW9523_REG_IN_STATE(pin); + else + reg = AW9523_REG_OUT_STATE(pin); + + return regmap_read(regmap, reg, state); +} + +static int aw9523_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + switch (type) { + case IRQ_TYPE_NONE: + case IRQ_TYPE_EDGE_BOTH: + return 0; + default: + return -EINVAL; + }; +} + +/* + * aw9523_irq_mask - Mask interrupt + * @d: irq data + * + * Sets which interrupt to mask in the bitmap; + * The interrupt will be masked when unlocking the irq bus. + */ +static void aw9523_irq_mask(struct irq_data *d) +{ + struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int n = d->hwirq % AW9523_PINS_PER_PORT; + + regmap_update_bits(awi->regmap, + AW9523_REG_INTR_DIS(d->hwirq), + BIT(n), BIT(n)); +} + +/* + * aw9523_irq_unmask - Unmask interrupt + * @d: irq data + * + * Sets which interrupt to unmask in the bitmap; + * The interrupt will be masked when unlocking the irq bus. + */ +static void aw9523_irq_unmask(struct irq_data *d) +{ + struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int n = d->hwirq % AW9523_PINS_PER_PORT; + + regmap_update_bits(awi->regmap, + AW9523_REG_INTR_DIS(d->hwirq), + BIT(n), 0); +} + +static irqreturn_t aw9523_irq_thread_func(int irq, void *dev_id) +{ + struct aw9523 *awi = (struct aw9523 *)dev_id; + unsigned long n, val = 0; + unsigned long changed_gpio; + unsigned int tmp, port_pin, i, ret; + + for (i = 0; i < AW9523_NUM_PORTS; i++) { + port_pin = i * AW9523_PINS_PER_PORT; + ret = regmap_read(awi->regmap, + AW9523_REG_IN_STATE(port_pin), + &tmp); + if (ret) + return ret; + val |= (u8)tmp << (i * 8); + } + + /* Handle GPIO input release interrupt as well */ + changed_gpio = awi->irq->cached_gpio ^ val; + awi->irq->cached_gpio = val; + + /* + * To avoid up to four *slow* i2c reads from any driver hooked + * up to our interrupts, just check for the irq_find_mapping + * result: if the interrupt is not mapped, then we don't want + * to care about it. + */ + for_each_set_bit(n, &changed_gpio, awi->gpio.ngpio) { + tmp = irq_find_mapping(awi->gpio.irq.domain, n); + if (tmp <= 0) + continue; + handle_nested_irq(tmp); + } + + return IRQ_HANDLED; +} + +/* + * aw9523_irq_bus_lock - Grab lock for interrupt operation + * @d: irq data + */ +static void aw9523_irq_bus_lock(struct irq_data *d) +{ + struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + + mutex_lock(&awi->irq->lock); + regcache_cache_only(awi->regmap, true); +} + +/* + * aw9523_irq_bus_sync_unlock - Synchronize state and unlock + * @d: irq data + * + * Writes the interrupt mask bits (found in the bit map) to the + * hardware, then unlocks the bus. + */ +static void aw9523_irq_bus_sync_unlock(struct irq_data *d) +{ + struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + + regcache_cache_only(awi->regmap, false); + regcache_sync(awi->regmap); + mutex_unlock(&awi->irq->lock); +} + +static int aw9523_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 regbit = offset % AW9523_PINS_PER_PORT; + int ret; + + mutex_lock(&awi->i2c_lock); + ret = aw9523_get_pin_direction(awi->regmap, offset, regbit); + mutex_unlock(&awi->i2c_lock); + + return ret; +} + +static int aw9523_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 regbit = offset % AW9523_PINS_PER_PORT; + unsigned int val; + int ret; + + mutex_lock(&awi->i2c_lock); + ret = aw9523_get_port_state(awi->regmap, offset, regbit, &val); + mutex_unlock(&awi->i2c_lock); + if (ret) + return ret; + + return !!(val & BIT(regbit)); +} + +/** + * _aw9523_gpio_get_multiple - Get I/O state for an entire port + * @regmap: Regmap structure + * @pin: gpiolib pin number + * @regbit: hw pin index, used to retrieve port number + * @state: returned port I/O state + * + * Return: Zero for success or negative number for error + */ +static int _aw9523_gpio_get_multiple(struct aw9523 *awi, u8 regbit, + u8 *state, u8 mask) +{ + u32 dir_in, val; + u8 m; + int ret; + + /* Registers are 8-bits wide */ + ret = regmap_read(awi->regmap, AW9523_REG_CONF_STATE(regbit), &dir_in); + if (ret) + return ret; + *state = 0; + + m = mask & dir_in; + if (m) { + ret = regmap_read(awi->regmap, AW9523_REG_IN_STATE(regbit), + &val); + if (ret) + return ret; + *state |= (u8)val & m; + } + + m = mask & ~dir_in; + if (m) { + ret = regmap_read(awi->regmap, AW9523_REG_OUT_STATE(regbit), + &val); + if (ret) + return ret; + *state |= (u8)val & m; + } + + return 0; +} + +static int aw9523_gpio_get_multiple(struct gpio_chip *chip, + unsigned long *mask, + unsigned long *bits) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 m, state = 0; + int ret; + + mutex_lock(&awi->i2c_lock); + + /* Port 0 (gpio 0-7) */ + m = *mask & U8_MAX; + if (m) { + ret = _aw9523_gpio_get_multiple(awi, 0, &state, m); + if (ret) + goto out; + } + *bits = state; + + /* Port 1 (gpio 8-15) */ + m = (*mask >> 8) & U8_MAX; + if (m) { + ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT, + &state, m); + if (ret) + goto out; + + *bits |= (state << 8); + } +out: + mutex_unlock(&awi->i2c_lock); + return ret; +} + +static void aw9523_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, + unsigned long *bits) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 mask_lo, mask_hi, bits_lo, bits_hi; + unsigned int reg; + int ret = 0; + + mask_lo = *mask & U8_MAX; + mask_hi = (*mask >> 8) & U8_MAX; + mutex_lock(&awi->i2c_lock); + if (mask_hi) { + reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT); + bits_hi = (*bits >> 8) & U8_MAX; + + ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi); + if (ret) { + dev_warn(awi->dev, "Cannot write port1 out level\n"); + goto out; + } + } + if (mask_lo) { + reg = AW9523_REG_OUT_STATE(0); + bits_lo = *bits & U8_MAX; + ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo); + if (ret) + dev_warn(awi->dev, "Cannot write port0 out level\n"); + } +out: + mutex_unlock(&awi->i2c_lock); +} + +static void aw9523_gpio_set(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 regbit = offset % AW9523_PINS_PER_PORT; + + mutex_lock(&awi->i2c_lock); + regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset), + BIT(regbit), value ? BIT(regbit) : 0); + mutex_unlock(&awi->i2c_lock); +} + + +static int aw9523_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 regbit = offset % AW9523_PINS_PER_PORT; + int ret; + + mutex_lock(&awi->i2c_lock); + ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset), + BIT(regbit), BIT(regbit)); + mutex_unlock(&awi->i2c_lock); + + return ret; +} + +static int aw9523_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct aw9523 *awi = gpiochip_get_data(chip); + u8 regbit = offset % AW9523_PINS_PER_PORT; + int ret; + + mutex_lock(&awi->i2c_lock); + ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset), + BIT(regbit), value ? BIT(regbit) : 0); + if (ret) + goto end; + + ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset), + BIT(regbit), 0); +end: + mutex_unlock(&awi->i2c_lock); + return ret; +} + +static int aw9523_drive_reset_gpio(struct aw9523 *awi) +{ + unsigned int chip_id; + int ret; + + /* + * If the chip is already configured for any reason, then we + * will probably succeed in sending the soft reset signal to + * the hardware through I2C: this operation takes less time + * compared to a full HW reset and it gives the same results. + */ + ret = regmap_write(awi->regmap, AW9523_REG_SOFT_RESET, 0); + if (ret == 0) + goto done; + + dev_dbg(awi->dev, "Cannot execute soft reset: trying hard reset\n"); + ret = gpiod_direction_output(awi->reset_gpio, 0); + if (ret) + return ret; + + /* The reset pulse has to be longer than 20uS due to deglitch */ + usleep_range(AW9523_HW_RESET_US, AW9523_HW_RESET_US + 1); + + ret = gpiod_direction_output(awi->reset_gpio, 1); + if (ret) + return ret; +done: + /* The HW needs at least 1uS to reliably recover after reset */ + usleep_range(AW9523_HW_RESET_RECOVERY_US, + AW9523_HW_RESET_RECOVERY_US + 1); + + /* Check the ChipID */ + ret = regmap_read(awi->regmap, AW9523_REG_CHIPID, &chip_id); + if (ret) { + dev_err(awi->dev, "Cannot read Chip ID: %d\n", ret); + return ret; + } + if (chip_id != AW9523_VAL_EXPECTED_CHIPID) { + dev_err(awi->dev, "Bad ChipID; read 0x%x, expected 0x%x\n", + chip_id, AW9523_VAL_EXPECTED_CHIPID); + return -EINVAL; + } + + return 0; +} + +static int aw9523_hw_reset(struct aw9523 *awi) +{ + int ret, max_retries = 2; + + /* Sometimes the chip needs more than one reset cycle */ + do { + ret = aw9523_drive_reset_gpio(awi); + if (ret == 0) + break; + max_retries--; + } while (max_retries); + + return ret; +} + +static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins) +{ + struct device *dev = awi->dev; + struct gpio_chip *gpiochip = &awi->gpio; + + gpiochip->label = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); + if (!gpiochip->label) + return -ENOMEM; + + gpiochip->base = -1; + gpiochip->ngpio = npins; + gpiochip->get_direction = aw9523_gpio_get_direction; + gpiochip->direction_input = aw9523_direction_input; + gpiochip->direction_output = aw9523_direction_output; + gpiochip->get = aw9523_gpio_get; + gpiochip->get_multiple = aw9523_gpio_get_multiple; + gpiochip->set = aw9523_gpio_set; + gpiochip->set_multiple = aw9523_gpio_set_multiple; + gpiochip->set_config = gpiochip_generic_config; + gpiochip->parent = dev; + gpiochip->of_node = dev->of_node; + gpiochip->owner = THIS_MODULE; + gpiochip->can_sleep = false; + + return 0; +} + +static int aw9523_init_irq(struct aw9523 *awi, int irq) +{ + struct device *dev = awi->dev; + struct gpio_irq_chip *gpioirq; + struct irq_chip *irqchip; + int ret; + + if (!device_property_read_bool(dev, "interrupt-controller")) + return 0; + + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); + if (!irqchip) + return -ENOMEM; + + awi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL); + if (!awi->irq) + return -ENOMEM; + + irqchip->name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); + if (!irqchip->name) + return -ENOMEM; + + irqchip->irq_mask = aw9523_irq_mask; + irqchip->irq_unmask = aw9523_irq_unmask; + irqchip->irq_bus_lock = aw9523_irq_bus_lock; + irqchip->irq_bus_sync_unlock = aw9523_irq_bus_sync_unlock; + irqchip->irq_set_type = aw9523_gpio_irq_type; + awi->irq->irqchip = irqchip; + mutex_init(&awi->irq->lock); + + ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func, + IRQF_ONESHOT, dev_name(dev), awi); + if (ret) { + dev_err(dev, "Failed to request irq %d\n", irq); + return ret; + } + + gpioirq = &awi->gpio.irq; + gpioirq->chip = irqchip; + gpioirq->parent_handler = NULL; + gpioirq->num_parents = 0; + gpioirq->parents = NULL; + gpioirq->default_type = IRQ_TYPE_LEVEL_MASK; + gpioirq->handler = handle_simple_irq; + gpioirq->threaded = true; + gpioirq->first = 0; + + return 0; +} + +static bool aw9523_is_reg_hole(unsigned int reg) +{ + return (reg > AW9523_REG_PORT_MODE(AW9523_PINS_PER_PORT) && + reg < AW9523_REG_SOFT_RESET) || + (reg > AW9523_REG_INTR_DIS(AW9523_PINS_PER_PORT) && + reg < AW9523_REG_CHIPID); +} + +static bool aw9523_readable_reg(struct device *dev, unsigned int reg) +{ + /* All available registers (minus holes) can be read */ + return !aw9523_is_reg_hole(reg); +} + +static bool aw9523_volatile_reg(struct device *dev, unsigned int reg) +{ + return aw9523_is_reg_hole(reg) || + reg == AW9523_REG_IN_STATE(0) || + reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT) || + reg == AW9523_REG_CHIPID || + reg == AW9523_REG_SOFT_RESET; +} + +static bool aw9523_writeable_reg(struct device *dev, unsigned int reg) +{ + return !aw9523_is_reg_hole(reg) && reg != AW9523_REG_CHIPID; +} + +static bool aw9523_precious_reg(struct device *dev, unsigned int reg) +{ + /* Reading AW9523_REG_IN_STATE clears interrupt status */ + return aw9523_is_reg_hole(reg) || + reg == AW9523_REG_IN_STATE(0) || + reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT); +} + +static const struct regmap_config aw9523_regmap = { + .reg_bits = 8, + .val_bits = 8, + .reg_stride = 1, + + .precious_reg = aw9523_precious_reg, + .readable_reg = aw9523_readable_reg, + .volatile_reg = aw9523_volatile_reg, + .writeable_reg = aw9523_writeable_reg, + + .cache_type = REGCACHE_FLAT, + .disable_locking = true, + + .num_reg_defaults_raw = AW9523_REG_SOFT_RESET, +}; + +static int aw9523_hw_init(struct aw9523 *awi) +{ + u8 p1_pin = AW9523_PINS_PER_PORT; + unsigned int val; + int ret; + + /* No register caching during initialization */ + regcache_cache_bypass(awi->regmap, true); + + /* Bring up the chip */ + ret = aw9523_hw_reset(awi); + if (ret) { + dev_err(awi->dev, "HW Reset failed: %d\n", ret); + return ret; + } + + /* + * This is the expected chip and it is running: it's time to + * set a safe default configuration in case the user doesn't + * configure (all of the available) pins in this chip. + * P.S.: The writes order doesn't matter. + */ + + /* Set all pins as GPIO */ + ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(0), U8_MAX); + if (ret) + return ret; + ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(p1_pin), U8_MAX); + if (ret) + return ret; + + /* Set Open-Drain mode on Port 0 (Port 1 is always P-P) */ + ret = regmap_write(awi->regmap, AW9523_REG_GCR, 0); + if (ret) + return ret; + + /* Set all pins as inputs */ + ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(0), U8_MAX); + if (ret) + return ret; + ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(p1_pin), U8_MAX); + if (ret) + return ret; + + /* Disable all interrupts to avoid unreasoned wakeups */ + ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(0), U8_MAX); + if (ret) + return ret; + ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(p1_pin), U8_MAX); + if (ret) + return ret; + + /* Clear setup-generated interrupts by performing a port state read */ + ret = aw9523_get_port_state(awi->regmap, 0, 0, &val); + if (ret) + return ret; + ret = aw9523_get_port_state(awi->regmap, p1_pin, 0, &val); + if (ret) + return ret; + + /* Everything went fine: activate and reinitialize register cache */ + regcache_cache_bypass(awi->regmap, false); + return regmap_reinit_cache(awi->regmap, &aw9523_regmap); +} + +static int aw9523_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct pinctrl_desc *pdesc; + struct aw9523 *awi; + int ret; + + awi = devm_kzalloc(dev, sizeof(*awi), GFP_KERNEL); + if (!awi) + return -ENOMEM; + + i2c_set_clientdata(client, awi); + + awi->dev = dev; + awi->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(awi->reset_gpio)) + return PTR_ERR(awi->reset_gpio); + gpiod_set_consumer_name(awi->reset_gpio, "aw9523 reset"); + + awi->regmap = devm_regmap_init_i2c(client, &aw9523_regmap); + if (IS_ERR(awi->regmap)) + return PTR_ERR(awi->regmap); + + awi->vio_vreg = devm_regulator_get_optional(dev, "vio"); + if (IS_ERR(awi->vio_vreg)) { + if (PTR_ERR(awi->vio_vreg) == -EPROBE_DEFER) + return -EPROBE_DEFER; + awi->vio_vreg = NULL; + } else { + ret = regulator_enable(awi->vio_vreg); + if (ret) + return ret; + } + + mutex_init(&awi->i2c_lock); + lockdep_set_subclass(&awi->i2c_lock, + i2c_adapter_depth(client->adapter)); + + pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL); + if (!pdesc) + return -ENOMEM; + + ret = aw9523_hw_init(awi); + if (ret) + goto err_disable_vregs; + + pdesc->name = dev_name(dev); + pdesc->owner = THIS_MODULE; + pdesc->pctlops = &aw9523_pinctrl_ops; + pdesc->pmxops = &aw9523_pinmux_ops; + pdesc->confops = &aw9523_pinconf_ops; + pdesc->pins = aw9523_pins; + pdesc->npins = ARRAY_SIZE(aw9523_pins); + + ret = aw9523_init_gpiochip(awi, pdesc->npins); + if (ret) + goto err_disable_vregs; + + if (client->irq) { + ret = aw9523_init_irq(awi, client->irq); + if (ret) + goto err_disable_vregs; + } + + awi->pctl = devm_pinctrl_register(dev, pdesc, awi); + if (IS_ERR(awi->pctl)) { + ret = PTR_ERR(awi->pctl); + dev_err(dev, "Cannot register pinctrl: %d", ret); + goto err_disable_vregs; + } + + ret = devm_gpiochip_add_data(dev, &awi->gpio, awi); + if (ret) + goto err_disable_vregs; + + return ret; + +err_disable_vregs: + if (awi->vio_vreg) + regulator_disable(awi->vio_vreg); + mutex_destroy(&awi->i2c_lock); + return ret; +} + +static int aw9523_remove(struct i2c_client *client) +{ + struct aw9523 *awi = i2c_get_clientdata(client); + int ret; + + if (!awi) + return 0; + + /* + * If the chip VIO is connected to a regulator that we can turn + * off, life is easy... otherwise, reinitialize the chip and + * set the pins to hardware defaults before removing the driver + * to leave it in a clean, safe and predictable state. + */ + if (awi->vio_vreg) { + regulator_disable(awi->vio_vreg); + } else { + mutex_lock(&awi->i2c_lock); + ret = aw9523_hw_init(awi); + mutex_unlock(&awi->i2c_lock); + if (ret) + return ret; + } + + mutex_destroy(&awi->i2c_lock); + return 0; +} + +static const struct i2c_device_id aw9523_i2c_id_table[] = { + { "aw9523_i2c", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table); + +static const struct of_device_id of_aw9523_i2c_match[] = { + { .compatible = "awinic,aw9523-pinctrl", }, +}; +MODULE_DEVICE_TABLE(of, of_aw9523_i2c_match); + +static struct i2c_driver aw9523_driver = { + .driver = { + .name = "aw9523-pinctrl", + .of_match_table = of_aw9523_i2c_match, + }, + .probe = aw9523_probe, + .remove = aw9523_remove, + .id_table = aw9523_i2c_id_table, +}; +module_i2c_driver(aw9523_driver); + +MODULE_DESCRIPTION("Awinic AW9523 I2C GPIO Expander driver"); +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:aw9523"); From bbe5a5b1a1e80a59624870ad8b8b2658fe872e5f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Dec 2020 14:54:10 +0100 Subject: [PATCH 087/174] dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver. Signed-off-by: AngeloGioacchino Del Regno --- .../pinctrl/awinic,aw9523-pinctrl.yaml | 139 ++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml new file mode 100644 index 000000000000..640d4d7e4cab --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW9523/AW9523B I2C GPIO Expander + +maintainers: + - AngeloGioacchino Del Regno + +description: | + The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function + I/O, 256 steps PWM mode and interrupt support. + +properties: + compatible: + const: awinic,aw9523-pinctrl + + reg: + maxItems: 1 + + '#gpio-cells': + description: | + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Specifies the INTN pin IRQ. + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + reset-gpios: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. + items: + pattern: "^gpio([0-9]|1[0-5])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the + specified pins. + + enum: [ gpio, pwm ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-open-drain: true + drive-push-pull: true + input-enable: true + input-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + # Example configuration to drive pins for a keyboard matrix + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + aw9523: gpio-expander@58 { + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + input-disable; + output-low; + }; + + keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + bias-pull-up; + drive-open-drain; + input-enable; + }; + }; + }; From d9db298685d44f108d24c463ff7a5e014b5b82f4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Dec 2020 15:44:37 +0100 Subject: [PATCH 088/174] dt-bindings: input: Add binding for gpio-fastmatrix-keyboard Add documentation for the gpio-fastmatrix-keyboard driver. Signed-off-by: AngeloGioacchino Del Regno (JAMI: merge with e7aa905a for 5.17) --- .../input/gpio-fastmatrix-keyboard.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/gpio-fastmatrix-keyboard.yaml diff --git a/Documentation/devicetree/bindings/input/gpio-fastmatrix-keyboard.yaml b/Documentation/devicetree/bindings/input/gpio-fastmatrix-keyboard.yaml new file mode 100644 index 000000000000..3830997016c0 --- /dev/null +++ b/Documentation/devicetree/bindings/input/gpio-fastmatrix-keyboard.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/gpio-fastmatrix-keyboard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fast modern GPIO-driven keyboard/keypad matrix driver binding + +maintainers: + - AngeloGioacchino Del Regno + +description: | + A simple common binding for matrix-connected keyboards/keypads, targeted at + defining the keys in the scope of linux key codes since that is a stable and + standardized interface at this time. + This driver uses the GPIOD API in order to support setting (and reading) an + entire array of GPIOs which is very fast (if the controller supports it) and + a requirement to support full keyboard matrices on slow external GPIO I2C + expanders, but also a great latency enhancement for faster GPIO controllers. + +allOf: + - $ref: input.yaml# + +properties: + compatible: + const: gpio-fastmatrix-keyboard + + label: + description: Descriptive name of the key. + + linux,keymap: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of packed 1-cell entries containing the equivalent of row, + column and linux key-code as specified in dt-bindings/input/input.h + + autorescan-ms: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Activates auto-rescanning of the matrix after receiving and processing + an event for quirky hardware that won't re-send interrupts on fast-press, + fast-depress, or multiple keys pressed events. + This time is expressed in milliseconds; if not specified, the feature is + disabled. + + col-scan-delay-us: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time to wait in microseconds for scan after activating a column. + If not specified, the default is 0 (no wait). + + debounce-delay-ms: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Matrix button debouncing interval time in milliseconds. + If not specified, debouncing is disabled. + + drive-inactive-cols: + type: boolean + description: Keep direction of inactive columns as output + + col-gpios: + minItems: 2 + maxItems: 20 + + keypad,num-rows: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of row lines connected to the keypad controller. + + keypad,num-columns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of column lines connected to the keypad controller. + + pinctrl-0: + maxItems: 1 + + pinctrl-names: + maxItems: 1 + + row-gpios: + minItems: 2 + maxItems: 20 + +required: + - compatible + - row-gpios + - col-gpios + - linux,keymap + - keypad,num-rows + - keypad,num-columns + +additionalProperties: true + +examples: + - | + #include + #include + + gpio-keyboard { + compatible = "gpio-fastmatrix-keyboard"; + label = "Keyboard over I2C Expander"; + row-gpios = + <&gpioext0 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 4 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 6 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>, + <&gpioext0 7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + col-gpios = + <&gpioext0 8 GPIO_ACTIVE_LOW>, + <&gpioext0 9 GPIO_ACTIVE_LOW>, + <&gpioext0 10 GPIO_ACTIVE_LOW>, + <&gpioext0 11 GPIO_ACTIVE_LOW>, + <&gpioext0 12 GPIO_ACTIVE_LOW>, + <&gpioext0 13 GPIO_ACTIVE_LOW>, + <&gpioext0 14 GPIO_ACTIVE_LOW>, + <&gpioext0 15 GPIO_ACTIVE_LOW>; + + linux,keymap = < + MATRIX_KEY(0, 0, KEY_F1) MATRIX_KEY(1, 0, KEY_H) + MATRIX_KEY(2, 0, KEY_B) MATRIX_KEY(3, 0, KEY_7) + /* ... */ + >; + + keypad,num-rows = <8>; + keypad,num-columns = <8>; + }; From a7333bdc359d32a8f2f94f0d697b56898e2a0005 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 9 Dec 2020 19:27:45 +0100 Subject: [PATCH 089/174] input: keyboard: Add Fast GPIO-driven keyboard/keypad matrix driver This driver is a reimplementation of matrix_keyboard, on which it is heavily based: the former was made back in 2009 and then lightly updated in 2012 to add some support for device-tree / OF. It turns out that this is not enough, nor OF is fully supported, as the global (or "clustered") interrupt is never probed, nor it made usage of the GPIOD API which, nowadays, really simplifies the job - but not only: it also provides means to set GPIO arrays for controllers that are supporting this. The latter is very important when dealing with slow GPIOs such as I2C and/or SPI expanders (and, again, not only); by using the new APIs everything fits the new systems, from simplifications of the probe/remove functions to opening possibility of using expanders to drive key matrices with or without protection diodes. But then, why wasn't the old matrix_keyboard driver modified instead of creating a new one? The problem there is that the old driver is made to support the old platform_device style and it's currently still being used by some PXA boards that are not (yet?) ported to device-tree, so it would be impossible to modernize it for good, which means that to support GPIOD (which is - really - required for the aforementioned reasons) and to fully support DT it would be necessary to wrap the old GPIO API around the new GPIOD one, creating overhead and also probably unnecessary memory usage, other than a very big driver which, at least on embedded devices (having limited resources), would be simply bad. Leaving the fact that I haven't got any old board so it's impossible for me to analyze and optimize for them. Since 98% of the users of the old driver are infact platforms that have been ported to (or are born with) DT, the introduction of a new driver that's purely made for them seemed to be the best choice, also because the expectations are (I think) that all of the old ARM-based boards will be ported to DT anyway, which will actually deprecate the good old matrix_keyboard driver. Signed-off-by: AngeloGioacchino Del Regno --- drivers/input/keyboard/Kconfig | 13 + drivers/input/keyboard/Makefile | 1 + drivers/input/keyboard/gpio_fastmatrix.c | 528 +++++++++++++++++++++++ 3 files changed, 542 insertions(+) create mode 100644 drivers/input/keyboard/gpio_fastmatrix.c diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 9417ee0b1eff..28c756ed65f0 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -242,6 +242,19 @@ config KEYBOARD_GPIO To compile this driver as a module, choose M here: the module will be called gpio_keys. +config KEYBOARD_GPIO_FASTMATRIX + tristate "GPIO Keyboard" + depends on GPIOLIB + select INPUT_MATRIXKMAP + help + This driver implements support for matrix keypads and/or + keyboards connected directly to GPIO pins of a CPU, made + to also perform with slow I2C GPIO expanders and even + on matrices with no protection diodes. + + To compile this driver as a module, choose M here: the + module will be called gpio_fastmatrix + config KEYBOARD_GPIO_POLLED tristate "Polled GPIO buttons" depends on GPIOLIB diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index e3c8648f834e..f731862251f1 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_KEYBOARD_DLINK_DIR685) += dlink-dir685-touchkeys.o obj-$(CONFIG_KEYBOARD_EP93XX) += ep93xx_keypad.o obj-$(CONFIG_KEYBOARD_GOLDFISH_EVENTS) += goldfish_events.o obj-$(CONFIG_KEYBOARD_GPIO) += gpio_keys.o +obj-$(CONFIG_KEYBOARD_GPIO_FASTMATRIX) += gpio_fastmatrix.o obj-$(CONFIG_KEYBOARD_GPIO_POLLED) += gpio_keys_polled.o obj-$(CONFIG_KEYBOARD_TCA6416) += tca6416-keypad.o obj-$(CONFIG_KEYBOARD_TCA8418) += tca8418_keypad.o diff --git a/drivers/input/keyboard/gpio_fastmatrix.c b/drivers/input/keyboard/gpio_fastmatrix.c new file mode 100644 index 000000000000..ed7e028199e4 --- /dev/null +++ b/drivers/input/keyboard/gpio_fastmatrix.c @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fast GPIO driven keyboard/keypad matrix driver + * + * Copyright (c) 2020 AngeloGioacchino Del Regno + * + * Based on matrix_keypad.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gpio_keyboard { + struct device *dev; + struct input_dev *input_dev; + unsigned int row_shift; + + struct gpio_descs *row_gpios; + struct gpio_descs *col_gpios; + u32 autorescan_ms; + u32 debounce_ms; + u32 col_scan_us; + int clustered_irq; + + DECLARE_BITMAP(disabled_gpios, MATRIX_MAX_ROWS); + + u32 last_key_state[MATRIX_MAX_COLS]; + struct delayed_work work; + struct mutex lock; + + bool drive_inactive_cols; + bool gpio_all_disabled; + bool scan_pending; + bool stopped; +}; + +static int activate_one_column(struct gpio_keyboard *gkb, int col, bool wait) +{ + int ret; + + ret = gpiod_direction_output(gkb->col_gpios->desc[col], 1); + if (ret) + return ret; + if (wait && gkb->col_scan_us) + udelay(gkb->col_scan_us); + return 0; +} + +/* + * NOTE: If drive_inactive_cols is false, then the GPIO has to be put into + * HiZ when de-activated to cause minmal side effect when scanning other + * columns. In that case it is configured here to be input, otherwise it is + * driven with the inactive value. + */ +static int deactivate_one_column(struct gpio_keyboard *gkb, int col) +{ + gpiod_set_value_cansleep(gkb->col_gpios->desc[col], 0); + if (!gkb->drive_inactive_cols) + return gpiod_direction_input(gkb->col_gpios->desc[col]); + return 0; +} + +static int activate_all_cols(struct gpio_keyboard *gkb) +{ + unsigned long val = ULONG_MAX; + int ret, col; + + /* + * Shortcut! If we don't have to set direction, we can use + * the way faster gpiod array setting instead. + */ + if (gkb->drive_inactive_cols) { + return gpiod_set_array_value_cansleep(gkb->col_gpios->ndescs, + gkb->col_gpios->desc, + gkb->col_gpios->info, + &val); + } + + for (col = 0; col < gkb->col_gpios->ndescs; col++) { + ret = activate_one_column(gkb, col, false); + if (ret) + return ret; + } + + return 0; +} + +static int deactivate_all_cols(struct gpio_keyboard *gkb) +{ + unsigned long val = 0; + int col, ret; + + /* + * If the GPIO controller supports setting all pins at once it + * is going to be way faster, otherwise this function will fall + * back to setting all pins one at a time. + */ + ret = gpiod_set_array_value_cansleep(gkb->col_gpios->ndescs, + gkb->col_gpios->desc, + gkb->col_gpios->info, &val); + if (ret) + return ret; + + if (!gkb->drive_inactive_cols) { + for (col = 0; col < gkb->col_gpios->ndescs; col++) + gpiod_direction_input(gkb->col_gpios->desc[col]); + } + return ret; +} + +static void enable_row_irqs(struct gpio_keyboard *gkb) +{ + int i; + + if (gkb->clustered_irq > 0) + enable_irq(gkb->clustered_irq); + else { + for (i = 0; i < gkb->row_gpios->ndescs; i++) + enable_irq(gpiod_to_irq(gkb->row_gpios->desc[i])); + } +} + +static void disable_row_irqs(struct gpio_keyboard *gkb) +{ + int i; + + if (gkb->clustered_irq > 0) + disable_irq_nosync(gkb->clustered_irq); + else { + for (i = 0; i < gkb->row_gpios->ndescs; i++) + disable_irq_nosync(gpiod_to_irq(gkb->row_gpios->desc[i])); + } +} + +/* + * This gets the keys from keyboard and reports it to input subsystem + */ +static void gpio_keyboard_scan(struct work_struct *work) +{ + struct gpio_keyboard *gkb = + container_of(work, struct gpio_keyboard, work.work); + struct input_dev *input_dev = gkb->input_dev; + const unsigned short *keycodes = input_dev->keycode; + u32 *new_state; + unsigned long row_values; + int ret, row, col, code; + u32 keymask = 0; + + new_state = kzalloc(gkb->col_gpios->ndescs * sizeof(*new_state), + GFP_KERNEL); + if (!new_state) + return; + + /* de-activate all columns for scanning */ + deactivate_all_cols(gkb); + + /* assert each column and read the row status out */ + for (col = 0; col < gkb->col_gpios->ndescs; col++) { + activate_one_column(gkb, col, true); + + ret = gpiod_get_array_value_cansleep(gkb->row_gpios->ndescs, + gkb->row_gpios->desc, + gkb->row_gpios->info, + &row_values); + new_state[col] = row_values; + keymask |= new_state[col]; + + if (deactivate_one_column(gkb, col)) { + activate_all_cols(gkb); + goto end; + } + } + + activate_all_cols(gkb); + + for (col = 0; col < gkb->col_gpios->ndescs; col++) { + u32 bits_changed = gkb->last_key_state[col] ^ new_state[col]; + if (bits_changed == 0) + continue; + + for (row = 0; bits_changed; row++, bits_changed >>=1 ) { + if (!(bits_changed & BIT(0))) + continue; + + code = MATRIX_SCAN_CODE(row, col, gkb->row_shift); + input_event(input_dev, EV_MSC, MSC_SCAN, code); + input_report_key(input_dev, keycodes[code], + new_state[col] & (1 << row)); + } + } + input_sync(input_dev); + + memcpy(gkb->last_key_state, new_state, sizeof(gkb->last_key_state)); + kfree(new_state); + + /* Avoid missing key release events on quirky hardware */ + if (gkb->autorescan_ms && keymask) { + queue_delayed_work(system_highpri_wq, &gkb->work, + msecs_to_jiffies(gkb->autorescan_ms)); + return; + } +end: + /* Enable IRQs again */ + mutex_lock(&gkb->lock); + gkb->scan_pending = false; + enable_row_irqs(gkb); + mutex_unlock(&gkb->lock); +} + +static irqreturn_t gpio_keyboard_interrupt(int irq, void *id) +{ + struct gpio_keyboard *gkb = id; + + /* + * See if another IRQ beaten us to it and scheduled the + * scan already. In that case we should not try to + * disable IRQs again. + */ + if (unlikely(gkb->scan_pending || gkb->stopped)) + goto out; + + mutex_lock(&gkb->lock); + + disable_row_irqs(gkb); + gkb->scan_pending = true; + mod_delayed_work(system_highpri_wq, &gkb->work, + msecs_to_jiffies(gkb->debounce_ms)); + +out: + mutex_unlock(&gkb->lock); + return IRQ_HANDLED; +} + +static int gpio_keyboard_start(struct input_dev *dev) +{ + struct gpio_keyboard *gkb = input_get_drvdata(dev); + + gkb->stopped = false; + + /* + * Schedule an immediate key scan to capture current key state; + * columns will be activated and IRQs be enabled after the scan. + */ + schedule_delayed_work(&gkb->work, 0); + + return 0; +} + +static void gpio_keyboard_stop(struct input_dev *dev) +{ + struct gpio_keyboard *gkb = input_get_drvdata(dev); + + mutex_lock(&gkb->lock); + gkb->stopped = true; + mutex_unlock(&gkb->lock); + + flush_delayed_work(&gkb->work); + /* + * gpio_keyboard_scan() will leave IRQs enabled; + * we should disable them now. + */ + disable_row_irqs(gkb); +} + +static void __maybe_unused gpio_keyboard_wakeup_en(struct gpio_keyboard *gkb) +{ + int irq, i; + + if (gkb->clustered_irq > 0) { + if (enable_irq_wake(gkb->clustered_irq) == 0) + gkb->gpio_all_disabled = true; + } else { + + for (i = 0; i < gkb->row_gpios->ndescs; i++) { + if (!test_bit(i, gkb->disabled_gpios)) { + irq = gpiod_to_irq(gkb->row_gpios->desc[i]); + + if (enable_irq_wake(irq) == 0) + __set_bit(i, gkb->disabled_gpios); + } + } + } +} + +static void __maybe_unused gpio_keyboard_wakeup_dis(struct gpio_keyboard *gkb) +{ + int irq, i; + + if (gkb->clustered_irq > 0) { + if (gkb->gpio_all_disabled) { + disable_irq_wake(gkb->clustered_irq); + gkb->gpio_all_disabled = false; + } + } else { + for (i = 0; i < gkb->row_gpios->ndescs; i++) { + if (test_and_clear_bit(i, gkb->disabled_gpios)) { + irq = gpiod_to_irq(gkb->row_gpios->desc[i]); + disable_irq_wake(irq); + } + } + } +} + +static int __maybe_unused gpio_keyboard_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gpio_keyboard *gkb = platform_get_drvdata(pdev); + + gpio_keyboard_stop(gkb->input_dev); + + if (device_may_wakeup(&pdev->dev)) + gpio_keyboard_wakeup_en(gkb); + + return 0; +} + +static int __maybe_unused gpio_keyboard_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gpio_keyboard *gkb = platform_get_drvdata(pdev); + + if (device_may_wakeup(&pdev->dev)) + gpio_keyboard_wakeup_dis(gkb); + + gpio_keyboard_start(gkb->input_dev); + + return 0; +} +static SIMPLE_DEV_PM_OPS(gpio_keyboard_pm_ops, + gpio_keyboard_suspend, gpio_keyboard_resume); + +static int gpio_keyboard_init_gpio(struct platform_device *pdev, + struct gpio_keyboard *gkb) +{ + int i, ret; + + if (gkb->clustered_irq > 0) { + ret = devm_request_threaded_irq(gkb->dev, gkb->clustered_irq, + NULL, gpio_keyboard_interrupt, + IRQF_ONESHOT, "gpio-keyboard", gkb); + if (ret < 0) { + dev_err(&pdev->dev, + "Cannot get IRQ %d\n", gkb->clustered_irq); + return ret; + } + } else { + for (i = 0; i < gkb->row_gpios->ndescs; i++) { + ret = devm_request_threaded_irq( + gkb->dev, + gpiod_to_irq(gkb->row_gpios->desc[i]), + NULL, gpio_keyboard_interrupt, + IRQF_TRIGGER_HIGH | + IRQF_TRIGGER_LOW, + "gpio-keyboard", gkb); + if (ret < 0) { + dev_err(&pdev->dev, + "Cannot get IRQ for gpio%d\n", + desc_to_gpio(gkb->row_gpios->desc[i])); + return ret; + } + } + } + + /* initialized as disabled - enabled by input->open */ + disable_row_irqs(gkb); + return 0; +} + +static int gpio_keyboard_parse_dt(struct gpio_keyboard *gkb) +{ + struct device *dev = gkb->dev; + int rc; + + /* + * Get as GPIOD_ASIS to use the configuration that comes from + * device-tree. Anyway, in many cases the row is configured as + * input, while the column is configured as output-high. + * + * This may vary depending on the hardware. + */ + gkb->row_gpios = devm_gpiod_get_array(dev, "row", GPIOD_ASIS); + if (IS_ERR(gkb->row_gpios)) + return PTR_ERR(gkb->row_gpios); + + gkb->col_gpios = devm_gpiod_get_array(dev, "col", GPIOD_ASIS); + if (IS_ERR(gkb->col_gpios)) + return PTR_ERR(gkb->col_gpios); + + /* All of these additional properties are optional */ + device_property_read_string(dev, "label", &gkb->input_dev->name); + + if (device_property_read_bool(dev, "autorepeat")) + __set_bit(EV_REP, gkb->input_dev->evbit); + + gkb->drive_inactive_cols = + device_property_read_bool(dev, "drive-inactive-cols"); + + rc = device_property_read_u32(dev, "autorescan-ms", + &gkb->autorescan_ms); + if (rc < 0) + gkb->autorescan_ms = 0; + + rc = device_property_read_u32(dev, "debounce-delay-ms", + &gkb->debounce_ms); + if (rc < 0) + gkb->debounce_ms = 0; + + rc = device_property_read_u32(dev, "col-scan-delay-us", + &gkb->col_scan_us); + if (rc < 0) + gkb->col_scan_us = 0; + + return 0; +} + +static int gpio_keyboard_probe(struct platform_device *pdev) +{ + struct gpio_keyboard *gkb; + bool wake; + int irq, ret; + + gkb = devm_kmalloc(&pdev->dev, sizeof(*gkb), GFP_KERNEL); + if (!gkb) + return -ENOMEM; + + gkb->dev = &pdev->dev; + gkb->input_dev = devm_input_allocate_device(&pdev->dev); + if (!gkb->input_dev) + return -ENOMEM; + + ret = gpio_keyboard_parse_dt(gkb); + if (ret) + return ret; + + irq = platform_get_irq_optional(pdev, 0); + gkb->clustered_irq = (irq > 0) ? irq : 0; + gkb->row_shift = get_count_order(gkb->col_gpios->ndescs); + gkb->stopped = true; + INIT_DELAYED_WORK(&gkb->work, gpio_keyboard_scan); + memset(gkb->last_key_state, 0, sizeof(gkb->last_key_state)); + mutex_init(&gkb->lock); + + if (!gkb->input_dev->name) + gkb->input_dev->name = pdev->name; + gkb->input_dev->id.bustype = BUS_HOST; + gkb->input_dev->dev.parent = &pdev->dev; + gkb->input_dev->open = gpio_keyboard_start; + gkb->input_dev->close = gpio_keyboard_stop; + + ret = matrix_keypad_build_keymap(NULL, NULL, + gkb->row_gpios->ndescs, + gkb->col_gpios->ndescs, + NULL, gkb->input_dev); + if (ret) { + dev_err(&pdev->dev, "failed to build keymap\n"); + return ret; + } + + input_set_capability(gkb->input_dev, EV_MSC, MSC_SCAN); + input_set_drvdata(gkb->input_dev, gkb); + + ret = gpio_keyboard_init_gpio(pdev, gkb); + if (ret) + return ret; + + ret = input_register_device(gkb->input_dev); + if (ret) + return ret; + + wake = device_property_read_bool(&pdev->dev, "wakeup-source"); + device_init_wakeup(&pdev->dev, wake); + + platform_set_drvdata(pdev, gkb); + + return 0; +} + +static int gpio_keyboard_remove(struct platform_device *pdev) +{ + struct gpio_keyboard *gkb = platform_get_drvdata(pdev); + int i; + + if (gkb->clustered_irq > 0) { + free_irq(gkb->clustered_irq, gkb); + } else { + for (i = 0; i < gkb->row_gpios->ndescs; i++) + free_irq(gpiod_to_irq(gkb->row_gpios->desc[i]), gkb); + } + input_unregister_device(gkb->input_dev); + + return 0; +} + +static const struct of_device_id gpio_keyboard_dt_match[] = { + { .compatible = "gpio-fastmatrix-keyboard" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpio_keyboard_dt_match); + +static struct platform_driver gpio_keyboard_driver = { + .probe = gpio_keyboard_probe, + .remove = gpio_keyboard_remove, + .driver = { + .name = "gpio-fastmatrix-keyboard", + .pm = &gpio_keyboard_pm_ops, + .of_match_table = gpio_keyboard_dt_match, + }, +}; +module_platform_driver(gpio_keyboard_driver); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("Fast GPIO driven keyboard/keypad matrix driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:gpio-fastmatrix-keyboard"); From c9f802b14004585755eb6bda7cc354de37da1f5c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 20 Jan 2021 15:56:59 +0100 Subject: [PATCH 090/174] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though this driver does actually handle both, if present: add the two in preparation for adding support for SoCs having them. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 31af04afda7d..736f52c742fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -435,6 +435,8 @@ enum dpu_clk_ctrl_type { DPU_CLK_CTRL_RGB3, DPU_CLK_CTRL_DMA0, DPU_CLK_CTRL_DMA1, + DPU_CLK_CTRL_DMA2, + DPU_CLK_CTRL_DMA3, DPU_CLK_CTRL_CURSOR0, DPU_CLK_CTRL_CURSOR1, DPU_CLK_CTRL_INLINE_ROT0_SSPP, From 4b7ee7c6c1d45341165660307c66858453d0111b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 20 Jan 2021 22:33:36 +0100 Subject: [PATCH 091/174] clk: qcom: gcc-msm8998: Set MISC flags, mark hmss/gpu-ahb critical It is being evaluated whether this commit is really needed. DONOTUPSTREAM. (JAMI: fixed up for v5.16-rc1) --- drivers/clk/qcom/gcc-msm8998.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 407e2c5caea4..194565dbe6db 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2080,6 +2080,7 @@ static struct clk_branch gcc_bimc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_gfx_clk", + .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -2220,6 +2221,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .name = "hmss_gpll0_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, }; @@ -3191,6 +3193,14 @@ static int gcc_msm8998_probe(struct platform_device *pdev) if (ret) return ret; + /* + * GCC_MMSS_MISC - GCC_GPU_MISC: + * 1. Disable the GPLL0 active input to MMSS and GPU + * 2. Select clk division 1 (CLK/2) + */ + regmap_write(regmap, 0x0902C, 0x10003); /* MMSS*/ + regmap_write(regmap, 0x71028, 0x10003); /* GPU */ + return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); } From b4524221dc1a59b093208f7f75fce7e77d7a2fc5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Dec 2020 12:35:07 +0100 Subject: [PATCH 092/174] clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks The pixel and byte clocks rate should not be cached, as a VCO shutdown may clear the frequency setup and this may not be set again due to the cached rate being present. This will also be useful when shadow clocks will be implemented in the DSI PLL for seamless timing/resolution switch. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/mmcc-msm8998.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c index c421b1291651..07dfdb9e280d 100644 --- a/drivers/clk/qcom/mmcc-msm8998.c +++ b/drivers/clk/qcom/mmcc-msm8998.c @@ -511,7 +511,7 @@ static struct clk_rcg2 byte0_clk_src = { .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -524,7 +524,7 @@ static struct clk_rcg2 byte1_clk_src = { .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1075,7 +1075,7 @@ static struct clk_rcg2 pclk0_clk_src = { .parent_data = mmss_xo_dsi0pll_dsi1pll, .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, }; @@ -1089,7 +1089,7 @@ static struct clk_rcg2 pclk1_clk_src = { .parent_data = mmss_xo_dsi0pll_dsi1pll, .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, }; From 288e9b5162f1cbff8e4c499248f1b2fd36f19bd7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 27 Jul 2021 12:35:49 +0300 Subject: [PATCH 093/174] drm/msm/dsi_phy_10nm: Fix bad VCO rate calculation --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index d8128f50b0dd..4c02eeaf9ce5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -110,7 +110,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_confi pll_freq = pll->vco_current_rate; - divider = fref * 2; + divider = fref; multiplier = 1 << FRAC_BITS; dec_multiple = div_u64(pll_freq * multiplier, divider); @@ -428,12 +428,11 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, * 1. Assumes prescaler is disabled */ multiplier = 1 << FRAC_BITS; - pll_freq = dec * (ref_clk * 2); - tmp64 = (ref_clk * 2 * frac); + pll_freq = dec * ref_clk; + tmp64 = ref_clk * frac; pll_freq += div_u64(tmp64, multiplier); vco_rate = pll_freq; - pll_10nm->vco_current_rate = vco_rate; DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac); From 29fb6d76d3fce3f361d8d736aea26a6e7d04afa1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 15:57:17 +0200 Subject: [PATCH 094/174] yoshino: Fix too high overheating backlight, enable all wled strings maple --- .../boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts | 5 +++-- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 9e6b06c9c157..3c05fb130899 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -106,7 +106,8 @@ &pmi8998_wled { status = "okay"; - qcom,num-strings = <3>; - qcom,enabled-strings = <0 1 2>; + //qcom,auto-string-detection; + qcom,num-strings = <4>; + qcom,enabled-strings = <0 1 2 3>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index a149a642ea48..8de3d79e7d11 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -484,7 +484,7 @@ &pmi8998_wled { status = "okay"; - default-brightness = <3000>; + default-brightness = <800>; qcom,switching-freq = <800>; qcom,ovp-millivolt = <29600>; qcom,current-boost-limit = <970>; From d54d3d6a7a16a3d6c40ae98a59e874deabd96dde Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 15:42:37 +0200 Subject: [PATCH 095/174] regulator: qcom-labibb: Always disable interrupts during OCP & SC Originally from: cd95ecae --- drivers/regulator/qcom-labibb-regulator.c | 32 +++++++++++++---------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c index 639b71eb41ff..3143e9765029 100644 --- a/drivers/regulator/qcom-labibb-regulator.c +++ b/drivers/regulator/qcom-labibb-regulator.c @@ -279,12 +279,6 @@ static irqreturn_t qcom_labibb_ocp_isr(int irq, void *chip) } vreg->ocp_irq_count++; - /* - * Disable the interrupt temporarily, or it will fire continuously; - * we will re-enable it in the recovery worker function. - */ - disable_irq_nosync(irq); - /* Warn the user for overcurrent */ dev_warn(vreg->dev, "Over-Current interrupt fired!\n"); @@ -304,6 +298,12 @@ end: if (ret) return IRQ_NONE; + /* + * Disable the interrupt temporarily, or it will fire continuously; + * we will re-enable it in the recovery worker function. + */ + disable_irq_nosync(irq); + return IRQ_HANDLED; } @@ -316,8 +316,11 @@ static int qcom_labibb_set_ocp(struct regulator_dev *rdev, int lim, int irq_trig_low, ret; /* - * labibb supports only protection - and does not support setting - * limit. Furthermore, we don't support disabling protection. + * labibb does not support specifying a current limit that is + * special to over-current protection, but only a global one + * that will be used for both current limiting and protection; + * for this reason, we only support enabling the OCP here. + * Furthermore, we don't support disabling protection. */ if (lim || severity != REGULATOR_SEVERITY_PROT || !enable) return -EINVAL; @@ -540,12 +543,6 @@ static irqreturn_t qcom_labibb_sc_isr(int irq, void *chip) /* Warn the user for short circuit */ dev_warn(vreg->dev, "Short-Circuit interrupt fired!\n"); - /* - * Disable the interrupt temporarily, or it will fire continuously; - * we will re-enable it in the recovery worker function. - */ - disable_irq_nosync(irq); - /* Signal out of regulation event to drivers */ regulator_notifier_call_chain(vreg->rdev, REGULATOR_EVENT_REGULATION_OUT, NULL); @@ -553,6 +550,13 @@ static irqreturn_t qcom_labibb_sc_isr(int irq, void *chip) /* Schedule the short-circuit handling as high-priority work */ mod_delayed_work(system_highpri_wq, &vreg->sc_recovery_work, msecs_to_jiffies(SC_RECOVERY_INTERVAL_MS)); + + /* + * Disable the interrupt temporarily, or it will fire continuously; + * we will re-enable it in the recovery worker function. + */ + disable_irq_nosync(irq); + return IRQ_HANDLED; } From 67c05fd70588cc988a489461181fd0f1818ffa91 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 16:35:27 +0200 Subject: [PATCH 096/174] arm64: dts: qcom: msm8998: Add qcom,adreno-smmu compatible --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 471372e573e8..ef61c8a0dcf0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2167,7 +2167,8 @@ }; adreno_smmu: iommu@5040000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2", + "qcom,adreno-smmu"; reg = <0x05040000 0x10000>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, <&gcc GCC_BIMC_GFX_CLK>, From d98aa89de228879726f65e92796a1f377256daa1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 16:48:22 +0200 Subject: [PATCH 097/174] arm64: dts: qcom: msm8998: Add imem pil-reloc-info for firmware loading Firmware loading (mainly the modem) may require IMEM PIL relocation informations: specify this imem region in dt for qcom_pil_info to use it. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index ef61c8a0dcf0..927a3306f242 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3460,6 +3460,21 @@ ; }; + imem@146bf000 { + compatible = "simple-mfd"; + reg = <0x146bf000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0x146bf000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,msm8998-adsp-pas"; reg = <0x17300000 0x4040>; From 18408450a4e125c6f1af0953a8350fd9fe5ec64f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 16:56:45 +0200 Subject: [PATCH 098/174] dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks, required to enable audio functionality on MSM8998. Signed-off-by: AngeloGioacchino Del Regno (JAMI: merge with e122a6a4 for 5.17) --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 72c99e486d86..52fedd30c9aa 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -186,6 +186,8 @@ #define UFS_UNIPRO_CORE_CLK_SRC 177 #define GCC_MMSS_GPLL0_CLK 178 #define HMSS_GPLL0_CLK_SRC 179 +#define HLOS1_VOTE_LPASS_CORE_SMMU_CLK 180 +#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 181 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 @@ -300,5 +302,6 @@ #define GCC_QUSB2PHY_PRIM_BCR 106 #define GCC_QUSB2PHY_SEC_BCR 107 #define GCC_MSS_RESTART 108 +#define GCC_MSS_Q6_BIMC_AXI_CLK 109 #endif From 62de45c5f8e0f9284e4d771379c7418589c2c542 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 16:58:20 +0200 Subject: [PATCH 099/174] clk: qcom: gcc-msm8998: Add q6 bimc and lpass core, adsp SMMU clocks Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related functionality on MSM8998 and APQ variants. Please note that the Q6 and the lpass iommu also need GDSCs to be enabled in order to initialize, which are going to be added in a later commit. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/gcc-msm8998.c | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 194565dbe6db..424371d88a44 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2835,6 +2835,43 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { }, }; +static struct clk_branch hlos1_vote_lpass_core_smmu_clk = { + .halt_reg = 0x7D010, + .clkr = { + .enable_reg = 0x7D010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "hlos1_vote_lpass_core_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { + .halt_reg = 0x7D014, + .clkr = { + .enable_reg = 0x7D014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x8A040, + .clkr = { + .enable_reg = 0x8A040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_mss_q6_bimc_axi_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -3038,6 +3075,9 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &hlos1_vote_lpass_core_smmu_clk.clkr, + [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { From 3c59b21e13e0f2461349afe0108537b895acefc4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 17:01:49 +0200 Subject: [PATCH 100/174] dt-bindings: clock: gcc-msm8998: Add LPASS adsp/core GDSCs definitions Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC as a final step to enable the required clock tree for the lpass iommu and for the audio dsp itself. Signed-off-by: AngeloGioacchino Del Regno --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 52fedd30c9aa..7a0b62b0a856 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -192,6 +192,8 @@ #define PCIE_0_GDSC 0 #define UFS_GDSC 1 #define USB_30_GDSC 2 +#define LPASS_ADSP_GDSC 3 +#define LPASS_CORE_GDSC 4 #define GCC_BLSP1_QUP1_BCR 0 #define GCC_BLSP1_QUP2_BCR 1 From b19351378969f2732de74c3939f60514e87987e4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 17:03:36 +0200 Subject: [PATCH 101/174] clk: qcom: gcc-msm8998: Add LPASS adsp and core GDSCs As a final step to entirely enable the required clock tree for the lpass iommu and audio dsp, add the lpass core/adsp GDSCs. As a side note, it was found out that disabling the lpass core GDSC at any time would cause a system lockup (and reboot): disabling this GDSC will leave the lpass iommu completely unclocked, losing its state entirely - including the secure contexts that have been previously set-up from the bootloader/TrustZone. Losing this IOMMU configuration will trigger a hypervisor fault, which will reboot the system; the only workaround for this issue is to declare the lpass core gdsc as always-on. It should also not be forgotten that this is all about firmware and there may be a version of it that doesn't enable this GDSC at all before booting Linux, which is the reason why this specific declaration wasn't simply omitted. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/qcom/gcc-msm8998.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 424371d88a44..d85091e6cd5d 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2902,6 +2902,26 @@ static struct gdsc usb_30_gdsc = { .flags = VOTABLE, }; +static struct gdsc hlos1_vote_lpass_adsp = { + .gdscr = 0x7d034, + .gds_hw_ctrl = 0x0, + .pd = { + .name = "lpass_adsp_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_lpass_core = { + .gdscr = 0x7d038, + .gds_hw_ctrl = 0x0, + .pd = { + .name = "lpass_core_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = ALWAYS_ON, +}; + static struct clk_regmap *gcc_msm8998_clocks[] = { [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, @@ -3084,6 +3104,8 @@ static struct gdsc *gcc_msm8998_gdscs[] = { [PCIE_0_GDSC] = &pcie_0_gdsc, [UFS_GDSC] = &ufs_gdsc, [USB_30_GDSC] = &usb_30_gdsc, + [LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp, + [LPASS_CORE_GDSC] = &hlos1_vote_lpass_core, }; static const struct qcom_reset_map gcc_msm8998_resets[] = { From d445d3a0d868eddcde19e95f71304468dcb483cd Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 17:11:02 +0200 Subject: [PATCH 102/174] arm64: dts: qcom: msm8998: Add disabled support for lpass iommu for q6 Add support for the LPASS (Q6) SMMU and keep it disabled as this is used only when the audio DSP is present and used, which is not mandatory to have. It is expected for board-specific device-trees to enable this node if supported. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 927a3306f242..731c5a0ea59e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2206,6 +2206,33 @@ "gpll0"; }; + lpass_q6_smmu: iommu@5100000 { + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + reg = <0x05100000 0x40000>; + clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; + clock-names = "iface"; + + #global-interrupts = <0>; + #iommu-cells = <1>; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + , + ; + + power-domains = <&gcc LPASS_ADSP_GDSC>; + status = "disabled"; + }; + remoteproc_slpi: remoteproc@5800000 { compatible = "qcom,msm8998-slpi-pas"; reg = <0x05800000 0x4040>; From ec880e7f428d400c01a2ab9685e7e3ef6d501e2d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 17:14:35 +0200 Subject: [PATCH 103/174] arm64: dts: qcom: msm8998: Define fastrpc ADSP compute context banks If the target board supports ADSP, it is essential to have fastrpc compute context banks defined. This commit adds the always usable unsecured context banks only. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 731c5a0ea59e..b4de3684e4f2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3532,6 +3532,33 @@ label = "lpass"; qcom,remote-pid = <2>; mboxes = <&apcs_glb 9>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + dma-ranges = <0 0x60000000 0 0x18000000>; + reg = <2>; + iommus = <&lpass_q6_smmu 2>; + }; + + cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&lpass_q6_smmu 5>; + }; + + cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&lpass_q6_smmu 6>; + }; + }; }; }; From 03d8638281c87bc80b74da46973218cec4cf8279 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 17:18:05 +0200 Subject: [PATCH 104/174] arm64: dts: qcom: msm8998: Add APR services configuration Add the standard APR Q6 services configuration for MSM8998, used by boards supporting the audio dsp. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b4de3684e4f2..0c7e47f983d1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include /* Macro for CPR-Hardened OPP entries - Example phandle: cprh_opp0 */ @@ -3533,6 +3534,60 @@ qcom,remote-pid = <2>; mboxes = <&apcs_glb 9>; + apr { + compatible = "qcom,apr-v2"; + power-domains = <&gcc LPASS_ADSP_GDSC>; + qcom,glink-channels = "apr_audio_svc"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + qcom,intents = <512 20>; + + apr-service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: apr-service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + hdmi@1 { + reg = <1>; + }; + }; + }; + + q6asm: apr-service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&lpass_q6_smmu 1>; + }; + }; + + q6adm: apr-service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; From 41bea9ea588c253c66eab87af4154b36bbabe7ac Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 19:09:29 +0200 Subject: [PATCH 105/174] arm64: dts: qcom: msm8998-xperia: Enable lpass smmu To support audio dsp functionality, enable the lpass smmu. The firmware distributed with the MSM8998 Sony Xperia smartphones requires us to skip resetting CB12 of this SMMU and to use CB11 as a context bank to emulate bypass streams. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixed up for v5.16-rc1) --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 8de3d79e7d11..40e5fb889c7a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -369,6 +369,13 @@ regulator-soft-start; }; +&lpass_q6_smmu { + qcom,bypass-cbndx = /bits/ 8 <11>; + qcom,reset-nodisable-cbs = /bits/ 8 <12>; + + status = "ok"; +}; + &mmcc { status = "ok"; }; From a8e39acb816c4de835f98bf5ca02b8ad57d36158 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 19:21:02 +0200 Subject: [PATCH 106/174] ASoC: qcom: Add MSM8998 sound card support Add MSM8998 sound support: this driver supports basic functionality and headphone jack. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for 5.17) --- sound/soc/qcom/Kconfig | 11 + sound/soc/qcom/Makefile | 2 + sound/soc/qcom/msm8998.c | 501 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 514 insertions(+) create mode 100644 sound/soc/qcom/msm8998.c diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index cf3e151bb635..05e2013bafbb 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -137,6 +137,17 @@ config SND_SOC_MSM8996 APQ8096 SoC-based systems. Say Y if you want to use audio device on this SoCs +config SND_SOC_MSM8998 + tristate "SoC Machine driver for MSM8998 and APQ8098 boards" + depends on QCOM_APR && I2C && SOUNDWIRE + depends on COMMON_CLK + select SND_SOC_QDSP6 + select SND_SOC_QCOM_COMMON + help + To add support for audio on Qualcomm Technologies Inc. + MSM8998 SoC-based systems. + Say Y if you want to use audio device on this SoCs. + config SND_SOC_SDM845 tristate "SoC Machine driver for SDM845 boards" depends on QCOM_APR && I2C && SOUNDWIRE diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile index 1600ae55bd34..26fe19ac60a6 100644 --- a/sound/soc/qcom/Makefile +++ b/sound/soc/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SND_SOC_LPASS_SC7180) += snd-soc-lpass-sc7180.o snd-soc-storm-objs := storm.o snd-soc-apq8016-sbc-objs := apq8016_sbc.o snd-soc-apq8096-objs := apq8096.o +snd-soc-msm8998-objs := msm8998.o snd-soc-sc7180-objs := sc7180.o snd-soc-sdm845-objs := sdm845.o snd-soc-sm8250-objs := sm8250.o @@ -26,6 +27,7 @@ snd-soc-qcom-common-objs := common.o obj-$(CONFIG_SND_SOC_STORM) += snd-soc-storm.o obj-$(CONFIG_SND_SOC_APQ8016_SBC) += snd-soc-apq8016-sbc.o obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-apq8096.o +obj-$(CONFIG_SND_SOC_MSM8998) += snd-soc-msm8998.o obj-$(CONFIG_SND_SOC_SC7180) += snd-soc-sc7180.o obj-$(CONFIG_SND_SOC_SDM845) += snd-soc-sdm845.o obj-$(CONFIG_SND_SOC_SM8250) += snd-soc-sm8250.o diff --git a/sound/soc/qcom/msm8998.c b/sound/soc/qcom/msm8998.c new file mode 100644 index 000000000000..60b5581f5c5b --- /dev/null +++ b/sound/soc/qcom/msm8998.c @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on sdm845.c + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * MSM8998 ASoC driver + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "qdsp6/q6afe.h" + +#define DRIVER_NAME "msm8998" +#define DEFAULT_SAMPLE_RATE_48K 48000 +#define DEFAULT_MCLK_RATE 24576000 +#define TDM_BCLK_RATE 6144000 +#define MI2S_BCLK_RATE 1536000 +#define LEFT_SPK_TDM_TX_MASK 0x30 +#define RIGHT_SPK_TDM_TX_MASK 0xC0 +#define SPK_TDM_RX_MASK 0x03 +#define NUM_TDM_SLOTS 8 +#define SLIM_MAX_TX_PORTS 17 +#define SLIM_MAX_RX_PORTS 14 +#define WCD934X_DEFAULT_MCLK_RATE 9600000 + +struct msm8998_snd_data { + struct snd_soc_jack jack; + bool jack_setup; + bool stream_prepared[SLIM_MAX_RX_PORTS]; + struct snd_soc_card *card; + uint32_t quat_tdm_clk_count; + struct sdw_stream_runtime *sruntime[SLIM_MAX_RX_PORTS]; +}; + +static unsigned int tdm_slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28}; + +static int msm8998_slim_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai; + struct msm8998_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card); + u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + struct sdw_stream_runtime *sruntime; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + int ret = 0, i; + + for_each_rtd_codec_dais(rtd, i, codec_dai) { + sruntime = snd_soc_dai_get_stream(codec_dai, + substream->stream); + if (sruntime != ERR_PTR(-ENOTSUPP)) + pdata->sruntime[cpu_dai->id] = sruntime; + + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + + if (ret != 0 && ret != -ENOTSUPP) { + pr_err("failed to get codec chan map, err:%d\n", ret); + return ret; + } else if (ret == -ENOTSUPP) { + /* Ignore unsupported */ + continue; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, + rx_ch_cnt, rx_ch); + else + ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt, + tx_ch, 0, NULL); + } + + return 0; +} + +static int msm8998_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai; + int ret = 0, j; + int channels, slot_width; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + slot_width = 16; + break; + default: + dev_err(rtd->dev, "%s: invalid param format 0x%x\n", + __func__, params_format(params)); + return -EINVAL; + } + + channels = params_channels(params); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0x3, + 8, slot_width); + if (ret < 0) { + dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, + channels, tdm_slot_offset); + if (ret < 0) { + dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } else { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xf, 0, + 8, slot_width); + if (ret < 0) { + dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, channels, + tdm_slot_offset, 0, NULL); + if (ret < 0) { + dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } + + for_each_rtd_codec_dais(rtd, j, codec_dai) { + + if (!strcmp(codec_dai->component->name_prefix, "Left")) { + ret = snd_soc_dai_set_tdm_slot( + codec_dai, LEFT_SPK_TDM_TX_MASK, + SPK_TDM_RX_MASK, NUM_TDM_SLOTS, + slot_width); + if (ret < 0) { + dev_err(rtd->dev, + "DEV0 TDM slot err:%d\n", ret); + return ret; + } + } + + if (!strcmp(codec_dai->component->name_prefix, "Right")) { + ret = snd_soc_dai_set_tdm_slot( + codec_dai, RIGHT_SPK_TDM_TX_MASK, + SPK_TDM_RX_MASK, NUM_TDM_SLOTS, + slot_width); + if (ret < 0) { + dev_err(rtd->dev, + "DEV1 TDM slot err:%d\n", ret); + return ret; + } + } + } + +end: + return ret; +} + +static int msm8998_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + int ret = 0; + + switch (cpu_dai->id) { + case QUATERNARY_TDM_RX_0: + case QUATERNARY_TDM_TX_0: + ret = msm8998_tdm_snd_hw_params(substream, params); + break; + case SLIMBUS_0_RX...SLIMBUS_6_TX: + ret = msm8998_slim_snd_hw_params(substream, params); + break; + case QUATERNARY_MI2S_RX: + break; + default: + pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id); + break; + } + return ret; +} + +static int msm8998_dai_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct msm8998_snd_data *pdata = snd_soc_card_get_drvdata(card); + struct snd_jack *jack; + /* + * Codec SLIMBUS configuration + * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13, RX14 + * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13, TX14, + * TX15, TX16 + */ + unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149, + 150, 151, 152, 153, 154, 155, + 156, 157 }; + unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, + 140, 141, 142, 143}; + int ret, i; + + if (!pdata->jack_setup) { + ret = snd_soc_card_jack_new(card, "Headset Jack", + SND_JACK_HEADSET | + SND_JACK_HEADPHONE | + SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3, + &pdata->jack, NULL, 0); + + if (ret < 0) { + dev_err(card->dev, "Unable to add Headphone Jack\n"); + return ret; + } + + jack = pdata->jack.jack; + + snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); + snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND); + snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP); + snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN); + pdata->jack_setup = true; + } + + switch (cpu_dai->id) { + case SLIMBUS_0_RX...SLIMBUS_6_TX: + for_each_rtd_codec_dais(rtd, i, codec_dai) { + ret = snd_soc_dai_set_channel_map(codec_dai, + ARRAY_SIZE(tx_ch), tx_ch, + ARRAY_SIZE(rx_ch), rx_ch); + if (ret != 0 && ret != -ENOTSUPP) + return ret; + + snd_soc_dai_set_sysclk(codec_dai, 0, + WCD934X_DEFAULT_MCLK_RATE, + SNDRV_PCM_STREAM_PLAYBACK); + + ret = snd_soc_component_set_jack(codec_dai->component, + &pdata->jack, NULL); + if (ret != 0 && ret != -ENOTSUPP) { + dev_warn(card->dev, "Failed to set jack: %d\n", ret); + return ret; + } + } + break; + default: + break; + } + + return 0; +} + +static int msm8998_snd_startup(struct snd_pcm_substream *substream) +{ + unsigned int codec_dai_fmt = SND_SOC_DAIFMT_CBS_CFS; + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_card *card = rtd->card; + struct msm8998_snd_data *data = snd_soc_card_get_drvdata(card); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); + int j; + int ret; + + switch (cpu_dai->id) { + case QUATERNARY_TDM_RX_0: + case QUATERNARY_TDM_TX_0: + if (++(data->quat_tdm_clk_count) == 1) { + snd_soc_dai_set_sysclk(cpu_dai, + Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT, + TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK); + } + + codec_dai_fmt |= SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_DSP_B; + + for_each_rtd_codec_dais(rtd, j, codec_dai) { + + if (!strcmp(codec_dai->component->name_prefix, + "Left")) { + ret = snd_soc_dai_set_fmt( + codec_dai, codec_dai_fmt); + if (ret < 0) { + dev_err(rtd->dev, + "Left TDM fmt err:%d\n", ret); + return ret; + } + } + + if (!strcmp(codec_dai->component->name_prefix, + "Right")) { + ret = snd_soc_dai_set_fmt( + codec_dai, codec_dai_fmt); + if (ret < 0) { + dev_err(rtd->dev, + "Right TDM slot err:%d\n", ret); + return ret; + } + } + } + break; + case SLIMBUS_0_RX...SLIMBUS_6_TX: + break; + + default: + pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id); + break; + } + return 0; +} + +static void msm8998_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_card *card = rtd->card; + struct msm8998_snd_data *data = snd_soc_card_get_drvdata(card); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + + switch (cpu_dai->id) { + case QUATERNARY_TDM_RX_0: + case QUATERNARY_TDM_TX_0: + if (--(data->quat_tdm_clk_count) == 0) { + snd_soc_dai_set_sysclk(cpu_dai, + Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT, + 0, SNDRV_PCM_STREAM_PLAYBACK); + } + break; + case SLIMBUS_0_RX...SLIMBUS_6_TX: + case QUATERNARY_MI2S_RX: + break; + + default: + pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id); + break; + } +} + +static int msm8998_snd_prepare(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct msm8998_snd_data *data = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id]; + int ret; + + if (!sruntime) + return 0; + + if (data->stream_prepared[cpu_dai->id]) { + sdw_disable_stream(sruntime); + sdw_deprepare_stream(sruntime); + data->stream_prepared[cpu_dai->id] = false; + } + + ret = sdw_prepare_stream(sruntime); + if (ret) + return ret; + + /** + * NOTE: there is a strict hw requirement about the ordering of port + * enables and actual WSA881x PA enable. PA enable should only happen + * after soundwire ports are enabled if not DC on the line is + * accumulated resulting in Click/Pop Noise + * PA enable/mute are handled as part of codec DAPM and digital mute. + */ + + ret = sdw_enable_stream(sruntime); + if (ret) { + sdw_deprepare_stream(sruntime); + return ret; + } + data->stream_prepared[cpu_dai->id] = true; + + return ret; +} + +static int msm8998_snd_hw_free(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct msm8998_snd_data *data = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id]; + + if (sruntime && data->stream_prepared[cpu_dai->id]) { + sdw_disable_stream(sruntime); + sdw_deprepare_stream(sruntime); + data->stream_prepared[cpu_dai->id] = false; + } + + return 0; +} + +static const struct snd_soc_ops msm8998_be_ops = { + .hw_params = msm8998_snd_hw_params, + .hw_free = msm8998_snd_hw_free, + .prepare = msm8998_snd_prepare, + .startup = msm8998_snd_startup, + .shutdown = msm8998_snd_shutdown, +}; + +static int msm8998_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); + + rate->min = rate->max = DEFAULT_SAMPLE_RATE_48K; + channels->min = channels->max = 2; + snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE); + + return 0; +} + +static const struct snd_soc_dapm_widget msm8998_snd_widgets[] = { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_SPK("Left Spk", NULL), + SND_SOC_DAPM_SPK("Right Spk", NULL), + SND_SOC_DAPM_MIC("Int Mic", NULL), +}; + +static void msm8998_add_ops(struct snd_soc_card *card) +{ + struct snd_soc_dai_link *link; + int i; + + for_each_card_prelinks(card, i, link) { + if (link->no_pcm == 1) { + link->ops = &msm8998_be_ops; + link->be_hw_params_fixup = msm8998_be_hw_params_fixup; + } + link->init = msm8998_dai_init; + } +} + +static int msm8998_snd_platform_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card; + struct msm8998_snd_data *data; + struct device *dev = &pdev->dev; + int ret; + + card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); + if (!card) + return -ENOMEM; + + /* Allocate the private data */ + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + card->driver_name = DRIVER_NAME; + card->dapm_widgets = msm8998_snd_widgets; + card->num_dapm_widgets = ARRAY_SIZE(msm8998_snd_widgets); + card->dev = dev; + card->owner = THIS_MODULE; + dev_set_drvdata(dev, card); + ret = qcom_snd_parse_of(card); + if (ret) + return ret; + + data->card = card; + snd_soc_card_set_drvdata(card, data); + + msm8998_add_ops(card); + return devm_snd_soc_register_card(dev, card); +} + +static const struct of_device_id msm8998_snd_device_id[] = { + { .compatible = "qcom,msm8998-sndcard" }, + {}, +}; +MODULE_DEVICE_TABLE(of, msm8998_snd_device_id); + +static struct platform_driver msm8998_snd_driver = { + .probe = msm8998_snd_platform_probe, + .driver = { + .name = "msm-snd-msm8998", + .of_match_table = msm8998_snd_device_id, + }, +}; +module_platform_driver(msm8998_snd_driver); + +MODULE_DESCRIPTION("msm8998 ASoC Machine Driver"); +MODULE_LICENSE("GPL v2"); From 27d473117ba62ea683a111612174d66e5bd87c45 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sat, 20 Nov 2021 22:48:10 +0200 Subject: [PATCH 107/174] ASoC: qcom: lpass-msm8998: Add platform driver for lpass audio Add platform driver for configuring msm8998 lpass core I2S and DMA configuration to support playback & capture to external codecs connected over primary & secondary MI2S interfaces. (driver originally split from 4d7e1ead3b08 ("fastmatrix yaml fix")) --- include/dt-bindings/sound/msm8998-lpass.h | 9 + sound/soc/qcom/Kconfig | 7 + sound/soc/qcom/Makefile | 2 + sound/soc/qcom/lpass-msm8998.c | 330 ++++++++++++++++++++++ 4 files changed, 348 insertions(+) create mode 100644 include/dt-bindings/sound/msm8998-lpass.h create mode 100644 sound/soc/qcom/lpass-msm8998.c diff --git a/include/dt-bindings/sound/msm8998-lpass.h b/include/dt-bindings/sound/msm8998-lpass.h new file mode 100644 index 000000000000..79fc5cb4882b --- /dev/null +++ b/include/dt-bindings/sound/msm8998-lpass.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MSM8998_LPASS_H +#define __DT_MSM8998_LPASS_H + +#include + +/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ + +#endif /* __DT_MSM8998_LPASS_H */ diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index 05e2013bafbb..73b96992cb56 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -30,6 +30,12 @@ config SND_SOC_LPASS_APQ8016 select SND_SOC_LPASS_CPU select SND_SOC_LPASS_PLATFORM +config SND_SOC_LPASS_MSM8998 + tristate + select SND_SOC_LPASS_CPU + select SND_SOC_LPASS_PLATFORM + select SND_SOC_LPASS_HDMI + config SND_SOC_LPASS_SC7180 tristate select SND_SOC_LPASS_CPU @@ -143,6 +149,7 @@ config SND_SOC_MSM8998 depends on COMMON_CLK select SND_SOC_QDSP6 select SND_SOC_QCOM_COMMON + select SND_SOC_LPASS_MSM8998 help To add support for audio on Qualcomm Technologies Inc. MSM8998 SoC-based systems. diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile index 26fe19ac60a6..07a5f205d886 100644 --- a/sound/soc/qcom/Makefile +++ b/sound/soc/qcom/Makefile @@ -5,6 +5,7 @@ snd-soc-lpass-hdmi-objs := lpass-hdmi.o snd-soc-lpass-platform-objs := lpass-platform.o snd-soc-lpass-ipq806x-objs := lpass-ipq806x.o snd-soc-lpass-apq8016-objs := lpass-apq8016.o +snd-soc-lpass-msm8998-objs := lpass-msm8998.o snd-soc-lpass-sc7180-objs := lpass-sc7180.o obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o @@ -12,6 +13,7 @@ obj-$(CONFIG_SND_SOC_LPASS_HDMI) += snd-soc-lpass-hdmi.o obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o obj-$(CONFIG_SND_SOC_LPASS_IPQ806X) += snd-soc-lpass-ipq806x.o obj-$(CONFIG_SND_SOC_LPASS_APQ8016) += snd-soc-lpass-apq8016.o +obj-$(CONFIG_SND_SOC_LPASS_MSM8998) += snd-soc-lpass-msm8998.o obj-$(CONFIG_SND_SOC_LPASS_SC7180) += snd-soc-lpass-sc7180.o # Machine diff --git a/sound/soc/qcom/lpass-msm8998.c b/sound/soc/qcom/lpass-msm8998.c new file mode 100644 index 000000000000..56079396337f --- /dev/null +++ b/sound/soc/qcom/lpass-msm8998.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 AngeloGioacchino Del Regno + * + * + * lpass-msm8998.c -- ALSA SoC platform-machine driver for QTi LPASS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lpass-lpaif-reg.h" +#include "lpass.h" + +static struct snd_soc_dai_driver msm8998_lpass_cpu_dai_driver[] = { + { + .id = MI2S_PRIMARY, + .name = "Primary MI2S", + .playback = { + .stream_name = "Primary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .capture = { + .stream_name = "Primary Capture", + .formats = SNDRV_PCM_FMTBIT_S16 | + SNDRV_PCM_FMTBIT_S32, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, { + .id = MI2S_SECONDARY, + .name = "Secondary MI2S", + .playback = { + .stream_name = "Secondary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, { + .id = MI2S_TERTIARY, + .name = "Tertiary MI2S", + .playback = { + .stream_name = "Tertiary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, { + .id = MI2S_QUATERNARY, + .name = "Quaternary MI2S", + .playback = { + .stream_name = "Quaternary Playback", + .formats = SNDRV_PCM_FMTBIT_S16, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .probe = &asoc_qcom_lpass_cpu_dai_probe, + .ops = &asoc_qcom_lpass_cpu_dai_ops, + }, { + .id = LPASS_DP_RX, + .name = "Hdmi", + .playback = { + .stream_name = "Hdmi Playback", + .formats = SNDRV_PCM_FMTBIT_S24, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &asoc_qcom_lpass_hdmi_dai_ops, + }, +}; + +static int msm8998_lpass_alloc_dma_channel(struct lpass_data *drvdata, + int direction, unsigned int dai_id) +{ + struct lpass_variant *v = drvdata->variant; + int chan = 0; + + if (dai_id == LPASS_DP_RX) { + if (direction == SNDRV_PCM_STREAM_PLAYBACK) { + chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map, + v->hdmi_rdma_channels); + + if (chan >= v->hdmi_rdma_channels) + return -EBUSY; + } + set_bit(chan, &drvdata->hdmi_dma_ch_bit_map); + } else { + if (direction == SNDRV_PCM_STREAM_PLAYBACK) { + chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, + v->rdma_channels); + + if (chan >= v->rdma_channels) + return -EBUSY; + } else { + chan = find_next_zero_bit(&drvdata->dma_ch_bit_map, + v->wrdma_channel_start + + v->wrdma_channels, + v->wrdma_channel_start); + + if (chan >= v->wrdma_channel_start + v->wrdma_channels) + return -EBUSY; + } + + set_bit(chan, &drvdata->dma_ch_bit_map); + } + return chan; +} + +static int msm8998_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id) +{ + if (dai_id == LPASS_DP_RX) + clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map); + else + clear_bit(chan, &drvdata->dma_ch_bit_map); + + return 0; +} + +static int msm8998_lpass_init(struct platform_device *pdev) +{ + struct lpass_data *drvdata = platform_get_drvdata(pdev); + struct lpass_variant *variant = drvdata->variant; + struct device *dev = &pdev->dev; + int ret, i; + + drvdata->clks = devm_kcalloc(dev, variant->num_clks, + sizeof(*drvdata->clks), GFP_KERNEL); + drvdata->num_clks = variant->num_clks; + + for (i = 0; i < drvdata->num_clks; i++) + drvdata->clks[i].id = variant->clk_name[i]; + + ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks); + if (ret) { + dev_err(dev, "Failed to get clocks %d\n", ret); + return ret; + } + + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); + if (ret) { + dev_err(dev, "msm8998 clk_enable failed\n"); + return ret; + } + + return 0; +} + +static int msm8998_lpass_exit(struct platform_device *pdev) +{ + struct lpass_data *drvdata = platform_get_drvdata(pdev); + + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); + + return 0; +} + +static struct lpass_variant msm8998_data = { + .i2sctrl_reg_base = 0x1000, + .i2sctrl_reg_stride = 0x1000, + .i2s_ports = 3, + .irq_reg_base = 0xa000, + .irq_reg_stride = 0x1000, + .irq_ports = 3, + .rdma_reg_base = 0xD000, + .rdma_reg_stride = 0x1000, + .rdma_channels = 5, + .hdmi_rdma_reg_base = 0x3000, + .hdmi_rdma_reg_stride = 0x1000, + .hdmi_rdma_channels = 4, + .dmactl_audif_start = 1, /* what's that?? */ + .wrdma_reg_base = 0x13000, + .wrdma_reg_stride = 0x1000, + .wrdma_channel_start = 5, /* ?? what's that ?? */ + .wrdma_channels = 4, + + .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000), + .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000), + .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000), + .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000), + .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000), + .micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000), + .micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000), + .wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000), + .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000), + + .rdma_dyncclk = REG_FIELD_ID(0xD000, 14, 14, 4, 0x1000), + .rdma_bursten = REG_FIELD_ID(0xD000, 13, 13, 4, 0x1000), + .rdma_wpscnt = REG_FIELD_ID(0xD000, 10, 12, 4, 0x1000), + .rdma_intf = REG_FIELD_ID(0xD000, 6, 9, 4, 0x1000), + .rdma_fifowm = REG_FIELD_ID(0xD000, 1, 5, 4, 0x1000), + .rdma_enable = REG_FIELD_ID(0xD000, 0, 0, 4, 0x1000), + + .wrdma_dyncclk = REG_FIELD_ID(0x13000, 12, 12, 3, 0x1000), + .wrdma_bursten = REG_FIELD_ID(0x13000, 11, 11, 3, 0x1000), + .wrdma_wpscnt = REG_FIELD_ID(0x13000, 8, 10, 3, 0x1000), + .wrdma_intf = REG_FIELD_ID(0x13000, 4, 7, 3, 0x1000), + .wrdma_fifowm = REG_FIELD_ID(0x13000, 1, 3, 3, 0x1000), + .wrdma_enable = REG_FIELD_ID(0x13000, 0, 0, 3, 0x1000), + + .hdmi_tx_ctl_addr = 0x1000, + .hdmi_legacy_addr = 0x1008, + .hdmi_vbit_addr = 0xc0, + .hdmi_ch_lsb_addr = 0x48, + .hdmi_ch_msb_addr = 0x4c, + .ch_stride = 0x8, + .hdmi_parity_addr = 0x34, + .hdmi_dmactl_addr = 0x38, + .hdmi_dma_stride = 0x4, + .hdmi_DP_addr = 0xc8, + .hdmi_sstream_addr = 0x1c, + .hdmi_irq_reg_base = 0x63000, + .hdmi_irq_ports = 1, + + .hdmi_rdma_dyncclk = REG_FIELD_ID(0x3000, 14, 14, 3, 0x1000), + .hdmi_rdma_bursten = REG_FIELD_ID(0x3000, 13, 13, 3, 0x1000), + .hdmi_rdma_burst8 = REG_FIELD_ID(0x3000, 15, 15, 3, 0x1000), + .hdmi_rdma_burst16 = REG_FIELD_ID(0x3000, 16, 16, 3, 0x1000), + .hdmi_rdma_dynburst = REG_FIELD_ID(0x3000, 18, 18, 3, 0x1000), + .hdmi_rdma_wpscnt = REG_FIELD_ID(0x3000, 10, 12, 3, 0x1000), + .hdmi_rdma_fifowm = REG_FIELD_ID(0x3000, 1, 5, 3, 0x1000), + .hdmi_rdma_enable = REG_FIELD_ID(0x3000, 0, 0, 3, 0x1000), + + .sstream_en = REG_FIELD(0x1c, 0, 0), + .dma_sel = REG_FIELD(0x1c, 1, 2), + .auto_bbit_en = REG_FIELD(0x1c, 3, 3), + .layout = REG_FIELD(0x1c, 4, 4), + .layout_sp = REG_FIELD(0x1c, 5, 8), + .set_sp_on_en = REG_FIELD(0x1c, 10, 10), + .dp_audio = REG_FIELD(0x1c, 11, 11), + .dp_staffing_en = REG_FIELD(0x1c, 12, 12), + .dp_sp_b_hw_en = REG_FIELD(0x1c, 13, 13), + + .mute = REG_FIELD(0xc8, 0, 0), + .as_sdp_cc = REG_FIELD(0xc8, 1, 3), + .as_sdp_ct = REG_FIELD(0xc8, 4, 7), + .aif_db4 = REG_FIELD(0xc8, 8, 15), + + .soft_reset = REG_FIELD(0x1000, 31, 31), + .force_reset = REG_FIELD(0x1000, 30, 30), + + .use_hw_chs = REG_FIELD(0x38, 0, 0), + .use_hw_usr = REG_FIELD(0x38, 1, 1), + .hw_chs_sel = REG_FIELD(0x38, 2, 4), + .hw_usr_sel = REG_FIELD(0x38, 5, 6), + + .replace_vbit = REG_FIELD(0xc0, 0, 0), + .vbit_stream = REG_FIELD(0xc0, 1, 1), + + .legacy_en = REG_FIELD(0x1008, 0, 0), + .calc_en = REG_FIELD(0x34, 0, 0), + .lsb_bits = REG_FIELD(0x48, 0, 31), + .msb_bits = REG_FIELD(0x4c, 0, 16), + + + .clk_name = (const char*[]) { + "pcnoc-sway-clk", + "audio-core", + "pcnoc-mport-clk", + }, + .num_clks = 3, + .dai_driver = msm8998_lpass_cpu_dai_driver, + .num_dai = ARRAY_SIZE(msm8998_lpass_cpu_dai_driver), + .dai_osr_clk_names = (const char *[]) { + "mclk0", + "null", + }, + .dai_bit_clk_names = (const char *[]) { + "mi2s-bit-clk0", + "mi2s-bit-clk1", + }, + .init = msm8998_lpass_init, + .exit = msm8998_lpass_exit, + .alloc_dma_channel = msm8998_lpass_alloc_dma_channel, + .free_dma_channel = msm8998_lpass_free_dma_channel, +}; + +static const struct of_device_id msm8998_lpass_cpu_device_id[] __maybe_unused = { + {.compatible = "qcom,msm8998-lpass-cpu", .data = &msm8998_data}, + {} +}; +MODULE_DEVICE_TABLE(of, msm8998_lpass_cpu_device_id); + +static struct platform_driver msm8998_lpass_cpu_platform_driver = { + .driver = { + .name = "msm8998-lpass-cpu", + .of_match_table = of_match_ptr(msm8998_lpass_cpu_device_id), + }, + .probe = asoc_qcom_lpass_cpu_platform_probe, + .remove = asoc_qcom_lpass_cpu_platform_remove, + .shutdown = asoc_qcom_lpass_cpu_platform_shutdown, +}; + +module_platform_driver(msm8998_lpass_cpu_platform_driver); + +MODULE_DESCRIPTION("msm8998 LPASS CPU DRIVER"); +MODULE_LICENSE("GPL v2"); From 2a698c43a622fe7953b6f257098a54cb1c9f7d70 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 9 Aug 2021 19:47:04 +0200 Subject: [PATCH 108/174] arm64: dts: qcom: msm8998: Add disabled slimbus support Add generic slimbus configuration to MSM8998 and keep it disabled. It is expected that this will be enabled in board-specific device trees when supported, along with the right audio codec. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0c7e47f983d1..5bbd3b027704 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3503,6 +3503,40 @@ }; }; + slimbam: dma-controller@17184000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x17184000 0x32000>; + num-channels = <31>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim: slim@171c0000 { + compatible = "qcom,slim-ngd-v2.1.0"; + reg = <0x171c0000 0x2c000>; + interrupts = ; + + qcom,apps-ch-pipes = <0x1f80>; + qcom,ea-pc = <0x210>; + status = "okay"; + dmas = <&slimbam 3>, <&slimbam 4>, + <&slimbam 5>, <&slimbam 6>; + dma-names = "rx", "tx", "tx2", "rx2"; + + #address-cells = <1>; + #size-cells = <0>; + + ngd@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,msm8998-adsp-pas"; reg = <0x17300000 0x4040>; From ddb5a4ec047d6342b37e4cde9ba1b74b03b8283c Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 17:46:39 +0200 Subject: [PATCH 109/174] mfd: wcd9335: Add support to wcd9335 codec Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC. This codec has integrated SoundWire controller, pin controller and interrupt controller. Originally from: d95b982a --- drivers/mfd/Kconfig | 12 ++ drivers/mfd/Makefile | 1 + drivers/mfd/wcd9335.c | 300 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 313 insertions(+) create mode 100644 drivers/mfd/wcd9335.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ba0b3eb131f1..4f8d456b716c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2032,6 +2032,18 @@ config MFD_WCD934X This driver provides common support WCD934x audio codec and its associated Pin Controller, Soundwire Controller and Audio codec. +config MFD_WCD9335 + tristate "Support for WCD9335 Codec" + depends on SLIMBUS + select REGMAP + select REGMAP_SLIMBUS + select REGMAP_IRQ + select MFD_CORE + help + Support for the Qualcomm WCD9335 Codec. + This driver provides common support WCD9335 audio codec and its + associated Pin Controller, Soundwire Controller and Audio codec. + config MFD_ATC260X tristate select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index df1ecc4a4c95..b4fc538193af 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -61,6 +61,7 @@ ifeq ($(CONFIG_MFD_CS47L24),y) arizona-objs += cs47l24-tables.o endif obj-$(CONFIG_MFD_WCD934X) += wcd934x.o +obj-$(CONFIG_MFD_WCD9335) += wcd9335.o obj-$(CONFIG_MFD_WM8400) += wm8400-core.o wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o wm831x-objs += wm831x-auxadc.o diff --git a/drivers/mfd/wcd9335.c b/drivers/mfd/wcd9335.c new file mode 100644 index 000000000000..fa8985f97359 --- /dev/null +++ b/drivers/mfd/wcd9335.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WCD9335_REGMAP_IRQ_REG(_irq, _off, _mask) \ + [_irq] = { \ + .reg_offset = (_off), \ + .mask = (_mask), \ + .type = { \ + .type_reg_offset = (_off), \ + .types_supported = IRQ_TYPE_EDGE_BOTH, \ + .type_reg_mask = (_mask), \ + .type_level_low_val = (_mask), \ + .type_level_high_val = (_mask), \ + .type_falling_val = 0, \ + .type_rising_val = 0, \ + }, \ + } + +static const struct mfd_cell wcd9335_devices[] = { + { + .name = "wcd9335-codec", + }, { + .name = "wcd9335-gpio", + .of_compatible = "qcom,wcd9340-gpio", + }, { + .name = "wcd9335-soundwire", + .of_compatible = "qcom,soundwire-v1.3.0", + }, +}; + +static const struct regmap_irq wcd9335_irqs[] = { + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_SLIMBUS, 0, BIT(0)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_HPH_PA_OCPL_FAULT, 0, BIT(2)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_HPH_PA_OCPR_FAULT, 0, BIT(3)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_MBHC_SW_DET, 1, BIT(0)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_MBHC_ELECT_INS_REM_DET, 1, BIT(1)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_MBHC_BUTTON_PRESS_DET, 1, BIT(2)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET, 1, BIT(3)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 1, BIT(4)), + WCD9335_REGMAP_IRQ_REG(WCD9335_IRQ_SOUNDWIRE, 2, BIT(4)), +}; + +static const struct regmap_irq_chip wcd9335_regmap_irq_chip = { + .name = "wcd9335_irq", + .status_base = WCD9335_INTR_PIN1_STATUS0, + .mask_base = WCD9335_INTR_PIN1_MASK0, + .ack_base = WCD9335_INTR_PIN1_CLEAR0, + .type_base = WCD9335_INTR_LEVEL0, + .num_type_reg = 4, + .type_in_mask = false, + .num_regs = 4, + .irqs = wcd9335_irqs, + .num_irqs = ARRAY_SIZE(wcd9335_irqs), +}; + +static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: + case WCD9335_SWR_AHB_BRIDGE_RD_DATA_0: + case WCD9335_SWR_AHB_BRIDGE_RD_DATA_1: + case WCD9335_SWR_AHB_BRIDGE_RD_DATA_2: + case WCD9335_SWR_AHB_BRIDGE_RD_DATA_3: + case WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS: + case WCD9335_ANA_MBHC_RESULT_3: + case WCD9335_ANA_MBHC_RESULT_2: + case WCD9335_ANA_MBHC_RESULT_1: + case WCD9335_ANA_MBHC_MECH: + case WCD9335_ANA_MBHC_ELECT: + case WCD9335_ANA_MBHC_ZDET: + case WCD9335_ANA_MICB2: + case WCD9335_ANA_RCO: + case WCD9335_ANA_BIAS: + return true; + default: + return false; + } +}; + +static const struct regmap_range_cfg wcd9335_ranges[] = { + { .name = "WCD9335", + .range_min = 0x0, + .range_max = WCD9335_MAX_REGISTER, + .selector_reg = WCD9335_SEL_REGISTER, + .selector_mask = WCD9335_SEL_MASK, + .selector_shift = WCD9335_SEL_SHIFT, + .window_start = WCD9335_WINDOW_START, + .window_len = WCD9335_WINDOW_LENGTH, + }, +}; + +static struct regmap_config wcd9335_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = 0xffff, + .can_multi_write = true, + .ranges = wcd9335_ranges, + .num_ranges = ARRAY_SIZE(wcd9335_ranges), + .volatile_reg = wcd9335_is_volatile_register, +}; + +static int wcd9335_bring_up(struct wcd9335_ddata *ddata) +{ + struct regmap *regmap = ddata->regmap; + u16 id_minor, id_major; + int ret; + + ret = regmap_bulk_read(regmap, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, + (u8 *)&id_minor, sizeof(u16)); + if (ret) + return ret; + + ret = regmap_bulk_read(regmap, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2, + (u8 *)&id_major, sizeof(u16)); + if (ret) + return ret; + + dev_info(ddata->dev, "WCD934x chip id major 0x%x, minor 0x%x\n", + id_major, id_minor); + + regmap_write(regmap, WCD9335_CODEC_RPM_RST_CTL, 0x01); + regmap_write(regmap, WCD9335_SIDO_NEW_VOUT_A_STARTUP, 0x19); + regmap_write(regmap, WCD9335_SIDO_NEW_VOUT_D_STARTUP, 0x15); + /* Add 1msec delay for VOUT to settle */ + usleep_range(1000, 1100); + regmap_write(regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); + regmap_write(regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); + regmap_write(regmap, WCD9335_CODEC_RPM_RST_CTL, 0x3); + regmap_write(regmap, WCD9335_CODEC_RPM_RST_CTL, 0x7); + regmap_write(regmap, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); + + return 0; +} + +static int wcd9335_slim_status_up(struct slim_device *sdev) +{ + struct device *dev = &sdev->dev; + struct wcd9335_ddata *ddata; + int ret; + + ddata = dev_get_drvdata(dev); + + ddata->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); + if (IS_ERR(ddata->regmap)) { + dev_err(dev, "Error allocating slim regmap\n"); + return PTR_ERR(ddata->regmap); + } + + ret = wcd9335_bring_up(ddata); + if (ret) { + dev_err(dev, "Failed to bring up WCD9335: err = %d\n", ret); + return ret; + } + + ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq, + IRQF_TRIGGER_HIGH, 0, + &wcd9335_regmap_irq_chip, + &ddata->irq_data); + if (ret) { + dev_err(dev, "Failed to add IRQ chip: err = %d\n", ret); + return ret; + } + + ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, wcd9335_devices, + ARRAY_SIZE(wcd9335_devices), NULL, 0, NULL); + if (ret) { + dev_err(dev, "Failed to add child devices: err = %d\n", + ret); + return ret; + } + + return ret; +} + +static int wcd9335_slim_status(struct slim_device *sdev, + enum slim_device_status status) +{ + switch (status) { + case SLIM_DEVICE_STATUS_UP: + return wcd9335_slim_status_up(sdev); + case SLIM_DEVICE_STATUS_DOWN: + mfd_remove_devices(&sdev->dev); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wcd9335_slim_probe(struct slim_device *sdev) +{ + struct device *dev = &sdev->dev; + struct device_node *np = dev->of_node; + struct wcd9335_ddata *ddata; + int reset_gpio, ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->irq = of_irq_get(np, 0); + if (ddata->irq < 0) + return dev_err_probe(ddata->dev, ddata->irq, + "Failed to get IRQ\n"); + + reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); + if (reset_gpio < 0) { + dev_err(dev, "Failed to get reset gpio: err = %d\n", + reset_gpio); + return reset_gpio; + } + + ddata->extclk = devm_clk_get(dev, "extclk"); + if (IS_ERR(ddata->extclk)) { + dev_err(dev, "Failed to get extclk"); + return PTR_ERR(ddata->extclk); + } + + ddata->supplies[0].supply = "vdd-buck"; + ddata->supplies[1].supply = "vdd-buck-sido"; + ddata->supplies[2].supply = "vdd-tx"; + ddata->supplies[3].supply = "vdd-rx"; + ddata->supplies[4].supply = "vdd-io"; + + ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, ddata->supplies); + if (ret) { + dev_err(dev, "Failed to get supplies: err = %d\n", ret); + return ret; + } + + ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, ddata->supplies); + if (ret) { + dev_err(dev, "Failed to enable supplies: err = %d\n", ret); + return ret; + } + + /* + * For WCD9335, it takes about 600us for the Vout_A and + * Vout_D to be ready after BUCK_SIDO is powered up. + * SYS_RST_N shouldn't be pulled high during this time + */ + usleep_range(600, 650); + gpio_direction_output(reset_gpio, 0); + msleep(20); + gpio_set_value(reset_gpio, 1); + msleep(20); + + ddata->dev = dev; + dev_set_drvdata(dev, ddata); + + return 0; +} + +static void wcd9335_slim_remove(struct slim_device *sdev) +{ + struct wcd9335_ddata *ddata = dev_get_drvdata(&sdev->dev); + + regulator_bulk_disable(WCD9335_MAX_SUPPLY, ddata->supplies); + mfd_remove_devices(&sdev->dev); +} + +static const struct slim_device_id wcd9335_slim_id[] = { + { SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9340, + SLIM_DEV_IDX_WCD9340, SLIM_DEV_INSTANCE_ID_WCD9340 }, + {} +}; + +static struct slim_driver wcd9335_slim_driver = { + .driver = { + .name = "wcd9335-slim", + }, + .probe = wcd9335_slim_probe, + .remove = wcd9335_slim_remove, + .device_status = wcd9335_slim_status, + .id_table = wcd9335_slim_id, +}; + +module_slim_driver(wcd9335_slim_driver); +MODULE_DESCRIPTION("WCD9335 slim driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("slim:217:250:*"); +MODULE_AUTHOR("Srinivas Kandagatla "); From e7f46aaebe591e97ba14df7773f5cd25fc0b8180 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 15:34:27 +0200 Subject: [PATCH 110/174] fixup! arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5bbd3b027704..8e6353f0cafd 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2191,7 +2191,6 @@ * SoC VDDMX RPM Power Domain in the Adreno driver. */ power-domains = <&gpucc GPU_GX_GDSC>; - status = "disabled"; }; gpucc: clock-controller@5065000 { From be48c36833243abc030aab38edbb5a7b7772cbe3 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 15:50:24 +0200 Subject: [PATCH 111/174] arm64: dts: qcom: msm8998: More audio related node changes Originally from: d95b982a --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 8e6353f0cafd..6d59a5c6f403 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -928,6 +928,9 @@ }; }; + sound: sound { + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -3511,6 +3514,7 @@ #dma-cells = <1>; qcom,ee = <1>; qcom,num-ees = <2>; + status = "disabled"; }; slim: slim@171c0000 { @@ -3520,22 +3524,22 @@ qcom,apps-ch-pipes = <0x1f80>; qcom,ea-pc = <0x210>; - status = "okay"; + dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; - ngd@1 { + slim_ngd: ngd@1 { reg = <1>; - #address-cells = <2>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <1>; }; }; - remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,msm8998-adsp-pas"; reg = <0x17300000 0x4040>; @@ -3630,7 +3634,7 @@ cb@2 { compatible = "qcom,fastrpc-compute-cb"; - dma-ranges = <0 0x60000000 0 0x18000000>; + //dma-ranges = <0 0x60000000 0 0x18000000>; reg = <2>; iommus = <&lpass_q6_smmu 2>; }; From c5da981db76ab779da9037c77559ad4b845affd0 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 15:48:02 +0200 Subject: [PATCH 112/174] arm64: dts: qcom: Enable audio on MSM8998 Sony Yoshino platform Originally from: d95b982a --- .../msm8998-sony-xperia-yoshino-lilac.dts | 5 + .../msm8998-sony-xperia-yoshino-maple.dts | 14 +- .../msm8998-sony-xperia-yoshino-poplar.dts | 13 +- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 229 ++++++++++++++++++ 4 files changed, 246 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts index caacb7c28402..5f40db508e63 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts @@ -25,6 +25,11 @@ qcom,soft-start-us = <800>; }; +&wcd9335 { + pinctrl-0 = <&cdc_reset_n &wcd_int_n>; + pinctrl-names = "default"; +}; + &vreg_l22a_2p85 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 3c05fb130899..cc6153167e8d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -76,12 +76,12 @@ &pm8005_gpio { ear_en_default: ear-en-active { pins = "gpio1"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - drive-push-pull; + function = "normal"; bias-disable; - qcom,drive-strength = ; - power-source = <1>; + drive-push-pull; + output-low; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <1>; }; }; @@ -111,3 +111,7 @@ qcom,enabled-strings = <0 1 2 3>; }; +&wcd9335 { + pinctrl-0 = <&cdc_reset_n &wcd_int_n &ear_en_default>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts index 84911139a7d8..4c55fd7636fb 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -25,16 +25,9 @@ qcom,soft-start-us = <800>; }; -&pm8005_gpio { - ear_en_default: ear-en-active { - pins = "gpio1"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - drive-push-pull; - bias-disable; - qcom,drive-strength = ; - power-source = <1>; - }; +&wcd9335 { + pinctrl-0 = <&cdc_reset_n &wcd_int_n>; + pinctrl-names = "default"; }; &vreg_l18a_2p85 { diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 40e5fb889c7a..8b0b78e02d4f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -500,6 +500,27 @@ qcom,enabled-strings = <0 1>; }; +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +/* + dai@3 { + reg = <3>; + direction = <2>; + is-compress-dai; + }; +*/ +}; + &qusb2phy { status = "okay"; @@ -509,6 +530,7 @@ &remoteproc_adsp { firmware-name = "adsp.mdt"; + status = "okay"; }; &remoteproc_mss { @@ -707,6 +729,181 @@ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; +/* Downstream example +&snd_9335 { + qcom,msm-mbhc-hphl-swh = <1>; + /delete-property/ qcom,hph-en1-gpio; + /delete-property/ qcom,hph-en0-gpio; + /delete-property/ qcom,us-euro-gpios; + qcom,ear-en-gpios = <&pm8005_gpios 1 0>; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCLeft Headset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC3", "MIC BIAS4", + "MIC BIAS4", "Digital Mic3", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; +}; +*/ + +&slimbam { + status = "okay"; +}; + +&slim { + status = "okay"; +}; + +&slim_ngd { + tasha_ifd: tas-ifd { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1{ + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_LN_BB_CLK1>; + #clock-cells = <0>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1"; + interrupt-controller; + #interrupt-cells = <1>; + reset-gpios = <&tlmm 64 0>; + + slim-ifc-dev = <&tasha_ifd>; + + #address-cells = <1>; + #size-cells = <1>; + #sound-dai-cells = <1>; + + swm: swm@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x40>; + interrupts-extended = <&wcd9335 13>; + + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; + /*downstream is <0xFF 0x00 0x1F 0xFF 0x00 0x1F 0x00 0x00>;*/ + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; + clocks = <&xo>; + clock-names = "iface"; + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + left_spkr: wsa8810-left { + compatible = "sdw10217201000"; + reg = <0 1>; + powerdown-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wsa_leftspk_pwr_n>; + pinctrl-names = "default"; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-right { + compatible = "sdw10217201000"; + powerdown-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; + reg = <0 2>; + pinctrl-0 = <&wsa_rightspk_pwr_n>; + pinctrl-names = "default"; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + }; + }; +}; + +&sound { + compatible = "qcom,msm8998-sndcard"; + model = "Sony-Xperia-Yoshino"; + + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "DMIC0", "MIC BIAS1", + "DMIC4", "MIC BIAS4", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT", + "MM_DL1", "MultiMedia1 Playback"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9335 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; @@ -797,6 +994,38 @@ drive-strength = <2>; }; + wcd_int_n: wcd-int-n { + pins = "gpio54"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + input-enable; + }; + + cdc_reset_n: cdc-reset-n { + pins = "gpio64"; + function = "gpio"; + bias-pull-down; + drive-strength = <16>; + output-high; + }; + + wsa_leftspk_pwr_n: wsa-leftspk-pwr-n { + pins = "gpio65"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + + wsa_rightspk_pwr_n: wsa-rightspk-pwr-n { + pins = "gpio66"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + ts_reset_n: ts-reset-n { pins = "gpio89"; function = "gpio"; From b908c27f65102257c954283687e17596c833ee44 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 31 Aug 2018 15:46:15 +0100 Subject: [PATCH 113/174] ASoC: wcd9335: add mbhc support Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/wcd9335.c | 296 ++++++++++++++++++++++++++++++++++++- 1 file changed, 294 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index 1e60db4056ad..0ba23b5d8ae4 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -86,12 +87,18 @@ #define WCD9335_DEC_PWR_LVL_HP 0x04 #define WCD9335_DEC_PWR_LVL_DF 0x00 +#define WCD9335_MBHC_MAX_BUTTONS (8) + #define WCD9335_SLIM_RX_CH(p) \ {.port = p + WCD9335_RX_START, .shift = p,} #define WCD9335_SLIM_TX_CH(p) \ {.port = p, .shift = p,} +static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; +static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; + /* vout step value */ #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) @@ -319,6 +326,16 @@ struct wcd9335_codec { u32 num_rx_port; u32 num_tx_port; + struct snd_soc_jack *jack; + bool hphl_jack_type_normally_open; + bool gnd_jack_type_normally_open; + bool mbhc_btn_enabled; + int mbhc_btn0_released; + bool detect_accessory_type; + int accessory_type; + /* Voltage threshold for button detection */ + u32 vref_btn[WCD9335_MBHC_MAX_BUTTONS]; + int sido_input_src; enum wcd9335_sido_voltage sido_voltage; @@ -2814,7 +2831,6 @@ static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, break; case SND_SOC_DAPM_POST_PMU: snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); - if (decimator == 0) { snd_soc_component_write(comp, WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); @@ -2825,7 +2841,6 @@ static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, snd_soc_component_write(comp, WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); } - snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x01); snd_soc_component_update_bits(comp, tx_vol_ctl_reg, @@ -3963,6 +3978,131 @@ static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, return 0; } +static irqreturn_t wcd9335_mbhc_sw_irq(int irq, void *data) +{ + struct wcd9335_codec *wcd = data; + struct snd_soc_component *component = wcd->component; + bool ins = false; + + if (snd_soc_component_read32(component, WCD9335_ANA_MBHC_MECH) & + WCD9335_MBHC_MECH_DETECT_TYPE_MASK) + ins = true; + + /* Set the detection type appropriately */ + snd_soc_component_update_bits(component, WCD9335_ANA_MBHC_MECH, + WCD9335_MBHC_MECH_DETECT_TYPE_MASK, + (!ins << WCD9335_MBHC_MECH_DETECT_TYPE_SHIFT)); + + if (ins) { /* hs insertion */ + u32 btndet_curr_src; + + /* + * If no micbias is enabled, then enable 100uA internal + * current source for Button detection + */ + if (snd_soc_component_read32(component, WCD9335_ANA_MICB2) & + WCD9335_ANA_MICB2_ENABLE) + btndet_curr_src = WCD9335_ANA_MBHC_BD_ISRC_OFF; + else + btndet_curr_src = WCD9335_ANA_MBHC_BD_ISRC_100UA; + + snd_soc_component_update_bits(component, + WCD9335_ANA_MBHC_ELECT, + WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK, + btndet_curr_src); + + /* + * if only a btn0 press event is receive just before + * insert event then its a 3 pole headphone else if + * both press and release event received then its + * a headset. + */ + if (wcd->mbhc_btn0_released) { + snd_soc_jack_report(wcd->jack, + SND_JACK_HEADSET, hs_jack_mask); + wcd->accessory_type = SND_JACK_HEADSET; + } else { + snd_soc_jack_report(wcd->jack, + SND_JACK_HEADPHONE, hs_jack_mask); + wcd->accessory_type = SND_JACK_HEADPHONE; + } + + wcd->detect_accessory_type = false; + + } else { /* removal */ + snd_soc_jack_report(wcd->jack, 0, hs_jack_mask); + wcd->detect_accessory_type = true; + wcd->mbhc_btn0_released = false; + } + + return IRQ_HANDLED; +} + +static irqreturn_t wcd9335_mbhc_btn_press_irq(int irq, void *data) +{ + struct wcd9335_codec *wcd = data; + struct snd_soc_component *comp = wcd->component; + u32 btn_result, result; + + /* do not handle any button events for headset without buttons */ + if (wcd->accessory_type == SND_JACK_HEADPHONE) + return IRQ_HANDLED; + + result = snd_soc_component_read32(comp, WCD9335_ANA_MBHC_RESULT_3); + btn_result = result & WCD9335_MBHC_BTN_RESULT_MASK; + + switch (btn_result) { + case 0xf: + snd_soc_jack_report(wcd->jack, SND_JACK_BTN_4, btn_mask); + break; + case 0x4: + snd_soc_jack_report(wcd->jack, SND_JACK_BTN_4, btn_mask); + break; + case 0x3: + snd_soc_jack_report(wcd->jack, SND_JACK_BTN_3, btn_mask); + break; + case 0x2: + snd_soc_jack_report(wcd->jack, SND_JACK_BTN_2, btn_mask); + break; + case 0x1: + snd_soc_jack_report(wcd->jack, SND_JACK_BTN_1, btn_mask); + break; + case 0x0: + /* handle BTN_0 specially for type detection */ + if (!wcd->detect_accessory_type) + snd_soc_jack_report(wcd->jack, + SND_JACK_BTN_0, btn_mask); + break; + default: + dev_err(comp->dev, + "Unexpected button press result (%x)", btn_result); + break; + } + + return IRQ_HANDLED; +} + +static irqreturn_t wcd9335_mbhc_bt_rel_irq(int irq, void *data) +{ + struct wcd9335_codec *wcd = data; + + + if (wcd->detect_accessory_type) { + u32 result = snd_soc_component_read32(wcd->component, + WCD9335_ANA_MBHC_RESULT_3); + + /* check if its BTN0 thats released */ + if (!(result & WCD9335_MBHC_BTN_RESULT_MASK)) + wcd->mbhc_btn0_released = true; + + } else { + if (wcd->accessory_type != SND_JACK_HEADPHONE) + snd_soc_jack_report(wcd->jack, 0, btn_mask); + } + + return IRQ_HANDLED; +} + static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) { struct wcd9335_codec *wcd = data; @@ -4037,11 +4177,95 @@ static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) return ret; } +static void wcd9335_program_btn_threshold(struct wcd9335_codec *wcd) +{ + int i, vth; + + for (i = 0; i < WCD9335_MBHC_MAX_BUTTONS; i++) { + vth = ((wcd->vref_btn[i] * 2) / 25) & 0x3F; + snd_soc_component_update_bits(wcd->component, + WCD9335_ANA_MBHC_BTN0 + i, + 0xFC, vth << 2); + } +} + +static void wcd9335_mbhc_initialise(struct wcd9335_codec *wcd) +{ + struct snd_soc_component *comp = wcd->component; + u32 plug_type = 0; + + snd_soc_component_update_bits(comp, WCD9335_MBHC_PLUG_DETECT_CTL, + WCD9335_MBHC_HSDET_PULLUP_CTL_MASK, + WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA); + + if (wcd->hphl_jack_type_normally_open) + plug_type |= WCD9335_MBHC_HPHL_PLUG_TYPE_NO; + + if (wcd->gnd_jack_type_normally_open) + plug_type |= WCD9335_MBHC_GND_PLUG_TYPE_NO; + + snd_soc_component_write(wcd->component, WCD9335_ANA_MBHC_MECH, + plug_type | + WCD9335_MBHC_L_DET_EN | + WCD9335_MBHC_HSL_PULLUP_COMP_EN | + WCD9335_MBHC_HPHL_100K_TO_GND_EN); + + /* Insertion debounce set to 96ms */ + snd_soc_component_write(wcd->component, + WCD9335_MBHC_PLUG_DETECT_CTL, + WCD9335_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS| + WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA); + /* Button Debounce set to 16ms */ + snd_soc_component_update_bits(wcd->component, WCD9335_MBHC_CTL_1, + WCD9335_MBHC_BTN_DBNC_MASK, + WCD9335_MBHC_BTN_DBNC_T_16_MS); + + /* enable bias distribution control */ + snd_soc_component_update_bits(comp, WCD9335_ANA_MBHC_ELECT, + WCD9335_ANA_MBHC_BIAS_EN_MASK, + WCD9335_ANA_MBHC_BIAS_EN); + + snd_soc_component_update_bits(wcd->component, + WCD9335_ANA_MBHC_ELECT, + WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK, + WCD9335_ANA_MBHC_BD_ISRC_100UA); + + /* enable MBHC clock */ + snd_soc_component_update_bits(wcd->component, WCD9335_MBHC_CTL_1, + WCD9335_MBHC_CTL_RCO_EN_MASK, + WCD9335_MBHC_CTL_RCO_EN); + + snd_soc_component_update_bits(wcd->component, WCD9335_MBHC_CTL_2, + WCD9335_MBHC_HS_VREF_CTL_MASK, + WCD9335_MBHC_HS_VREF_1P5_V); + + /* program HS_VREF value */ + wcd9335_program_btn_threshold(wcd); + /* Start FSM */ + snd_soc_component_update_bits(wcd->component, WCD9335_ANA_MBHC_ELECT, + BIT(7), BIT(7)); + + wcd->mbhc_btn0_released = false; + wcd->detect_accessory_type = true; +} + static struct wcd9335_irq wcd9335_irqs[] = { { .irq = WCD9335_IRQ_SLIMBUS, .handler = wcd9335_slimbus_irq, .name = "SLIM Slave", + }, { + .irq = WCD9335_IRQ_MBHC_SW_DET, + .handler = wcd9335_mbhc_sw_irq, + .name = "Headset Mech Insert Removal", + }, { + .irq = WCD9335_IRQ_MBHC_BUTTON_PRESS_DET, + .handler = wcd9335_mbhc_btn_press_irq, + .name = "Headset Button Press", + }, { + .irq = WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET, + .handler = wcd9335_mbhc_bt_rel_irq, + .name = "Headset Button Release", }, }; @@ -4850,6 +5074,7 @@ static void wcd9335_codec_init(struct snd_soc_component *component) wcd9335_codec_reg_init[i].val); wcd9335_enable_efuse_sensing(component); + wcd9335_mbhc_initialise(wcd); } static int wcd9335_codec_probe(struct snd_soc_component *component) @@ -4914,10 +5139,21 @@ static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, return clk_set_rate(wcd->mclk, freq); } +static int wcd9335_codec_set_jack(struct snd_soc_component *comp, + struct snd_soc_jack *jack, void *data) +{ + struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); + + wcd->jack = jack; + + return 0; +} + static const struct snd_soc_component_driver wcd9335_component_drv = { .probe = wcd9335_codec_probe, .remove = wcd9335_codec_remove, .set_sysclk = wcd9335_codec_set_sysclk, + .set_jack = wcd9335_codec_set_jack, .controls = wcd9335_snd_controls, .num_controls = ARRAY_SIZE(wcd9335_snd_controls), .dapm_widgets = wcd9335_dapm_widgets, @@ -4926,10 +5162,39 @@ static const struct snd_soc_component_driver wcd9335_component_drv = { .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), }; +static void of_parse_mbhc_data(struct device *dev, struct wcd9335_codec *wcd) +{ + int rval; + + if (of_property_read_bool(dev->of_node, + "qcom,hphl-jack-type-normally-open")) + wcd->hphl_jack_type_normally_open = true; + else + wcd->hphl_jack_type_normally_open = false; + + if (of_property_read_bool(dev->of_node, + "qcom,gnd-jack-type-normally-open")) + wcd->gnd_jack_type_normally_open = true; + else + wcd->gnd_jack_type_normally_open = false; + + wcd->mbhc_btn_enabled = true; + rval = of_property_read_u32_array(dev->of_node, + "qcom,mbhc-vthreshold", + &wcd->vref_btn[0], + WCD9335_MBHC_MAX_BUTTONS); + if (rval < 0) { + wcd->mbhc_btn_enabled = false; + dev_err(dev, "MBHC btn detection disabled\n"); + } +} + static int wcd9335_probe(struct wcd9335_codec *wcd) { struct device *dev = wcd->dev; + of_parse_mbhc_data(dev, wcd); + memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); @@ -5017,6 +5282,33 @@ static const struct regmap_irq wcd9335_codec_irqs[] = { .type_reg_mask = BIT(0), }, }, + [WCD9335_IRQ_MBHC_SW_DET] = { + .reg_offset = 1, + .mask = BIT(0), + .type = { + .type_reg_offset = 1, + .types_supported = IRQ_TYPE_EDGE_BOTH, + .type_reg_mask = BIT(0), + }, + }, + [WCD9335_IRQ_MBHC_BUTTON_PRESS_DET] = { + .reg_offset = 1, + .mask = BIT(2), + .type = { + .type_reg_offset = 1, + .types_supported = IRQ_TYPE_EDGE_BOTH, + .type_reg_mask = BIT(2), + }, + }, + [WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET] = { + .reg_offset = 1, + .mask = BIT(3), + .type = { + .type_reg_offset = 1, + .types_supported = IRQ_TYPE_EDGE_BOTH, + .type_reg_mask = BIT(3), + }, + } }; static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { From 306b3191906732cacc785b219d7e2d515f5aa75e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 13:34:05 +0200 Subject: [PATCH 114/174] ASoC: codecs: wcd9335: Fix headphone jack commit for new upstream kernel --- sound/soc/codecs/wcd9335.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index 0ba23b5d8ae4..914cd18cb4bd 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -3984,7 +3984,7 @@ static irqreturn_t wcd9335_mbhc_sw_irq(int irq, void *data) struct snd_soc_component *component = wcd->component; bool ins = false; - if (snd_soc_component_read32(component, WCD9335_ANA_MBHC_MECH) & + if (snd_soc_component_read(component, WCD9335_ANA_MBHC_MECH) & WCD9335_MBHC_MECH_DETECT_TYPE_MASK) ins = true; @@ -4000,7 +4000,7 @@ static irqreturn_t wcd9335_mbhc_sw_irq(int irq, void *data) * If no micbias is enabled, then enable 100uA internal * current source for Button detection */ - if (snd_soc_component_read32(component, WCD9335_ANA_MICB2) & + if (snd_soc_component_read(component, WCD9335_ANA_MICB2) & WCD9335_ANA_MICB2_ENABLE) btndet_curr_src = WCD9335_ANA_MBHC_BD_ISRC_OFF; else @@ -4048,7 +4048,7 @@ static irqreturn_t wcd9335_mbhc_btn_press_irq(int irq, void *data) if (wcd->accessory_type == SND_JACK_HEADPHONE) return IRQ_HANDLED; - result = snd_soc_component_read32(comp, WCD9335_ANA_MBHC_RESULT_3); + result = snd_soc_component_read(comp, WCD9335_ANA_MBHC_RESULT_3); btn_result = result & WCD9335_MBHC_BTN_RESULT_MASK; switch (btn_result) { @@ -4088,7 +4088,7 @@ static irqreturn_t wcd9335_mbhc_bt_rel_irq(int irq, void *data) if (wcd->detect_accessory_type) { - u32 result = snd_soc_component_read32(wcd->component, + u32 result = snd_soc_component_read(wcd->component, WCD9335_ANA_MBHC_RESULT_3); /* check if its BTN0 thats released */ From ed8cdf880311eb7196a935521f56de272e3235cf Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 16:40:05 +0200 Subject: [PATCH 115/174] arm64: dts: qcom: AUDIO WORKS oon MSM8998 Sony Yoshino platform!!! --- .../msm8998-sony-xperia-yoshino-maple.dts | 2 +- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 215 ++++++++++++++++-- 2 files changed, 202 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index cc6153167e8d..fdad49628970 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -79,7 +79,7 @@ function = "normal"; bias-disable; drive-push-pull; - output-low; + output-high; power-source = <1>; /* 1.8V */ qcom,drive-strength = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 8b0b78e02d4f..b61a4657eca5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -512,13 +512,11 @@ dai@2 { reg = <2>; }; -/* dai@3 { reg = <3>; - direction = <2>; - is-compress-dai; +// direction = <2>; +// is-compress-dai; }; -*/ }; &qusb2phy { @@ -729,6 +727,8 @@ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; + /* EAR-EN is NXP NX5L2750C */ + /* Downstream example &snd_9335 { qcom,msm-mbhc-hphl-swh = <1>; @@ -777,21 +777,27 @@ <&rpmcc RPM_SMD_LN_BB_CLK1>; #clock-cells = <0>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - interrupt-parent = <&tlmm>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr1"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 0>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; slim-ifc-dev = <&tasha_ifd>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-vthreshold = <1700>; + + /* On SoMC Yoshino, HPHL is normally open, GND normally closed */ + qcom,hphl-jack-type-normally-open; + //qcom,gnd-jack-type-normally-open; + #address-cells = <1>; #size-cells = <1>; #sound-dai-cells = <1>; @@ -839,20 +845,197 @@ }; }; + +/* NOTES */ +/* + # This is Dragonboard 820C + EnableSequence [ + cset "name='SLIM RX0 MUX' ZERO" + cset "name='SLIM RX1 MUX' ZERO" + cset "name='SLIM RX2 MUX' ZERO" + cset "name='SLIM RX3 MUX' ZERO" + cset "name='SLIM RX4 MUX' ZERO" + cset "name='SLIM RX5 MUX' AIF4_PB" + cset "name='SLIM RX6 MUX' AIF4_PB" + cset "name='SLIM RX7 MUX' ZERO" + cset "name='RX INT1_2 MUX' RX5" + cset "name='RX INT2_2 MUX' RX6" + ## gain to 0dB + cset "name='RX5 Digital Volume' 68" + ## gain to 0dB + cset "name='RX6 Digital Volume' 68" + cset "name='SLIMBUS_6_RX Audio Mixer MultiMedia2' 1" + cset "name='RX INT1 DEM MUX' CLSH_DSM_OUT" + cset "name='RX INT2 DEM MUX' CLSH_DSM_OUT" + ] + + +######### WORKS!!!!!! SHE SPEEEEEAKS!!!!!!! ######### +tinymix set "SLIM RX2 MUX" ZERO +tinymix set "SLIM RX3 MUX" ZERO +tinymix set "SLIM RX4 MUX" ZERO +tinymix set "SLIM RX5 MUX" ZERO +tinymix set "SLIM RX6 MUX" ZERO +tinymix set "SLIM RX7 MUX" ZERO +tinymix set "SLIM RX0 MUX" AIF1_PB +tinymix set "SLIM RX1 MUX" AIF1_PB +tinymix set "RX INT1_2 MUX" RX0 +tinymix set "RX INT2_2 MUX" RX1 +tinymix set "RX INT1_1 MIX1 INP0" RX0 +tinymix set "RX INT2_1 MIX1 INP0" RX1 +tinymix set "SLIMBUS_0_RX Audio Mixer MultiMedia1" 1 +tinymix set "RX INT1 DEM MUX" CLSH_DSM_OUT +tinymix set "RX INT2 DEM MUX" CLSH_DSM_OUT +tinymix set "SLIM TX0 MUX" DEC0 +tinymix set "AIF1_CAP Mixer SLIM TX0" 1 + +tinymix set "RX INT2_1 MIX1 INP0" RX1 +tinymix set "RX INT1_1 MIX1 INP0" RX0 +tinymix set "RX INT1_1 MIX1 INP0" RX2 +tinymix set "RX INT1_1 MIX1 INP0" RX0 +tinymix set "RX INT1_1 MIX1 INP0" RX2 +tinymix set "RX INT2_1 MIX1 INP0" RX2 +tinymix set "RX INT2_1 MIX1 INP0" RX1 +tinymix set "RX INT1_1 MIX1 INP0" RX0 +tinymix set "RX INT0_1 MIX1 INP0" RX0 +tinymix set "RX INT0_1 MIX1 INP0" RX1 +tinymix set "RX INT0_1 MIX1 INP0" RX2 +tinymix set "RX INT0_1 MIX1 INP0" RX0 +tinymix set "RX INT3_1 MIX1 INP0" RX0 +tinymix set "RX INT4_1 MIX1 INP0" RX0 +tinymix set "RX INT5_1 MIX1 INP0" RX0 +tinymix set "RX INT6_1 MIX1 INP0" RX1 +tinymix set "RX INT7_1 MIX1 INP0" RX1 +tinymix set "RX INT7_1 MIX1 INP0" RX1 +tinymix set "RX INT8_1 MIX1 INP0" RX1 +tinymix set "RX INT0_1 MIX1 INP1" RX0 +tinymix set "RX INT0_1 MIX1 INP1" RX2 +tinymix set "RX INT0_1 MIX1 INP1" RX0 +tinymix set "RX INT1_1 MIX1 INP1" RX0 +tinymix set "RX INT2_1 MIX1 INP1" RX0 +tinymix set "RX INT3_1 MIX1 INP1" RX0 +tinymix set "RX INT4_1 MIX1 INP1" RX0 +tinymix set "RX INT5_1 MIX1 INP1" RX0 +tinymix set "RX INT6_1 MIX1 INP1" RX0 +tinymix set "RX INT7_1 MIX1 INP1" RX0 +tinymix set "RX INT8_1 MIX1 INP1" RX0 +tinymix set "RX INT0_1 MIX1 INP2" RX1 +tinymix set "RX INT1_1 MIX1 INP2" RX1 +tinymix set "RX INT2_1 MIX1 INP2" RX1 +tinymix set "RX INT3_1 MIX1 INP2" RX1 +tinymix set "RX INT4_1 MIX1 INP2" RX1 +tinymix set "RX INT5_1 MIX1 INP2" RX1 +tinymix set "RX INT6_1 MIX1 INP2" RX1 +tinymix set "RX INT7_1 MIX1 INP2" RX1 +tinymix set "RX INT8_1 MIX1 INP2" RX1 +tinymix set "RX INT8_1 MIX1 INP2" RX0 +tinymix set "RX INT7_1 MIX1 INP2" RX0 +tinymix set "RX INT6_1 MIX1 INP2" RX0 + +tinymix set "RX0 Digital Volume" 80 +tinymix set "RX1 Digital Volume" 80 +tinymix set "RX2 Digital Volume" 80 + +*/ + &sound { compatible = "qcom,msm8998-sndcard"; model = "Sony-Xperia-Yoshino"; - audio-routing = "RX_BIAS", "MCLK", + /* Audio routing including WSA amp speakers */ +/* audio-routing = "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", "AMIC3", "MIC BIAS3", "DMIC0", "MIC BIAS1", "DMIC4", "MIC BIAS4", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback"; + "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", + "MultiMedia3 Capture", "MM_UL3"; +*/ + + /* Basic routing, 3.5mm jack only */ + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "DMIC0", "MIC BIAS1", + "DMIC4", "MIC BIAS4", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", + "MultiMedia3 Capture", "MM_UL3"; + +/* + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ mm1-dai-link { + /* Deep Buffer playback for SLIM{0,7}, BT, USBAUDIO, AFE, DP, HDMI */ link-name = "MultiMedia1"; cpu { sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; @@ -860,6 +1043,7 @@ }; mm2-dai-link { + /* Multichannel playback for HDMI and DP */ link-name = "MultiMedia2"; cpu { sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; @@ -867,6 +1051,7 @@ }; mm3-dai-link { + /* Ultra Low Latency playback for SLIM0, HDMI, and DP */ link-name = "MultiMedia3"; cpu { sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; @@ -884,7 +1069,9 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9335 0>; + /* Support only sound through 3.5mm for now: soundwire is currently unavailable */ + //sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9335 0>; + sound-dai = <&wcd9335 0>; }; }; From ed0bb1af2a1c4c6b5a205752ee87a155036435ee Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 20:38:28 +0200 Subject: [PATCH 116/174] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for MSM8998 and SDM630 Similarly to MSM8996 DragonBoard 820c, MSM8998 and SDM630 are equipped with Adreno 5xx series, which doesn't have separate pagetables support at the moment of writing. Skip the TTBR1 quirk for these two SoCs as to get Adreno in a usable state. --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index d32fe3e267d8..de5b61520c08 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -184,7 +184,9 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; - if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2") || + of_device_is_compatible(np, "qcom,msm8998-smmu-v2") || + of_device_is_compatible(np, "qcom,sdm630-smmu-v2")) return false; return true; From 0bc0889e0277ec3d1817e80f31736c40b1f031ed Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 20:42:48 +0200 Subject: [PATCH 117/174] iommu/arm-smmu-qcom: Add MSM8998 and SDM660 mss compatibles for identity Add MSM8998 and SDM660's mss-pil compatibles to switch the default iommu domain type to IDENTITY, as similarly required by SDM845 and others. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index de5b61520c08..33309554e394 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -232,11 +232,13 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, { .compatible = "qcom,mdp4" }, { .compatible = "qcom,mdss" }, + { .compatible = "qcom,msm8998-mss-pil" }, { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7180-mss-pil" }, { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc7280-mss-pil" }, { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sdm660-mss-pil" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, { } From 5b33bb93625bf5af0df3c98303daa72ea22b59a6 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 15:58:16 +0200 Subject: [PATCH 118/174] ASoC: wcd9335: various tests Originally from: c215a022 --- sound/soc/codecs/wcd9335.c | 15 ++++++++++++--- sound/soc/codecs/wcd9335.h | 6 ++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index 914cd18cb4bd..c7093decd7c6 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -493,7 +493,7 @@ static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, - {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, + {WCD9335_HPH_OCP_CTL, 0xFF, 0x7A}, /*downstream is ff 7a */ {WCD9335_HPH_L_TEST, 0x01, 0x01}, {WCD9335_HPH_R_TEST, 0x01, 0x01}, {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, @@ -506,6 +506,13 @@ static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, + + {WCD9335_DIFF_LO_CORE_OUT_PROG, 0xFC, 0xA0}, + {WCD9335_SE_LO_COM1, 0xFF, 0xC0}, + {WCD9335_CDC_RX3_RX_PATH_SEC0, 0xFC, 0xF4}, + {WCD9335_CDC_RX4_RX_PATH_SEC0, 0xFC, 0xF4}, + {WCD9335_CDC_RX5_RX_PATH_SEC0, 0xFC, 0xF8}, + {WCD9335_CDC_RX6_RX_PATH_SEC0, 0xFC, 0xF8}, }; /* Cutoff frequency for high pass filter */ @@ -3753,11 +3760,12 @@ static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); int hph_mode = wcd->hph_mode; - +pr_err("%s\n", __func__); switch (event) { case SND_SOC_DAPM_PRE_PMU: break; case SND_SOC_DAPM_POST_PMU: +pr_err("%s post pmu\n", __func__); /* * 7ms sleep is required after PA is enabled as per * HW requirement @@ -3781,6 +3789,7 @@ static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, break; case SND_SOC_DAPM_PRE_PMD: +pr_err("%s pre pmd\n", __func__); wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); break; case SND_SOC_DAPM_POST_PMD: @@ -3902,7 +3911,7 @@ static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); int hph_mode = wcd->hph_mode; - +pr_err("%s\n", __func__); switch (event) { case SND_SOC_DAPM_PRE_PMU: break; diff --git a/sound/soc/codecs/wcd9335.h b/sound/soc/codecs/wcd9335.h index 490fc44144a2..d54d6b1aedea 100644 --- a/sound/soc/codecs/wcd9335.h +++ b/sound/soc/codecs/wcd9335.h @@ -368,8 +368,10 @@ #define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2) #define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea) #define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb) +#define WCD9335_DIFF_LO_CORE_OUT_PROG WCD9335_REG(0x06, 0x0ef) #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1) #define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2) +#define WCD9335_SE_LO_COM1 WCD9335_REG(0x06, 0x0f6) #define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8) #define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9) #define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa) @@ -495,6 +497,7 @@ #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082) #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083) #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084) +#define WCD9335_CDC_RX3_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x085) #define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091) #define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092) #define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094) @@ -502,6 +505,7 @@ #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096) #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097) #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098) +#define WCD9335_CDC_RX4_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x099) #define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5) #define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6) #define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8) @@ -509,6 +513,7 @@ #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa) #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab) #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac) +#define WCD9335_CDC_RX5_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x0ad) #define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9) #define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba) #define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc) @@ -516,6 +521,7 @@ #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be) #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf) #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0) +#define WCD9335_CDC_RX6_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x0c1) #define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd) #define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce) #define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf) From 0b49adafb0b593c0898d825a83e6db97dae5c306 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 16:00:32 +0200 Subject: [PATCH 119/174] arm64: dts: qcom: msm8998-xperia: various tests Originally from: c215a022 --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index b61a4657eca5..3177012625a7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -778,12 +778,13 @@ #clock-cells = <0>; interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1"; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; slim-ifc-dev = <&tasha_ifd>; From e3fa3e3ed1f2a2ebba3e4bfcb19eee95cfa36f0f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 11 Aug 2021 21:28:34 +0200 Subject: [PATCH 120/174] adreno 5xx: TTBR1 extravaganza on MSM8998 (JAMI: fixup for 5.16) --- .../msm8998-sony-xperia-yoshino-maple.dts | 4 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 66 ++++++++++++++++++- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 +- 4 files changed, 69 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index fdad49628970..7a730ae623b5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -107,8 +107,8 @@ status = "okay"; //qcom,auto-string-detection; - qcom,num-strings = <4>; - qcom,enabled-strings = <0 1 2 3>; + qcom,num-strings = <3>; + qcom,enabled-strings = <0 1 2>; }; &wcd9335 { diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 3d28fcf841a6..e649ab137e49 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -121,6 +121,48 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit msm_gpu_retire(gpu); } +static void a5xx_set_pagetable(struct a5xx_gpu *a5xx_gpu, + struct msm_ringbuffer *ring, struct msm_file_private *ctx) +{ + phys_addr_t ttbr; + u32 asid; + u64 memptr = rbmemptr(ring, ttbr0); + + if (ctx == a5xx_gpu->cur_ctx) + return; + + if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) + return; + + /* Execute the table update */ + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 3); + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); + + OUT_RING(ring, + CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | + CP_SMMU_TABLE_UPDATE_1_ASID(asid)); + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); + + /* + * Write the new TTBR0 to the memstore. This is good for debugging. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); + OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); + + /* + * And finally, trigger a uche flush to be sure there isn't anything + * lingering in that part of the GPU + */ + + OUT_PKT7(ring, CP_EVENT_WRITE, 1); + OUT_RING(ring, 0x31); + + a5xx_gpu->cur_ctx = ctx; +} + static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -151,13 +193,17 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) OUT_RING(ring, 1); /* Enable local preemption for finegrain preemption */ - OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); - OUT_RING(ring, 0x02); + //OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + //OUT_RING(ring, 0x02); + OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1); + OUT_RING(ring, 0x01); /* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */ OUT_PKT7(ring, CP_YIELD_ENABLE, 1); OUT_RING(ring, 0x02); + a5xx_set_pagetable(a5xx_gpu, ring, submit->queue->ctx); + /* Submit the commands */ for (i = 0; i < submit->nr_cmds; i++) { switch (submit->cmd[i].type) { @@ -942,6 +988,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) a5xx_preempt_fini(gpu); gpu->nr_rings = 1; } + a5xx_gpu->cur_ctx = NULL; a5xx_preempt_hw_init(gpu); @@ -1697,6 +1744,20 @@ static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR); } +static struct msm_gem_address_space * +a5xx_create_private_address_space(struct msm_gpu *gpu) +{ + struct msm_mmu *mmu; + + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); + + if (IS_ERR(mmu)) + return ERR_CAST(mmu); + + return msm_gem_address_space_create(mmu, + "gpu", 0x100000000ULL, 0x1ffffffffULL); +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -1718,6 +1779,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_get = a5xx_gpu_state_get, .gpu_state_put = a5xx_gpu_state_put, .create_address_space = adreno_iommu_create_address_space, + .create_private_address_space = a5xx_create_private_address_space, .get_rptr = a5xx_get_rptr, }, .get_timestamp = a5xx_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index c7187bcc5e90..781b759918e9 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -29,6 +29,7 @@ struct a5xx_gpu { struct msm_ringbuffer *cur_ring; struct msm_ringbuffer *next_ring; + struct msm_file_private *cur_ctx; struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS]; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 33309554e394..1645a8e7d93b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -182,13 +182,13 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) { +/* const struct device_node *np = smmu->dev->of_node; - if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2") || of_device_is_compatible(np, "qcom,msm8998-smmu-v2") || of_device_is_compatible(np, "qcom,sdm630-smmu-v2")) return false; - +*/ return true; } From c53aa1d6d4586787ebd41aa82b194165739fb7a0 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 16:08:09 +0200 Subject: [PATCH 121/174] [ANNOTATION] Base @ angelo/5.14-msm8998-audio-working I also rebased this tree on the linus/v5.17-rc1 tag and while at it finally dropped changes irrelevant to msm8998. From 61491d1901369551918e5a71235a275682931cfe Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 10 Dec 2021 02:26:52 +0000 Subject: [PATCH 122/174] dt-bindings: input: add Qualcomm SPMI haptics driver Add bindings for qcom PMIC SPMI haptics driver. Signed-off-by: Caleb Connolly --- .../bindings/input/qcom,spmi-haptics.yaml | 123 ++++++++++++++++++ include/dt-bindings/input/qcom,spmi-haptics.h | 32 +++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml create mode 100644 include/dt-bindings/input/qcom,spmi-haptics.h diff --git a/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml b/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml new file mode 100644 index 000000000000..d02a30c7554c --- /dev/null +++ b/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2020 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/qcom,spmi-haptics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc PMI8998 spmi haptics + +maintainers: + - Caleb Connolly + +description: | + Qualcomm SPMI haptics is a peripheral on some QTI PMICs. It supports linear resonant + actuators and eccentric rotating mass type haptics commonly found in mobile devices. + It supports multiple sources of wave data such as an internal buffer, direct play + (from kernel or userspace) as well as an audio output mode. + +properties: + compatible: + items: + - enum: + - qcom,pmi8998-haptics + - qcom,pmi8996-haptics + - qcom,pmi8941-haptics + + reg: + maxItems: 1 + + interrupts: + items: + - description: short circuit interrupt + - description: play interrupt + + interrupt-names: + items: + - const: short + - const: play + + qcom,actuator-type: + description: | + The type of actuator attached to the hardware. + Allowed values are, + 0 - HAP_TYPE_LRA + 1 - HAP_TYPE_ERM + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + default: 0 + + qcom,wave-shape: + description: | + Selects the wave shape to use. + Allowed values are, + 0 - HAP_WAVE_SINE + 1 - HAP_WAVE_SQUARE + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + default: 0 + + qcom,play-mode: + description: | + Selects the play mode to use. + Allowed values are, + 0 - HAP_PLAY_DIRECT + 1 - HAP_PLAY_BUFFER + 2 - HAP_PLAY_AUDIO + 3 - HAP_PLAY_PWM + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + default: 2 + + qcom,wave-play-rate-us: + description: | + Wave sample durection in microseconds, 1/f where f + is the resonant frequency of the actuator. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20475 + + qcom,brake-pattern: + minItems: 4 + maxItems: 4 + description: | + The brake pattern are the strengths of the pattern + used to brake the haptics. Allowed values are, + 0 - 0V + 1 - Vmax/4 + 2 - Vmax/2 + 3 - Vmax + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0x3, 0x3, 0x2, 0x1] + +required: + - compatible + - reg + - interrupts + - qcom,wave-play-rate-us + +additionalProperties: false + +examples: + - | + #include + #include + + spmi { + #address-cells = <1>; + #size-cells = <0>; + pmi8998_haptics: haptics@c000 { + compatible = "qcom,pmi8998-haptics"; + reg = <0xc000>; + + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "short", "play"; + + qcom,wave-shape = ; + qcom,play-mode = ; + qcom,brake-pattern = <0x3 0x3 0x2 0x1>; + + status = "disabled"; + }; + }; diff --git a/include/dt-bindings/input/qcom,spmi-haptics.h b/include/dt-bindings/input/qcom,spmi-haptics.h new file mode 100644 index 000000000000..14a7e7d1471e --- /dev/null +++ b/include/dt-bindings/input/qcom,spmi-haptics.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for pmi8998 SPMI haptics options. + */ + +#ifndef _DT_BINDINGS_QCOM_PMIC_SPMI_HAPTICS_ +#define _DT_BINDINGS_QCOM_PMIC_SPMI_HAPTICS_ + +// Actuator types +#define HAP_TYPE_LRA 0 +#define HAP_TYPE_ERM 1 + +// LRA Wave type +#define HAP_WAVE_SINE 0 +#define HAP_WAVE_SQUARE 1 + +// Play modes +#define HAP_PLAY_DIRECT 0 +#define HAP_PLAY_BUFFER 1 +#define HAP_PLAY_AUDIO 2 +#define HAP_PLAY_PWM 3 + +#define HAP_PLAY_MAX HAP_PLAY_PWM + +// Auto resonance type +#define HAP_AUTO_RES_NONE 0 +#define HAP_AUTO_RES_ZXD 1 +#define HAP_AUTO_RES_QWD 2 +#define HAP_AUTO_RES_MAX_QWD 3 +#define HAP_AUTO_RES_ZXD_EOP 4 + +#endif /* _DT_BINDINGS_QCOM_PMIC_SPMI_HAPTICS_ */ From 769df9c28b65fb8e94236803a40ce689949d9001 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 10 Dec 2021 02:26:56 +0000 Subject: [PATCH 123/174] input: add Qualcomm SPMI haptics driver Add support for the haptics found in pmi8998 and related PMICs. Based on the ff-memless interface. Currently this driver provides a partial implementation of hardware features. This driver only supports LRAs (Linear Resonant Actuators) in the "buffer" mode with a single wave pattern. Signed-off-by: Caleb Connolly --- drivers/input/misc/Kconfig | 12 + drivers/input/misc/Makefile | 1 + drivers/input/misc/qcom-spmi-haptics.c | 977 +++++++++++++++++++++++++ 3 files changed, 990 insertions(+) create mode 100644 drivers/input/misc/qcom-spmi-haptics.c diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index dd5227cf8696..b759d9719695 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -186,6 +186,18 @@ config INPUT_PMIC8XXX_PWRKEY To compile this driver as a module, choose M here: the module will be called pmic8xxx-pwrkey. +config INPUT_QCOM_SPMI_HAPTICS + tristate "Qualcomm SPMI HAPTICS" + depends on ARCH_QCOM + depends on SPMI + select INPUT_FF_MEMLESS + help + This option enables support for the haptics found in pmi8998 and + related PMICs. Based on the ff-memless interface. + + To compile this driver as module, choose M here: the + module will be called qcom_spmi_haptics. + config INPUT_SPARCSPKR tristate "SPARC Speaker support" depends on PCI && SPARC64 diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index b92c53a6b5ae..e58110893e56 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o obj-$(CONFIG_INPUT_POWERMATE) += powermate.o obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o obj-$(CONFIG_INPUT_PWM_VIBRA) += pwm-vibra.o +obj-$(CONFIG_INPUT_QCOM_SPMI_HAPTICS) += qcom-spmi-haptics.o obj-$(CONFIG_INPUT_RAVE_SP_PWRBUTTON) += rave-sp-pwrbutton.o obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o diff --git a/drivers/input/misc/qcom-spmi-haptics.c b/drivers/input/misc/qcom-spmi-haptics.c new file mode 100644 index 000000000000..bfed023c3816 --- /dev/null +++ b/drivers/input/misc/qcom-spmi-haptics.c @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Caleb Connolly + * Qualcomm QPMI haptics driver for pmi8998 and related PMICs. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define HAP_STATUS_1_REG 0x0A +#define HAP_BUSY_BIT BIT(1) +#define SC_FLAG_BIT BIT(3) +#define AUTO_RES_ERROR_BIT BIT(4) + +#define HAP_LRA_AUTO_RES_LO_REG 0x0B +#define HAP_LRA_AUTO_RES_HI_REG 0x0C + +#define HAP_EN_CTL_REG 0x46 +#define HAP_EN_BIT BIT(7) + +#define HAP_EN_CTL2_REG 0x48 +#define BRAKE_EN_BIT BIT(0) + +#define HAP_AUTO_RES_CTRL_REG 0x4B +#define AUTO_RES_EN_BIT BIT(7) +#define AUTO_RES_ERR_RECOVERY_BIT BIT(3) +#define AUTO_RES_EN_FLAG_BIT BIT(0) + +#define HAP_CFG1_REG 0x4C +#define HAP_ACT_TYPE_MASK BIT(0) + +#define HAP_CFG2_REG 0x4D +#define HAP_LRA_RES_TYPE_MASK BIT(0) + +#define HAP_SEL_REG 0x4E +#define HAP_WF_SOURCE_MASK GENMASK(5, 4) +#define HAP_WF_SOURCE_SHIFT 4 + +#define HAP_LRA_AUTO_RES_REG 0x4F +#define LRA_AUTO_RES_MODE_MASK GENMASK(6, 4) +#define LRA_AUTO_RES_MODE_SHIFT 4 +#define LRA_HIGH_Z_MASK GENMASK(3, 2) +#define LRA_HIGH_Z_SHIFT 2 +#define LRA_RES_CAL_MASK GENMASK(1, 0) +#define HAP_RES_CAL_PERIOD_MIN 4 +#define HAP_RES_CAL_PERIOD_MAX 32 + +#define HAP_VMAX_CFG_REG 0x51 +#define HAP_VMAX_OVD_BIT BIT(6) +#define HAP_VMAX_MASK GENMASK(5, 1) +#define HAP_VMAX_SHIFT 1 + +#define HAP_ILIM_CFG_REG 0x52 +#define HAP_ILIM_SEL_MASK BIT(0) +#define HAP_ILIM_400_MA 0 +#define HAP_ILIM_800_MA 1 + +#define HAP_SC_DEB_REG 0x53 +#define HAP_SC_DEB_MASK GENMASK(2, 0) +#define HAP_SC_DEB_CYCLES_MIN 0 +#define HAP_DEF_SC_DEB_CYCLES 8 +#define HAP_SC_DEB_CYCLES_MAX 32 + +#define HAP_RATE_CFG1_REG 0x54 +#define HAP_RATE_CFG1_MASK GENMASK(7, 0) +#define HAP_RATE_CFG2_SHIFT 8 + +#define HAP_RATE_CFG2_REG 0x55 +#define HAP_RATE_CFG2_MASK GENMASK(3, 0) + +#define HAP_SC_CLR_REG 0x59 +#define SC_CLR_BIT BIT(0) + +#define HAP_BRAKE_REG 0x5C +#define HAP_BRAKE_PAT_MASK 0x3 + +#define HAP_WF_REPEAT_REG 0x5E +#define WF_REPEAT_MASK GENMASK(6, 4) +#define WF_REPEAT_SHIFT 4 +#define WF_REPEAT_MIN 1 +#define WF_REPEAT_MAX 128 +#define WF_S_REPEAT_MASK GENMASK(1, 0) +#define WF_S_REPEAT_MIN 1 +#define WF_S_REPEAT_MAX 8 + +#define HAP_WF_S1_REG 0x60 +#define HAP_WF_SIGN_BIT BIT(7) +#define HAP_WF_OVD_BIT BIT(6) +#define HAP_WF_SAMP_MAX GENMASK(5, 1) +#define HAP_WF_SAMPLE_LEN 8 + +#define HAP_PLAY_REG 0x70 +#define HAP_PLAY_BIT BIT(7) +#define HAP_PAUSE_BIT BIT(0) + +#define HAP_SEC_ACCESS_REG 0xD0 +#define HAP_SEC_ACCESS_UNLOCK 0xA5 + +#define HAP_TEST2_REG 0xE3 + + +#define HAP_VMAX_MIN_MV 116 +#define HAP_VMAX_MAX_MV 3596 +#define HAP_VMAX_MAX_MV_STRONG 3596 + +#define HAP_WAVE_PLAY_RATE_MIN_US 0 +#define HAP_WAVE_PLAY_RATE_MAX_US 20475 +#define HAP_WAVE_PLAY_TIME_MAX_MS 15000 + +#define AUTO_RES_ERR_POLL_TIME_NS (20 * NSEC_PER_MSEC) +#define HAPTICS_BACK_EMF_DELAY_US 20000 + +#define HAP_BRAKE_PAT_LEN 4 +#define HAP_WAVE_SAMP_LEN 8 +#define NUM_WF_SET 4 +#define HAP_WAVE_SAMP_SET_LEN (HAP_WAVE_SAMP_LEN * NUM_WF_SET) +#define HAP_RATE_CFG_STEP_US 5 + +#define SC_MAX_COUNT 5 +#define SC_COUNT_RST_DELAY_US 1000000 + +enum hap_play_control { + HAP_STOP, + HAP_PAUSE, + HAP_PLAY, +}; + +/** + * struct spmi_haptics - struct for spmi haptics data. + * + * @dev: Our device parent. + * @regmap: Register map for the hardware block. + * @haptics_input_dev: The input device used to receive events. + * @work: Work struct to play effects. + * @base: Base address of the regmap. + * @active: Atomic value used to track if haptics are currently playing. + * @play_irq: Fired to load the next wave pattern. + * @sc_irq: Short circuit irq. + * @last_sc_time: Time since the short circuit IRQ last fired. + * @sc_count: Number of times the short circuit IRQ has fired in this interval. + * @actuator_type: The type of actuator in use. + * @wave_shape: The shape of the waves to use (sine or square). + * @play_mode: The play mode to use (direct, buffer, pwm, audio). + * @magnitude: The strength we should be playing at. + * @vmax: Max voltage to use when playing. + * @current_limit: The current limit for this hardware (400mA or 800mA). + * @play_wave_rate: The wave rate to use for this hardware. + * @wave_samp: The array of wave samples to write for buffer mode. + * @brake_pat: The pattern to apply when braking. + * @play_lock: Lock to be held when updating the hardware state. + */ +struct spmi_haptics { + struct device *dev; + struct regmap *regmap; + struct input_dev *haptics_input_dev; + struct work_struct work; + u32 base; + + atomic_t active; + + int play_irq; + int sc_irq; + ktime_t last_sc_time; + u8 sc_count; + + u8 actuator_type; + u8 wave_shape; + u8 play_mode; + int magnitude; + u32 vmax; + u32 current_limit; + u32 play_wave_rate; + + u32 wave_samp[HAP_WAVE_SAMP_SET_LEN]; + u8 brake_pat[HAP_BRAKE_PAT_LEN]; + + struct mutex play_lock; +}; + +static inline bool is_secure_addr(u16 addr) +{ + return (addr & 0xFF) > 0xD0; +} + +static int spmi_haptics_read(struct spmi_haptics *haptics, + u16 addr, u8 *val, int len) +{ + int ret; + + ret = regmap_bulk_read(haptics->regmap, addr, val, len); + if (ret < 0) + dev_err(haptics->dev, "Error reading address: 0x%x, ret %d\n", addr, ret); + + return ret; +} + +static int spmi_haptics_write(struct spmi_haptics *haptics, + u16 addr, u8 *val, int len) +{ + int ret, i; + + if (is_secure_addr(addr)) { + for (i = 0; i < len; i++) { + dev_dbg(haptics->dev, "%s: unlocking for addr: 0x%x, val: 0x%x", __func__, + addr, val[i]); + ret = regmap_write(haptics->regmap, + haptics->base + HAP_SEC_ACCESS_REG, HAP_SEC_ACCESS_UNLOCK); + if (ret < 0) { + dev_err(haptics->dev, "Error writing unlock code, ret %d\n", + ret); + return ret; + } + + ret = regmap_write(haptics->regmap, addr + i, val[i]); + if (ret < 0) { + dev_err(haptics->dev, "Error writing address 0x%x, ret %d\n", + addr + i, ret); + return ret; + } + } + } else { + if (len > 1) + ret = regmap_bulk_write(haptics->regmap, addr, val, len); + else + ret = regmap_write(haptics->regmap, addr, *val); + } + + if (ret < 0) + dev_err(haptics->dev, "%s: Error writing address: 0x%x, ret %d\n", + __func__, addr, ret); + + return ret; +} + +static int spmi_haptics_write_masked(struct spmi_haptics *haptics, + u16 addr, u8 mask, u8 val) +{ + int ret; + + if (is_secure_addr(addr)) { + ret = regmap_write(haptics->regmap, + haptics->base + HAP_SEC_ACCESS_REG, HAP_SEC_ACCESS_UNLOCK); + if (ret < 0) { + dev_err(haptics->dev, "Error writing unlock code - ret %d\n", ret); + return ret; + } + } + + ret = regmap_update_bits(haptics->regmap, addr, mask, val); + if (ret < 0) + dev_err(haptics->dev, "Error writing address: 0x%x - ret %d\n", addr, ret); + + return ret; +} + +static bool is_haptics_idle(struct spmi_haptics *haptics) +{ + int ret; + u8 val; + + if (haptics->play_mode == HAP_PLAY_DIRECT || + haptics->play_mode == HAP_PLAY_PWM) + return true; + + ret = spmi_haptics_read(haptics, haptics->base + HAP_STATUS_1_REG, &val, 1); + if (ret < 0 || (val & HAP_BUSY_BIT)) + return false; + + return true; +} + +static int spmi_haptics_module_enable(struct spmi_haptics *haptics, bool enable) +{ + u8 val; + + dev_dbg(haptics->dev, "Setting module enable: %d", enable); + + val = enable ? HAP_EN_BIT : 0; + return spmi_haptics_write(haptics, haptics->base + HAP_EN_CTL_REG, &val, 1); +} + +static int spmi_haptics_write_vmax(struct spmi_haptics *haptics) +{ + u8 val = 0; + u32 vmax_mv = haptics->vmax; + + vmax_mv = clamp_t(u32, vmax_mv, HAP_VMAX_MIN_MV, HAP_VMAX_MAX_MV); + + dev_dbg(haptics->dev, "Setting vmax to: %d", vmax_mv); + + val = DIV_ROUND_CLOSEST(vmax_mv, HAP_VMAX_MIN_MV); + val = FIELD_PREP(HAP_VMAX_MASK, val); + + // TODO: pm660 can enable overdrive here + + return spmi_haptics_write_masked(haptics, haptics->base + HAP_VMAX_CFG_REG, + HAP_VMAX_MASK | HAP_WF_OVD_BIT, val); +} + +static int spmi_haptics_write_current_limit(struct spmi_haptics *haptics) +{ + haptics->current_limit = clamp_t(u32, haptics->current_limit, + HAP_ILIM_400_MA, HAP_ILIM_800_MA); + + dev_dbg(haptics->dev, "Setting current_limit to: 0x%x", haptics->current_limit); + + return spmi_haptics_write_masked(haptics, haptics->base + HAP_ILIM_CFG_REG, + HAP_ILIM_SEL_MASK, haptics->current_limit); +} + +static int spmi_haptics_write_play_mode(struct spmi_haptics *haptics) +{ + u8 val = 0; + + if (!is_haptics_idle(haptics)) + return -EBUSY; + + dev_dbg(haptics->dev, "Setting play_mode to: 0x%x", haptics->play_mode); + + val = FIELD_PREP(HAP_WF_SOURCE_MASK, haptics->play_mode); + return spmi_haptics_write_masked(haptics, haptics->base + HAP_SEL_REG, + HAP_WF_SOURCE_MASK, val); + +} + +static int spmi_haptics_write_play_rate(struct spmi_haptics *haptics, u16 play_rate) +{ + u8 val[2]; + + dev_dbg(haptics->dev, "Setting play_rate to: %d", play_rate); + + val[0] = FIELD_PREP(HAP_RATE_CFG1_MASK, play_rate); + val[1] = FIELD_PREP(HAP_RATE_CFG2_MASK, play_rate >> HAP_RATE_CFG2_SHIFT); + return spmi_haptics_write(haptics, haptics->base + HAP_RATE_CFG1_REG, val, 2); +} + +/* + * spmi_haptics_set_auto_res() - Auto resonance + * allows the haptics to automatically adjust the + * speed of the oscillation in order to maintain + * the resonant frequency. + */ +static int spmi_haptics_set_auto_res(struct spmi_haptics *haptics, bool enable) +{ + u8 val; + + // LRAs are the only type to support auto res + if (haptics->actuator_type != HAP_TYPE_LRA) + return 0; + + val = enable ? AUTO_RES_EN_BIT : 0; + + return spmi_haptics_write_masked(haptics, haptics->base + HAP_TEST2_REG, + AUTO_RES_EN_BIT, val); +} + +static int spmi_haptics_write_brake(struct spmi_haptics *haptics) +{ + int ret, i; + u8 val; + + dev_dbg(haptics->dev, "Configuring brake pattern"); + + ret = spmi_haptics_write_masked(haptics, haptics->base + HAP_EN_CTL2_REG, + BRAKE_EN_BIT, 1); + if (ret < 0) + return ret; + + for (i = HAP_BRAKE_PAT_LEN - 1, val = 0; i >= 0; i--) { + u8 p = haptics->brake_pat[i] & HAP_BRAKE_PAT_MASK; + + val |= p << (i * 2); + } + + return spmi_haptics_write(haptics, haptics->base + HAP_BRAKE_REG, &val, 1); +} + +static int spmi_haptics_write_buffer_config(struct spmi_haptics *haptics) +{ + u8 buf[HAP_WAVE_SAMP_LEN]; + int i; + + dev_dbg(haptics->dev, "Writing buffer config"); + + for (i = 0; i < HAP_WAVE_SAMP_LEN; i++) + buf[i] = haptics->wave_samp[i]; + + return spmi_haptics_write(haptics, haptics->base + HAP_WF_S1_REG, buf, + HAP_WAVE_SAMP_LEN); +} + +static int spmi_haptics_write_wave_repeat(struct spmi_haptics *haptics) +{ + u8 val, mask; + + /* The number of times to repeat each wave */ + mask = WF_REPEAT_MASK | WF_S_REPEAT_MASK; + val = FIELD_PREP(WF_REPEAT_MASK, 0) | + FIELD_PREP(WF_S_REPEAT_MASK, 0); + + return spmi_haptics_write_masked(haptics, haptics->base + HAP_WF_REPEAT_REG, + mask, val); +} + +static int spmi_haptics_write_play_control(struct spmi_haptics *haptics, + enum hap_play_control ctrl) +{ + u8 val; + + switch (ctrl) { + case HAP_STOP: + val = 0; + break; + case HAP_PAUSE: + val = HAP_PAUSE_BIT; + break; + case HAP_PLAY: + val = HAP_PLAY_BIT; + break; + default: + return 0; + } + + dev_dbg(haptics->dev, "haptics play ctrl: %d\n", ctrl); + return spmi_haptics_write(haptics, haptics->base + HAP_PLAY_REG, &val, 1); +} + +/* + * This IRQ is fired to tell us to load the next wave sample set. + * As we only currently support a single sample set, it's unused. + */ +static irqreturn_t spmi_haptics_play_irq_handler(int irq, void *data) +{ + struct spmi_haptics *haptics = data; + + dev_dbg(haptics->dev, "play_irq triggered"); + + return IRQ_HANDLED; +} + +/** + * spmi_haptics_sc_irq_handler() - short circuit irq handler + * Fires every ~50ms whilst the haptics are active. + * If the SC_FLAG_BIT is set then that means there isn't a short circuit + * and we just need to clear the IRQ to indicate that the device should + * keep vibrating. + * + * Otherwise, it means a short circuit situation has occurred. + * + * @irq: irq number + * @data: haptics data + * Returns: IRQ_HANDLED + */ +static irqreturn_t spmi_haptics_sc_irq_handler(int irq, void *data) +{ + struct spmi_haptics *haptics = data; + int ret; + u8 val; + s64 sc_delta_time_us; + ktime_t temp; + + ret = spmi_haptics_read(haptics, haptics->base + HAP_STATUS_1_REG, &val, 1); + if (ret < 0) + return IRQ_HANDLED; + + if (!(val & SC_FLAG_BIT)) { + haptics->sc_count = 0; + return IRQ_HANDLED; + } + + temp = ktime_get(); + sc_delta_time_us = ktime_us_delta(temp, haptics->last_sc_time); + haptics->last_sc_time = temp; + + if (sc_delta_time_us > SC_COUNT_RST_DELAY_US) + haptics->sc_count = 0; + else + haptics->sc_count++; + + // Clear the interrupt flag + val = SC_CLR_BIT; + ret = spmi_haptics_write(haptics, haptics->base + HAP_SC_CLR_REG, &val, 1); + if (ret < 0) + return IRQ_HANDLED; + + if (haptics->sc_count > SC_MAX_COUNT) { + dev_err(haptics->dev, "Short circuit persists, disabling haptics\n"); + ret = spmi_haptics_module_enable(haptics, false); + if (ret < 0) + dev_err(haptics->dev, "Error disabling module, rc=%d\n", ret); + } + + return IRQ_HANDLED; +} + + +/** + * spmi_haptics_init() - Initialise haptics hardware for use + * @haptics: haptics device + * Returns: 0 on success, < 0 on error + */ +static int spmi_haptics_init(struct spmi_haptics *haptics) +{ + int ret; + u8 val, mask; + u16 play_rate; + + ret = spmi_haptics_write_masked(haptics, haptics->base + HAP_CFG1_REG, + HAP_ACT_TYPE_MASK, haptics->actuator_type); + if (ret < 0) + return ret; + + /* + * Configure auto resonance + * see spmi_haptics_lra_auto_res_config downstream + * This is greatly simplified. + */ + val = FIELD_PREP(LRA_RES_CAL_MASK, ilog2(32 / HAP_RES_CAL_PERIOD_MIN)) | + FIELD_PREP(LRA_AUTO_RES_MODE_MASK, HAP_AUTO_RES_ZXD_EOP) | + FIELD_PREP(LRA_HIGH_Z_MASK, 1); + + mask = LRA_AUTO_RES_MODE_MASK | LRA_HIGH_Z_MASK | LRA_RES_CAL_MASK; + + ret = spmi_haptics_write_masked(haptics, haptics->base + HAP_LRA_AUTO_RES_REG, + mask, val); + + /* Configure the PLAY MODE register */ + ret = spmi_haptics_write_play_mode(haptics); + if (ret < 0) + return ret; + + ret = spmi_haptics_write_vmax(haptics); + if (ret < 0) + return ret; + + /* Configure the ILIM register */ + ret = spmi_haptics_write_current_limit(haptics); + if (ret < 0) + return ret; + + // Configure the debounce for short-circuit detection. + ret = spmi_haptics_write_masked(haptics, haptics->base + HAP_SC_DEB_REG, + HAP_SC_DEB_MASK, HAP_SC_DEB_CYCLES_MAX); + if (ret < 0) + return ret; + + // write the wave shape + ret = spmi_haptics_write_masked(haptics, haptics->base + HAP_CFG2_REG, + HAP_LRA_RES_TYPE_MASK, haptics->wave_shape); + if (ret < 0) + return ret; + + play_rate = haptics->play_wave_rate / HAP_RATE_CFG_STEP_US; + + /* + * Configure RATE_CFG1 and RATE_CFG2 registers. + * Note: For ERM these registers act as play rate and + * for LRA these represent resonance period + */ + ret = spmi_haptics_write_play_rate(haptics, play_rate); + if (ret < 0) + return ret; + + ret = spmi_haptics_write_brake(haptics); + if (ret < 0) + return ret; + + if (haptics->play_mode == HAP_PLAY_BUFFER) { + ret = spmi_haptics_write_wave_repeat(haptics); + if (ret < 0) + return ret; + + ret = spmi_haptics_write_buffer_config(haptics); + if (ret < 0) + return ret; + } + + dev_dbg(haptics->dev, "%s: Requesting play IRQ, irq: %d", __func__, + haptics->play_irq); + ret = devm_request_threaded_irq(haptics->dev, haptics->play_irq, + NULL, spmi_haptics_play_irq_handler, IRQF_ONESHOT, + "haptics_play_irq", haptics); + + if (ret < 0) { + dev_err(haptics->dev, "Unable to request play IRQ ret=%d\n", ret); + return ret; + } + + /* use play_irq only for buffer mode */ + if (haptics->play_mode != HAP_PLAY_BUFFER) + disable_irq(haptics->play_irq); + + dev_dbg(haptics->dev, "%s: Requesting play IRQ, irq: %d", __func__, + haptics->play_irq); + ret = devm_request_threaded_irq(haptics->dev, haptics->sc_irq, + NULL, spmi_haptics_sc_irq_handler, IRQF_ONESHOT, + "haptics_sc_irq", haptics); + + if (ret < 0) { + dev_err(haptics->dev, "Unable to request sc IRQ ret=%d\n", ret); + return ret; + } + + return 0; +} + +/** + * spmi_haptics_enable - handler to start/stop vibration + * @haptics: pointer to haptics struct + * Returns: 0 on success, < 0 on failure + */ +static int spmi_haptics_enable(struct spmi_haptics *haptics) +{ + int ret; + + mutex_lock(&haptics->play_lock); + if (haptics->sc_count > SC_MAX_COUNT) { + dev_err(haptics->dev, "Can't play while in short circuit"); + ret = -1; + goto out; + } + ret = spmi_haptics_set_auto_res(haptics, false); + if (ret < 0) { + dev_err(haptics->dev, "Error disabling auto_res, ret=%d\n", ret); + goto out; + } + + ret = spmi_haptics_module_enable(haptics, true); + if (ret < 0) { + dev_err(haptics->dev, "Error enabling module, ret=%d\n", ret); + goto out; + } + + ret = spmi_haptics_write_play_control(haptics, HAP_PLAY); + if (ret < 0) { + dev_err(haptics->dev, "Error enabling play, ret=%d\n", ret); + goto out; + } + + ret = spmi_haptics_set_auto_res(haptics, true); + if (ret < 0) { + dev_err(haptics->dev, "Error enabling auto_res, ret=%d\n", ret); + goto out; + } + +out: + mutex_unlock(&haptics->play_lock); + return ret; +} + +/** + * spmi_haptics_enable - handler to start/stop vibration + * @haptics: pointer to haptics struct + * Returns: 0 on success, < 0 on failure + */ +static int spmi_haptics_disable(struct spmi_haptics *haptics) +{ + int ret; + + mutex_lock(&haptics->play_lock); + + ret = spmi_haptics_write_play_control(haptics, HAP_STOP); + if (ret < 0) { + dev_err(haptics->dev, "Error disabling play, ret=%d\n", ret); + goto out; + } + + ret = spmi_haptics_module_enable(haptics, false); + if (ret < 0) { + dev_err(haptics->dev, "Error disabling module, ret=%d\n", ret); + goto out; + } + +out: + mutex_unlock(&haptics->play_lock); + return ret; +} + +/* + * Threaded function to update the haptics state. + */ +static void spmi_haptics_work(struct work_struct *work) +{ + struct spmi_haptics *haptics = container_of(work, struct spmi_haptics, work); + + int ret; + bool enable; + + enable = atomic_read(&haptics->active); + dev_dbg(haptics->dev, "%s: state: %d\n", __func__, enable); + + if (enable) + ret = spmi_haptics_enable(haptics); + else + ret = spmi_haptics_disable(haptics); + if (ret < 0) + dev_err(haptics->dev, "Error setting haptics, ret=%d", ret); +} + +/** + * spmi_haptics_close - callback for input device close + * @dev: input device pointer + * + * Turns off the vibrator. + */ +static void spmi_haptics_close(struct input_dev *dev) +{ + struct spmi_haptics *haptics = input_get_drvdata(dev); + + cancel_work_sync(&haptics->work); + if (atomic_read(&haptics->active)) { + atomic_set(&haptics->active, 0); + schedule_work(&haptics->work); + } +} + +/** + * spmi_haptics_play_effect - play haptics effects + * @dev: input device pointer + * @data: data of effect + * @effect: effect to play + */ +static int spmi_haptics_play_effect(struct input_dev *dev, void *data, + struct ff_effect *effect) +{ + struct spmi_haptics *haptics = input_get_drvdata(dev); + + dev_dbg(haptics->dev, "%s: Rumbling with strong: %d and weak: %d", __func__, + effect->u.rumble.strong_magnitude, effect->u.rumble.weak_magnitude); + + haptics->magnitude = effect->u.rumble.strong_magnitude >> 8; + if (!haptics->magnitude) + haptics->magnitude = effect->u.rumble.weak_magnitude >> 10; + + if (!haptics->magnitude) { + atomic_set(&haptics->active, 0); + goto end; + } + + atomic_set(&haptics->active, 1); + + haptics->vmax = ((HAP_VMAX_MAX_MV - HAP_VMAX_MIN_MV) * haptics->magnitude) / 100 + + HAP_VMAX_MIN_MV; + + dev_dbg(haptics->dev, "%s: magnitude: %d, vmax: %d", __func__, + haptics->magnitude, haptics->vmax); + + spmi_haptics_write_vmax(haptics); + +end: + schedule_work(&haptics->work); + + return 0; +} + +static int spmi_haptics_probe(struct platform_device *pdev) +{ + struct spmi_haptics *haptics; + struct device_node *node; + struct input_dev *input_dev; + int ret; + u32 val; + int i; + + haptics = devm_kzalloc(&pdev->dev, sizeof(*haptics), GFP_KERNEL); + if (!haptics) + return -ENOMEM; + + haptics->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!haptics->regmap) + return -ENODEV; + + node = pdev->dev.of_node; + + haptics->dev = &pdev->dev; + + ret = of_property_read_u32(node, "reg", &haptics->base); + if (ret < 0) { + dev_err(haptics->dev, "Couldn't find reg in node = %s ret = %d\n", + node->full_name, ret); + return ret; + } + + haptics->play_irq = platform_get_irq_byname(pdev, "play"); + if (haptics->play_irq < 0) { + dev_err(&pdev->dev, "Unable to get play irq\n"); + ret = haptics->play_irq; + goto register_fail; + } + + haptics->sc_irq = platform_get_irq_byname(pdev, "short"); + if (haptics->sc_irq < 0) { + dev_err(&pdev->dev, "Unable to get sc irq\n"); + ret = haptics->sc_irq; + goto register_fail; + } + + // We only support LRAs for now + haptics->actuator_type = HAP_TYPE_LRA; + ret = of_property_read_u32(node, "qcom,actuator-type", &val); + if (!ret) { + if (val != HAP_TYPE_LRA) { + dev_err(&pdev->dev, "qcom,actuator-type (%d) isn't supported\n", val); + ret = -EINVAL; + goto register_fail; + } + haptics->actuator_type = val; + } + + // Only buffer mode is currently supported + haptics->play_mode = HAP_PLAY_BUFFER; + ret = of_property_read_u32(node, "qcom,play-mode", &val); + if (!ret) { + if (val != HAP_PLAY_BUFFER) { + dev_err(&pdev->dev, "qcom,play-mode (%d) isn't supported\n", val); + ret = -EINVAL; + goto register_fail; + } + haptics->play_mode = val; + } + + ret = of_property_read_u32(node, "qcom,wave-play-rate-us", &val); + if (!ret) { + haptics->play_wave_rate = val; + } else if (ret != -EINVAL) { + dev_err(haptics->dev, "Unable to read play rate ret=%d\n", ret); + goto register_fail; + } + + haptics->play_wave_rate = + clamp_t(u32, haptics->play_wave_rate, + HAP_WAVE_PLAY_RATE_MIN_US, HAP_WAVE_PLAY_RATE_MAX_US); + + haptics->wave_shape = HAP_WAVE_SINE; + ret = of_property_read_u32(node, "qcom,wave-shape", &val); + if (!ret) { + if (val != HAP_WAVE_SINE && val != HAP_WAVE_SQUARE) { + dev_err(&pdev->dev, "qcom,wave-shape is invalid: %d\n", val); + ret = -EINVAL; + goto register_fail; + } + haptics->wave_shape = val; + } + + haptics->brake_pat[0] = 0x3; + haptics->brake_pat[1] = 0x3; + haptics->brake_pat[2] = 0x2; + haptics->brake_pat[3] = 0x1; + + ret = of_property_read_u8_array(node, "qcom,brake-pattern", haptics->brake_pat, 4); + if (ret < 0 && ret != -EINVAL) { + dev_err(&pdev->dev, "qcom,brake-pattern is invalid, ret = %d\n", ret); + goto register_fail; + } + + haptics->current_limit = HAP_ILIM_400_MA; + + for (i = 0; i < HAP_WAVE_SAMP_LEN; i++) + haptics->wave_samp[i] = HAP_WF_SAMP_MAX; + + ret = spmi_haptics_init(haptics); + if (ret < 0) { + dev_err(&pdev->dev, "Error initialising haptics, ret=%d\n", + ret); + goto register_fail; + } + + platform_set_drvdata(pdev, haptics); + + input_dev = devm_input_allocate_device(&pdev->dev); + if (!input_dev) + return -ENOMEM; + + INIT_WORK(&haptics->work, spmi_haptics_work); + haptics->haptics_input_dev = input_dev; + + input_dev->name = "spmi_haptics"; + input_dev->id.version = 1; + input_dev->close = spmi_haptics_close; + input_set_drvdata(input_dev, haptics); + // Figure out how to make this FF_PERIODIC + input_set_capability(haptics->haptics_input_dev, EV_FF, FF_RUMBLE); + + ret = input_ff_create_memless(input_dev, NULL, + spmi_haptics_play_effect); + if (ret) { + dev_err(&pdev->dev, + "couldn't register vibrator as FF device\n"); + goto register_fail; + } + + ret = input_register_device(input_dev); + if (ret) { + dev_err(&pdev->dev, "couldn't register input device\n"); + goto register_fail; + } + + return 0; + +register_fail: + cancel_work_sync(&haptics->work); + mutex_destroy(&haptics->play_lock); + + return ret; +} + +static int __maybe_unused spmi_haptics_suspend(struct device *dev) +{ + struct spmi_haptics *haptics = dev_get_drvdata(dev); + + cancel_work_sync(&haptics->work); + spmi_haptics_disable(haptics); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(spmi_haptics_pm_ops, spmi_haptics_suspend, NULL); + +static int spmi_haptics_remove(struct platform_device *pdev) +{ + struct spmi_haptics *haptics = dev_get_drvdata(&pdev->dev); + + cancel_work_sync(&haptics->work); + mutex_destroy(&haptics->play_lock); + input_unregister_device(haptics->haptics_input_dev); + + return 0; +} + +static void spmi_haptics_shutdown(struct platform_device *pdev) +{ + struct spmi_haptics *haptics = dev_get_drvdata(&pdev->dev); + + cancel_work_sync(&haptics->work); + + spmi_haptics_disable(haptics); +} + +static const struct of_device_id spmi_haptics_match_table[] = { + { .compatible = "qcom,spmi-haptics" }, + { } +}; +MODULE_DEVICE_TABLE(of, spmi_haptics_match_table); + +static struct platform_driver spmi_haptics_driver = { + .probe = spmi_haptics_probe, + .remove = spmi_haptics_remove, + .shutdown = spmi_haptics_shutdown, + .driver = { + .name = "spmi-haptics", + .pm = &spmi_haptics_pm_ops, + .of_match_table = spmi_haptics_match_table, + }, +}; +module_platform_driver(spmi_haptics_driver); + +MODULE_DESCRIPTION("spmi haptics driver using ff-memless framework"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Caleb Connolly "); From e20414070bcc8f9bde32216177bff527f2a990c1 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 10 Dec 2021 02:27:00 +0000 Subject: [PATCH 124/174] arm64: dts: qcom: pmi8998: introduce spmi haptics Add bindings for Qualcomm SPMI haptics on platforms using pmi8998. Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index a5d50d7156cc..55430ec29380 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include @@ -62,5 +63,20 @@ status = "disabled"; }; + + pmi8998_haptics: haptics@c000 { + compatible = "qcom,pmi8998-haptics"; + reg = <0xc000>; + + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "short", "play"; + + qcom,wave-shape = ; + qcom,play-mode = ; + qcom,brake-pattern = <0x3 0x3 0x2 0x1>; + + status = "disabled"; + }; }; }; From 6f6f039c9ea1f1dc998e81bdb5329a9dc08715a7 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 10 Dec 2021 02:27:20 +0000 Subject: [PATCH 125/174] arm64: dts: qcom: msm8998-oneplus-common: Enable PMI8998 haptics The OnePlus 5 and 5T both have a haptics engine connected to PMI8998. Signed-off-by: Jami Kettunen Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 9823d48a91b1..1a38db26a8c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -257,6 +257,12 @@ }; }; +&pmi8998_haptics { + status = "okay"; + + qcom,wave-play-rate-us = <4255>; +}; + &qusb2phy { status = "okay"; From f780d839de59c3691669805b542591255bf1869b Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 16:12:04 +0200 Subject: [PATCH 126/174] [ANNOTATION] Import SPMI haptics driver v4 Drop SDM845 DTS changes though. Link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20211210022639.2779173-1-caleb@connolly.tech/ From 0c7a8ce70a0cb66941fa015739b04f7df3edac0f Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 25 Dec 2020 12:55:46 +0530 Subject: [PATCH 127/174] power: supply: introduce pmi8998 fuel guage driver --- drivers/power/supply/Kconfig | 10 + drivers/power/supply/Makefile | 1 + drivers/power/supply/pmi8998_fg.c | 526 ++++++++++++++++++++++++++++++ drivers/power/supply/pmi8998_fg.h | 138 ++++++++ 4 files changed, 675 insertions(+) create mode 100644 drivers/power/supply/pmi8998_fg.c create mode 100644 drivers/power/supply/pmi8998_fg.h diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index b366e2fd8e97..0eb25bc8e7e6 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -866,4 +866,14 @@ config CHARGER_SURFACE Microsoft Surface devices, i.e. Surface Pro 7, Surface Laptop 3, Surface Book 3, and Surface Laptop Go. +config BATTERY_PMI8998_FG + tristate "Qualcomm PMI8998 fuel gauge driver" + depends on MFD_SPMI_PMIC + help + Say Y here to enable the Qualcomm PMI8998 Fuel Gauge driver. This + adds support for battery fuel gauging and state of charge of + battery connected tothe fuel gauge. The state of charge is + reported through a BMS power supply property and also sends + uevents when the capacity is updated. + endif # POWER_SUPPLY diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 2c1b264b2046..7e325b7fa246 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -105,3 +105,4 @@ obj-$(CONFIG_RN5T618_POWER) += rn5t618_power.o obj-$(CONFIG_BATTERY_ACER_A500) += acer_a500_battery.o obj-$(CONFIG_BATTERY_SURFACE) += surface_battery.o obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o +obj-$(CONFIG_BATTERY_PMI8998_FG) += pmi8998_fg.o diff --git a/drivers/power/supply/pmi8998_fg.c b/drivers/power/supply/pmi8998_fg.c new file mode 100644 index 000000000000..ba2cf70ecc15 --- /dev/null +++ b/drivers/power/supply/pmi8998_fg.c @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmi8998_fg.h" + +/************************ + * IO FUNCTIONS + * **********************/ + +/** + * pmi8998_read() - Read multiple registers with regmap_bulk_read + * + * @param map The regmap to read + * @param val Pointer to read values into + * @param addr Address to read from + * @param len Number of registers (bytes) to read + * @return int 0 on success, negative errno on error + */ +static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) +{ + if ((addr & 0xff00) == 0) { + pr_err("base cannot be zero base=0x%02x\n", addr); + return -EINVAL; + } + + pr_info("%s: reading 0x%x bytes from 0x%x", __func__, len, addr); + + return regmap_bulk_read(map, addr, val, len); +} + +/** + * @brief pmi8998_write() - Write multiple registers with regmap_bulk_write + * + * @param map The regmap to write + * @param val Pointer to write values into + * @param addr Address to write from + * @param len Number of registers (bytes) to write + * @return int 0 on success, negative errno on error + */ +static int pmi8998_write(struct regmap *map, u8 *val, u16 addr, int len) +{ + int rc; + bool sec_access = (addr & 0xff) > 0xd0; + u8 sec_addr_val = 0xa5; + + if (sec_access) { + rc = regmap_bulk_write(map, + (addr & 0xff00) | 0xd0, + &sec_addr_val, 1); + } + + if ((addr & 0xff00) == 0) { + pr_err("addr cannot be zero base=0x%02x\n", addr); + return -EINVAL; + } + + return regmap_bulk_write(map, addr, val, len); +} + +/** + * @brief pmi8998_masked_write() - like pmi8998_write but applies + * a mask first. + * + * @param map The regmap to write + * @param val Pointer to write values into + * @param addr Address to write from + * @param len Number of registers (bytes) to write + * @return int 0 on success, negative errno on error + */ +static int pmi8998_masked_write(struct regmap *map, u16 addr, + u8 mask, u8 val) +{ + int error; + u8 reg; + error = pmi8998_read(map, ®, addr, 1); + if (error) + return error; + + reg &= ~mask; + reg |= val & mask; + + error = pmi8998_write(map, ®, addr, 1); + return error; +} + +static int64_t twos_compliment_extend(int64_t val, int nbytes) +{ + int i; + int64_t mask; + + mask = 0x80LL << ((nbytes - 1) * 8); + if (val & mask) { + for (i = 8; i > nbytes; i--) { + mask = 0xFFLL << ((i - 1) * 8); + val |= mask; + } + } + return val; +} + +/************************* + * Battery Status RW + * ***********************/ + +static int pmi8998_fg_get_capacity(struct pmi8998_fg_chip *chip, int *val) +{ + u8 cap[2]; + int error = pmi8998_read(chip->regmap, cap, REG_BASE(chip) + BATT_MONOTONIC_SOC, 2); + if (error) + return error; + if (cap[0] != cap[1]) { + cap[0] = cap[0] < cap[1] ? cap[0] : cap[1]; + } + *val = DIV_ROUND_CLOSEST((cap[0] - 1) * 98, 0xff - 2) + 1; + return 0; +} + +static bool pmi8998_battery_missing(struct pmi8998_fg_chip *chip) +{ + int rc; + u8 fg_batt_sts; + + rc = pmi8998_read(chip->regmap, &fg_batt_sts, + REG_BATT(chip) + INT_RT_STS, 1); + if (rc) { + pr_warn("read read failed: addr=%03X, rc=%d\n", + REG_BATT(chip) + INT_RT_STS, rc); + return false; + } + + // Bit 6 is set if the battery is missing + return (fg_batt_sts & BIT(6)) ? true : false; +} + +static int pmi8998_fg_get_temperature(struct pmi8998_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_TEMP, 2); + if (rc) { + pr_err("Failed to read temperature\n"); + return rc; + } + temp = ((readval[1] & BATT_TEMP_MSB_MASK) << 8) | + (readval[0] & BATT_TEMP_LSB_MASK); + temp = DIV_ROUND_CLOSEST(temp * 10, 4); + + *val = temp -2730; + return 0; +} + +static int pmi8998_fg_get_current(struct pmi8998_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_CURRENT, 2); + if (rc) { + pr_err("Failed to read current\n"); + return rc; + } + + temp = readval[1] << 8 | readval[0]; + temp = twos_compliment_extend(temp, 2); + *val = div_s64((s64)temp * 488281, + 1000); + return 0; +} + +static int pmi8998_fg_get_voltage(struct pmi8998_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_VOLTAGE, 2); + if (rc) { + pr_err("Failed to read voltage\n"); + return rc; + } + + temp = readval[1] << 8 | readval[0]; + temp = twos_compliment_extend(temp, 2); + *val = div_s64((s64)temp * 122070, + 1000); + return 0; +} + +static int pmi8998_fg_get_max_charge_design(struct pmi8998_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + BATT_INFO_CHARGE_MAX_DESIGN, 2); + if (rc) { + pr_err("Failed to read voltage\n"); + return rc; + } + + temp = readval[1] << 8 | readval[0]; + temp = twos_compliment_extend(temp, 2); + *val = div_s64((s64)temp * 122070, + 1000); + return 0; +} + +/******************** + * Init stuff + * ******************/ + +static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) +{ + int rc = 0; + u8 temp; + + /* clear the error */ + rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + MEM_INTF_IMA_CFG, + BIT(2), BIT(2)); + if (rc) { + pr_err("Error writing to IMA_CFG, rc=%d\n", rc); + return rc; + } + + temp = 0x4; + rc = pmi8998_write(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_ADDR_LSB + 1, 1); + if (rc) { + pr_err("Error writing to MEM_INTF_ADDR_MSB, rc=%d\n", rc); + return rc; + } + + temp = 0x0; + rc = pmi8998_write(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_WR_DATA0 + 3, 1); + if (rc) { + pr_err("Error writing to WR_DATA3, rc=%d\n", rc); + return rc; + } + + rc = pmi8998_read(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_RD_DATA0 + 3, 1); + if (rc) { + pr_err("Error writing to RD_DATA3, rc=%d\n", rc); + return rc; + } + + rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + MEM_INTF_IMA_CFG, + BIT(2), 0); + if (rc) { + pr_err("Error writing to IMA_CFG, rc=%d\n", rc); + return rc; + } + return rc; +} + +static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, + bool check_hw_sts) +{ + int rc = 0, ret = 0; + u8 err_sts = 0, exp_sts = 0, hw_sts = 0; + bool run_err_clr_seq = false; + + rc = pmi8998_read(chip->regmap, &err_sts, + REG_MEM(chip) + MEM_INTF_IMA_ERR_STS, 1); + if (rc) { + dev_err(chip->dev, "failed to read IMA_ERR_STS, rc=%d\n", rc); + return rc; + } + + rc = pmi8998_read(chip->regmap, &exp_sts, + REG_MEM(chip) + MEM_INTF_IMA_EXP_STS, 1); + if (rc) { + dev_err(chip->dev, "Error in reading IMA_EXP_STS, rc=%d\n", rc); + return rc; + } + + if (check_hw_sts) { + rc = pmi8998_read(chip->regmap, &hw_sts, + REG_MEM(chip) + MEM_INTF_IMA_HW_STS, 1); + if (rc) { + dev_err(chip->dev, "Error in reading IMA_HW_STS, rc=%d\n", rc); + return rc; + } + /* + * Lower nibble should be equal to upper nibble before SRAM + * transactions begins from SW side. + */ + if ((hw_sts & 0x0f) != hw_sts >> 4) { + dev_err(chip->dev, "IMA HW not in correct state, hw_sts=%x\n", + hw_sts); + run_err_clr_seq = true; + } + } + + if (exp_sts & (BIT(0) | BIT(1) | BIT(3) | + BIT(4) | BIT(5) | BIT(6) | + BIT(7))) { + dev_warn(chip->dev, "IMA exception bit set, exp_sts=%x\n", exp_sts); + run_err_clr_seq = true; + } + + if (run_err_clr_seq) { + ret = pmi8998_iacs_clear_sequence(chip); + if (!ret) + return -EAGAIN; + else + dev_err(chip->dev, "Error clearing IMA exception ret=%d\n", ret); + } + + return rc; +} + +static int fg_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct pmi8998_fg_chip *chip = power_supply_get_drvdata(psy); + int error = 0; + + dev_info(chip->dev, "Getting property: %d", psp); + + switch (psp) { + case POWER_SUPPLY_PROP_MANUFACTURER: + val->strval = "QCOM"; + break; + case POWER_SUPPLY_PROP_MODEL_NAME: + val->strval = "PMI8998 Battery"; + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = POWER_SUPPLY_TECHNOLOGY_LION; + break; + case POWER_SUPPLY_PROP_CAPACITY: + error = pmi8998_fg_get_capacity(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + error = pmi8998_fg_get_current(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + error = pmi8998_fg_get_voltage(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = chip->batt_info.batt_max_voltage_uv; + break; + case POWER_SUPPLY_PROP_TEMP: + error = pmi8998_fg_get_temperature(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN: + val->intval = 3370000; + break; + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: + case POWER_SUPPLY_PROP_CHARGE_FULL: /* TODO: Implement learning */ + val->intval = chip->batt_info.nom_cap_uah; + break; + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_CHARGING; + //error = smb2_chg_get_status(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_HEALTH: + val->intval = POWER_SUPPLY_HEALTH_GOOD; + break; + default: + pr_err("invalid property: %d\n", psp); + return -EINVAL; + } + return error; +} + +static const struct power_supply_desc bms_psy_desc = { + .name = "pmi8998-bms", + .type = POWER_SUPPLY_TYPE_BATTERY, + .properties = fg_properties, + .num_properties = ARRAY_SIZE(fg_properties), + .get_property = fg_get_property, +}; + +static int pmi8998_fg_of_battery_init(struct pmi8998_fg_chip *chip){ + struct device_node *batt_node; + struct device_node *node = chip->dev->of_node; + int rc = 0; + + batt_node = of_find_node_by_name(node, "qcom,battery-data"); + if (!batt_node) { + pr_err("No available batterydata\n"); + return rc; + } + + of_property_read_u32(batt_node, "qcom,max-voltage-uv", + &chip->batt_info.batt_max_voltage_uv_design); + + // Can be read from SRAM, hardcode in DTS for now as reading SRAM is HARD! + of_property_read_u32(batt_node, "qcom,design-capacity", + &chip->batt_info.nom_cap_uah); + + return rc; +} + +static int pmi8998_fg_probe(struct platform_device *pdev) +{ + struct power_supply_config supply_config = {}; + struct pmi8998_fg_chip *chip; + const __be32 *prop_addr; + int rc = 0; + u8 dma_status; + bool error_present; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + return -ENOMEM; + } + + chip->dev = &pdev->dev; + mutex_init(&chip->lock); + + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(chip->dev, "failed to locate the regmap\n"); + return -ENODEV; + } + + // Get base address + prop_addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL); + if (!prop_addr) { + dev_err(chip->dev, "Couldn't read SOC base address from dt\n"); + return -EINVAL; + } + chip->base = be32_to_cpu(*prop_addr); + + // Init memif fn inlined here (chip hardware info) + rc = pmi8998_read(chip->regmap, chip->revision, REG_MEM(chip) + DIG_MINOR, 4); + if (rc) { + dev_err(chip->dev, "Unable to read FG revision rc=%d\n", rc); + return rc; + } + + dev_dbg(chip->dev, "pmi8998 revision DIG:%d.%d ANA:%d.%d\n", + chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], + chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); + + /* + * Change the FG_MEM_INT interrupt to track IACS_READY + * condition instead of end-of-transaction. This makes sure + * that the next transaction starts only after the hw is ready. + * IACS_INTR_SRC_SLCT is BIT(3) + */ + rc = pmi8998_masked_write(chip->regmap, + REG_MEM(chip) + MEM_INTF_IMA_CFG, BIT(3), BIT(3)); + if (rc) { + dev_err(chip->dev, + "failed to configure interrupt source %d\n", + rc); + return rc; + } + + rc = pmi8998_clear_ima(chip, true); + if (rc && rc != -EAGAIN) { + dev_err(chip->dev, "Error clearing IMA, exception rc=%d", rc); + return rc; + } + + // Check and clear DMA errors + rc = pmi8998_read(chip->regmap, &dma_status, REG_MEM(chip) + 0x70, 1); + if (rc < 0) { + pr_err("failed to read dma_status, rc=%d\n", rc); + return rc; + } + + error_present = dma_status & (BIT(1) | BIT(2)); + rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + 0x71, BIT(0), + error_present ? BIT(0) : 0); + if (rc < 0) { + pr_err("failed to write dma_ctl, rc=%d\n", rc); + return rc; + } + + dev_dbg(chip->dev, "probed revision DIG:%d.%d ANA:%d.%d\n", + chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], + chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); + + supply_config.drv_data = chip; + supply_config.of_node = pdev->dev.of_node; + + chip->bms_psy = devm_power_supply_register(chip->dev, + &bms_psy_desc, &supply_config); + if (IS_ERR(chip->bms_psy)) { + dev_err(&pdev->dev, "failed to register battery\n"); + return PTR_ERR(chip->bms_psy); + } + + platform_set_drvdata(pdev, chip); + return 0; +} + +static int pmi8998_fg_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id fg_match_id_table[] = { + { .compatible = "qcom,pmi8998-fg" }, + { /* sentinal */ } +}; +MODULE_DEVICE_TABLE(of, fg_match_id_table); + +static struct platform_driver qcom_fg_driver = { + .probe = pmi8998_fg_probe, + .remove = pmi8998_fg_remove, + .driver = { + .name = "pmi8998-fg", + .of_match_table = fg_match_id_table, + }, +}; + +module_platform_driver(qcom_fg_driver); + +MODULE_AUTHOR("Caleb Connolly "); +MODULE_AUTHOR("Joel Selvaraj "); +MODULE_DESCRIPTION("Qualcomm PMI8998 Fuel Guage Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/supply/pmi8998_fg.h b/drivers/power/supply/pmi8998_fg.h new file mode 100644 index 000000000000..20dd2d2fc6e8 --- /dev/null +++ b/drivers/power/supply/pmi8998_fg.h @@ -0,0 +1,138 @@ + +// #define FG_PARAM_MAX 49 + +/**** Registers *****/ + +// pmi8998 v2 specific +#define BATT_INFO_CHARGE_MAX_DESIGN 0x4a +#define MEM_INTF_CFG 0x50 +#define MEM_INTF_ADDR_LSB 0x61 +#define MEM_INTF_RD_DATA0 0x67 +#define MEM_INTF_WR_DATA0 0x63 + +#define SMB2_CABLE_CONNECTED 0x06 + +// pm8950 / pm89988 common +#define MEM_INTF_IMA_CFG 0x52 +#define MEM_INTF_IMA_OPR_STS 0x54 +#define MEM_INTF_IMA_EXP_STS 0x55 +#define MEM_INTF_IMA_HW_STS 0x56 +#define MEM_INTF_BEAT_COUNT 0x57 +#define MEM_INTF_IMA_ERR_STS 0x5f +#define MEM_INTF_IMA_BYTE_EN 0x60 + +#define BATT_INFO_THERM_C1 0x5c +#define BATT_INFO_VBATT_LSB 0xa0 +#define BATT_INFO_VBATT_MSB 0xa1 +#define BATT_INFO_IBATT_LSB 0xa2 +#define BATT_INFO_IBATT_MSB 0xa3 +#define BATT_INFO_BATT_TEMP_LSB 0x50 +#define BATT_INFO_BATT_TEMP_MSB 0x51 +#define BATT_MONOTONIC_SOC 0x09 + +#define BATT_TEMP_LSB_MASK GENMASK(7, 0) +#define BATT_TEMP_MSB_MASK GENMASK(2, 0) + +#define REG_BASE(chip) (chip->base) +#define REG_BATT(chip) (chip->base + 0x100) +#define REG_MEM(chip) (chip->base + 0x400) + +/* Interrupt offsets */ +#define INT_RT_STS 0x10 +#define INT_EN_CLR 0x16 + +// Param addresses +#define PARAM_ADDR_BATT_TEMP 0x50 +#define PARAM_ADDR_BATT_VOLTAGE 0xa0 +#define PARAM_ADDR_BATT_CURRENT 0xa2 + +enum wa_flags { + PMI8998_V1_REV_WA, + PMI8998_V2_REV_WA, +}; + +enum pmi8998_rev_offsets { + DIG_MINOR = 0x0, + DIG_MAJOR = 0x1, + ANA_MINOR = 0x2, + ANA_MAJOR = 0x3, +}; +enum pmi8998_rev { + DIG_REV_1 = 0x1, + DIG_REV_2 = 0x2, + DIG_REV_3 = 0x3, +}; + +enum charger_status{ + TRICKLE_CHARGE = 0, + PRE_CHARGE, + FAST_CHARGE, + FULLON_CHARGE, + TAPER_CHARGE, + TERMINATE_CHARGE, + INHIBIT_CHARGE, + DISABLE_CHARGE, +}; + +static enum power_supply_property fg_properties[] = { + POWER_SUPPLY_PROP_MANUFACTURER, + POWER_SUPPLY_PROP_MODEL_NAME, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN, + POWER_SUPPLY_PROP_TEMP, + // POWER_SUPPLY_PROP_CHARGE_NOW, + // POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_STATUS, +}; + +struct fg_learning_data { + struct mutex learning_lock; + bool active; + int64_t cc_uah; + int learned_cc_uah; + int init_cc_pc_val; + int max_start_soc; + int max_increment; + int max_decrement; + int vbat_est_thr_uv; + int max_cap_limit; + int min_cap_limit; + int min_temp; + int max_temp; +}; + +struct battery_info { + const char *manufacturer; + const char *model; + const char *serial_num; + + int nom_cap_uah; + + int batt_max_voltage_uv_design; + int batt_max_voltage_uv; +}; + +struct pmi8998_fg_chip { + struct device *dev; + unsigned int base; + struct regmap *regmap; + struct mutex lock; + + struct power_supply *bms_psy; + + u8 revision[4]; + bool ima_supported; + + struct battery_info batt_info; + + struct fg_learning_data learning_data; + + int health; + int status; +}; From 8a66c540f262185d8eda85218828efb9fc7a489e Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 25 Dec 2020 12:56:42 +0530 Subject: [PATCH 128/174] arm64: dts: qcom: pmi8998: Add nodes for pmi8998 fuel guage --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 55430ec29380..6d6f843a6a4a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -19,6 +19,15 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pmi8998_fg: fuel_guage { + compatible = "qcom,pmi8998-fg"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x4000>; + }; }; pmi8998_lsid1: pmic@3 { From d962bb5d78c143ea1d542bd218368809ddd5ec33 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Thu, 31 Dec 2020 16:35:41 +0530 Subject: [PATCH 129/174] power: supply: add battery charging status feature --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 6 +- drivers/power/supply/pmi8998_fg.c | 106 ++++++++++++++++++++++++-- drivers/power/supply/pmi8998_fg.h | 7 ++ 3 files changed, 109 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 6d6f843a6a4a..d1239cc224f0 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -25,8 +25,10 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - - reg = <0x4000>; + //FG //Charger + reg = <0x4000 0x1000>; + interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb-plugin"; }; }; diff --git a/drivers/power/supply/pmi8998_fg.c b/drivers/power/supply/pmi8998_fg.c index ba2cf70ecc15..f38f1984b59c 100644 --- a/drivers/power/supply/pmi8998_fg.c +++ b/drivers/power/supply/pmi8998_fg.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include "pmi8998_fg.h" @@ -318,6 +320,70 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, return rc; } +int pmi8998_get_prop_usb_online(struct pmi8998_fg_chip *chip, int *val){ + unsigned int stat; + int rc; + + rc = regmap_read(chip->regmap, POWER_PATH_STATUS_REG, &stat); + if (rc < 0){ + dev_err(chip->dev, "Couldn't read POWER_PATH_STATUS! ret=%d\n", rc); + return rc; + } + + dev_dbg(chip->dev, "USB POWER_PATH_STATUS : 0x%02x\n", stat); + *val = (stat & BIT(4)) && (stat & BIT(0)); + return rc; +} + +int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ + int usb_online_val; + unsigned int stat; + int rc; + bool usb_online; + + rc = pmi8998_get_prop_usb_online(chip, &usb_online_val); + if (rc < 0) { + dev_err(chip->dev, "Couldn't get usb online property rc=%d\n", rc); + return rc; + } + dev_dbg(chip->dev, "USB ONLINE val : %d\n", usb_online_val); + usb_online = (bool)usb_online_val; + + if (!usb_online) { + *val = POWER_SUPPLY_STATUS_DISCHARGING; + return rc; + } + + rc = regmap_read(chip->regmap, BATTERY_CHARGER_STATUS_REG(chip), &stat); + if (rc < 0){ + dev_err(chip->dev, "Charging status REGMAP read failed! ret=%d\n", rc); + return rc; + } + + stat = stat & BATTERY_CHARGER_STATUS_MASK; + dev_dbg(chip->dev, "Charging status : %d!\n", stat); + + switch (stat) { + case TRICKLE_CHARGE: + case PRE_CHARGE: + case FAST_CHARGE: + case FULLON_CHARGE: + case TAPER_CHARGE: + case TERMINATE_CHARGE: + case INHIBIT_CHARGE: + *val = POWER_SUPPLY_STATUS_CHARGING; + break; + case DISABLE_CHARGE: + *val = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + default: + *val = POWER_SUPPLY_STATUS_UNKNOWN; + break; + } + + return rc; +} + static int fg_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -325,7 +391,7 @@ static int fg_get_property(struct power_supply *psy, struct pmi8998_fg_chip *chip = power_supply_get_drvdata(psy); int error = 0; - dev_info(chip->dev, "Getting property: %d", psp); + dev_dbg(chip->dev, "Getting property: %d", psp); switch (psp) { case POWER_SUPPLY_PROP_MANUFACTURER: @@ -360,8 +426,7 @@ static int fg_get_property(struct power_supply *psy, val->intval = chip->batt_info.nom_cap_uah; break; case POWER_SUPPLY_PROP_STATUS: - val->intval = POWER_SUPPLY_STATUS_CHARGING; - //error = smb2_chg_get_status(chip, &val->intval); + error = pmi8998_get_prop_batt_status(chip, &val->intval); break; case POWER_SUPPLY_PROP_HEALTH: val->intval = POWER_SUPPLY_HEALTH_GOOD; @@ -402,12 +467,19 @@ static int pmi8998_fg_of_battery_init(struct pmi8998_fg_chip *chip){ return rc; } +irqreturn_t pmi8998_handle_usb_plugin(int irq, void *data){ + struct pmi8998_fg_chip *chip = data; + dev_dbg(chip->dev, "USB IRQ called!\n"); + power_supply_changed(chip->bms_psy); + return IRQ_HANDLED; +} + static int pmi8998_fg_probe(struct platform_device *pdev) { struct power_supply_config supply_config = {}; struct pmi8998_fg_chip *chip; const __be32 *prop_addr; - int rc = 0; + int rc = 0, irq; u8 dma_status; bool error_present; @@ -433,6 +505,13 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } chip->base = be32_to_cpu(*prop_addr); + prop_addr = of_get_address(pdev->dev.of_node, 1, NULL, NULL); + if (!prop_addr) { + dev_err(chip->dev, "Couldn't read CHG base address from dt\n"); + return -EINVAL; + } + chip->chg_base = be32_to_cpu(*prop_addr); + // Init memif fn inlined here (chip hardware info) rc = pmi8998_read(chip->regmap, chip->revision, REG_MEM(chip) + DIG_MINOR, 4); if (rc) { @@ -479,10 +558,6 @@ static int pmi8998_fg_probe(struct platform_device *pdev) pr_err("failed to write dma_ctl, rc=%d\n", rc); return rc; } - - dev_dbg(chip->dev, "probed revision DIG:%d.%d ANA:%d.%d\n", - chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], - chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); supply_config.drv_data = chip; supply_config.of_node = pdev->dev.of_node; @@ -495,6 +570,21 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, chip); + + irq = of_irq_get_byname(pdev->dev.of_node, "usb-plugin"); + if (irq < 0) { + dev_err(&pdev->dev, "Couldn't get irq usb-plugin byname\n"); + return irq; + } + + rc = devm_request_threaded_irq(chip->dev, irq, NULL, + pmi8998_handle_usb_plugin, + IRQF_ONESHOT, "usb-plugin", chip); + if (rc < 0) { + pr_err("Couldn't request irq %d\n", irq); + return rc; + } + return 0; } diff --git a/drivers/power/supply/pmi8998_fg.h b/drivers/power/supply/pmi8998_fg.h index 20dd2d2fc6e8..81a90945c0e6 100644 --- a/drivers/power/supply/pmi8998_fg.h +++ b/drivers/power/supply/pmi8998_fg.h @@ -46,6 +46,12 @@ #define PARAM_ADDR_BATT_VOLTAGE 0xa0 #define PARAM_ADDR_BATT_CURRENT 0xa2 +#define MISC_BASE 0x1600 + +#define BATTERY_CHARGER_STATUS_REG(chip) (chip->chg_base + 0x06) +#define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0) +#define POWER_PATH_STATUS_REG (MISC_BASE + 0x0B) + enum wa_flags { PMI8998_V1_REV_WA, PMI8998_V2_REV_WA, @@ -121,6 +127,7 @@ struct battery_info { struct pmi8998_fg_chip { struct device *dev; unsigned int base; + unsigned int chg_base; struct regmap *regmap; struct mutex lock; From f1b6077a1363b1ee89cabc6b8bc61db295b549a1 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 1 Jan 2021 16:18:26 +0530 Subject: [PATCH 130/174] fg: clean and read charge full and max voltage from dts --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 3 + drivers/power/supply/pmi8998_fg.c | 274 +++++++++++++++++--------- drivers/power/supply/pmi8998_fg.h | 69 +++---- 3 files changed, 209 insertions(+), 137 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index d1239cc224f0..ad509c25cac3 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -29,6 +29,9 @@ reg = <0x4000 0x1000>; interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "usb-plugin"; + qcom,max-voltage-uv = <4400000>; + qcom,min-voltage-uv = <3700000>; + qcom,battery-capacity-ua = <4000000>; }; }; diff --git a/drivers/power/supply/pmi8998_fg.c b/drivers/power/supply/pmi8998_fg.c index f38f1984b59c..1aea6eaf30f9 100644 --- a/drivers/power/supply/pmi8998_fg.c +++ b/drivers/power/supply/pmi8998_fg.c @@ -36,7 +36,7 @@ static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) return -EINVAL; } - pr_info("%s: reading 0x%x bytes from 0x%x", __func__, len, addr); + //pr_info("%s: reading 0x%x bytes from 0x%x", __func__, len, addr); return regmap_bulk_read(map, addr, val, len); } @@ -118,7 +118,7 @@ static int64_t twos_compliment_extend(int64_t val, int nbytes) static int pmi8998_fg_get_capacity(struct pmi8998_fg_chip *chip, int *val) { u8 cap[2]; - int error = pmi8998_read(chip->regmap, cap, REG_BASE(chip) + BATT_MONOTONIC_SOC, 2); + int error = pmi8998_read(chip->regmap, cap, REG_BASE + BATT_MONOTONIC_SOC, 2); if (error) return error; if (cap[0] != cap[1]) { @@ -128,29 +128,12 @@ static int pmi8998_fg_get_capacity(struct pmi8998_fg_chip *chip, int *val) return 0; } -static bool pmi8998_battery_missing(struct pmi8998_fg_chip *chip) -{ - int rc; - u8 fg_batt_sts; - - rc = pmi8998_read(chip->regmap, &fg_batt_sts, - REG_BATT(chip) + INT_RT_STS, 1); - if (rc) { - pr_warn("read read failed: addr=%03X, rc=%d\n", - REG_BATT(chip) + INT_RT_STS, rc); - return false; - } - - // Bit 6 is set if the battery is missing - return (fg_batt_sts & BIT(6)) ? true : false; -} - static int pmi8998_fg_get_temperature(struct pmi8998_fg_chip *chip, int *val) { int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_TEMP, 2); + rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_TEMP, 2); if (rc) { pr_err("Failed to read temperature\n"); return rc; @@ -168,16 +151,15 @@ static int pmi8998_fg_get_current(struct pmi8998_fg_chip *chip, int *val) int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_CURRENT, 2); + rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_CURRENT, 2); if (rc) { pr_err("Failed to read current\n"); return rc; } - + //handle rev 1 too temp = readval[1] << 8 | readval[0]; - temp = twos_compliment_extend(temp, 2); - *val = div_s64((s64)temp * 488281, - 1000); + temp = twos_compliment_extend(temp, 15); + *val = div_s64((s64)temp * 488281, 1000); return 0; } @@ -186,34 +168,14 @@ static int pmi8998_fg_get_voltage(struct pmi8998_fg_chip *chip, int *val) int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + PARAM_ADDR_BATT_VOLTAGE, 2); + rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_VOLTAGE, 2); if (rc) { pr_err("Failed to read voltage\n"); return rc; } - + //handle rev 1 too temp = readval[1] << 8 | readval[0]; - temp = twos_compliment_extend(temp, 2); - *val = div_s64((s64)temp * 122070, - 1000); - return 0; -} - -static int pmi8998_fg_get_max_charge_design(struct pmi8998_fg_chip *chip, int *val) -{ - int rc, temp; - u8 readval[2]; - - rc = pmi8998_read(chip->regmap, readval, REG_BATT(chip) + BATT_INFO_CHARGE_MAX_DESIGN, 2); - if (rc) { - pr_err("Failed to read voltage\n"); - return rc; - } - - temp = readval[1] << 8 | readval[0]; - temp = twos_compliment_extend(temp, 2); - *val = div_s64((s64)temp * 122070, - 1000); + *val = div_u64((u64)temp * 122070, 1000); return 0; } @@ -227,7 +189,7 @@ static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) u8 temp; /* clear the error */ - rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + MEM_INTF_IMA_CFG, + rc = pmi8998_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, BIT(2), BIT(2)); if (rc) { pr_err("Error writing to IMA_CFG, rc=%d\n", rc); @@ -235,26 +197,26 @@ static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) } temp = 0x4; - rc = pmi8998_write(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_ADDR_LSB + 1, 1); + rc = pmi8998_write(chip->regmap, &temp, REG_MEM + MEM_INTF_ADDR_LSB + 1, 1); if (rc) { pr_err("Error writing to MEM_INTF_ADDR_MSB, rc=%d\n", rc); return rc; } temp = 0x0; - rc = pmi8998_write(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_WR_DATA0 + 3, 1); + rc = pmi8998_write(chip->regmap, &temp, REG_MEM + MEM_INTF_WR_DATA0 + 3, 1); if (rc) { pr_err("Error writing to WR_DATA3, rc=%d\n", rc); return rc; } - rc = pmi8998_read(chip->regmap, &temp, REG_MEM(chip) + MEM_INTF_RD_DATA0 + 3, 1); + rc = pmi8998_read(chip->regmap, &temp, REG_MEM + MEM_INTF_RD_DATA0 + 3, 1); if (rc) { pr_err("Error writing to RD_DATA3, rc=%d\n", rc); return rc; } - rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + MEM_INTF_IMA_CFG, + rc = pmi8998_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, BIT(2), 0); if (rc) { pr_err("Error writing to IMA_CFG, rc=%d\n", rc); @@ -271,14 +233,14 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, bool run_err_clr_seq = false; rc = pmi8998_read(chip->regmap, &err_sts, - REG_MEM(chip) + MEM_INTF_IMA_ERR_STS, 1); + REG_MEM + MEM_INTF_IMA_ERR_STS, 1); if (rc) { dev_err(chip->dev, "failed to read IMA_ERR_STS, rc=%d\n", rc); return rc; } rc = pmi8998_read(chip->regmap, &exp_sts, - REG_MEM(chip) + MEM_INTF_IMA_EXP_STS, 1); + REG_MEM + MEM_INTF_IMA_EXP_STS, 1); if (rc) { dev_err(chip->dev, "Error in reading IMA_EXP_STS, rc=%d\n", rc); return rc; @@ -286,7 +248,7 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, if (check_hw_sts) { rc = pmi8998_read(chip->regmap, &hw_sts, - REG_MEM(chip) + MEM_INTF_IMA_HW_STS, 1); + REG_MEM + MEM_INTF_IMA_HW_STS, 1); if (rc) { dev_err(chip->dev, "Error in reading IMA_HW_STS, rc=%d\n", rc); return rc; @@ -384,6 +346,81 @@ int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ return rc; } +int pmi8998_get_prop_health_status(struct pmi8998_fg_chip *chip, int *val){ + unsigned int stat; + int rc; + + rc = regmap_read(chip->regmap, BATTERY_HEALTH_STATUS_REG(chip), &stat); + if (rc < 0){ + dev_err(chip->dev, "Health status REGMAP read failed! ret=%d\n", rc); + return rc; + } + + if (stat & BIT(0)) + *val = POWER_SUPPLY_HEALTH_COLD; + else if (stat & BIT(1)) + *val = POWER_SUPPLY_HEALTH_OVERHEAT; + else if (stat & BIT(2)) + *val = POWER_SUPPLY_HEALTH_COOL; + else if (stat & BIT(3)) + *val = POWER_SUPPLY_HEALTH_WARM; + else + *val = POWER_SUPPLY_HEALTH_GOOD; + + return rc; +} + +static int pmi8998_get_temp_threshold(struct pmi8998_fg_chip *chip, + enum power_supply_property psp, int *val) +{ + int rc; + u8 temp; + u16 reg; + + switch (psp) { + case POWER_SUPPLY_PROP_TEMP_MIN: + reg = BATT_INFO_JEITA_COLD(chip); + break; + case POWER_SUPPLY_PROP_TEMP_MAX: + reg = BATT_INFO_JEITA_HOT(chip); + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MIN: + reg = BATT_INFO_JEITA_COOL(chip); + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MAX: + reg = BATT_INFO_JEITA_WARM(chip); + break; + default: + return -EINVAL; + } + + rc = pmi8998_read(chip->regmap, &temp, reg, 1); + if (rc < 0) { + dev_err(chip->dev, "Error in reading jeita level for psp:%d, rc=%d\n", psp, rc); + return rc; + } + + /* Resolution is 0.5C. Base is -30C. */ + *val = (((5 * temp) / 10) - 30) * 10; + return 0; +} + +static void fg_get_model_name(struct pmi8998_fg_chip *chip, union power_supply_propval *val) +{ + switch (chip->subtype) + { + case PMI8998_SUBTYPE: + val->strval = "PMI8998 Battery"; + break; + case PM8998_SUBTYPE: + val->strval = "PM8998 Battery"; + break; + //handle pm660 and other socs that use fg3 + default: + val->strval = "Unknown PMIC Battery"; + } +} + static int fg_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -395,10 +432,10 @@ static int fg_get_property(struct power_supply *psy, switch (psp) { case POWER_SUPPLY_PROP_MANUFACTURER: - val->strval = "QCOM"; + val->strval = "Qualcomm"; break; case POWER_SUPPLY_PROP_MODEL_NAME: - val->strval = "PMI8998 Battery"; + fg_get_model_name(chip, val); break; case POWER_SUPPLY_PROP_TECHNOLOGY: val->intval = POWER_SUPPLY_TECHNOLOGY_LION; @@ -412,64 +449,80 @@ static int fg_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_VOLTAGE_NOW: error = pmi8998_fg_get_voltage(chip, &val->intval); break; - case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: - val->intval = chip->batt_info.batt_max_voltage_uv; - break; - case POWER_SUPPLY_PROP_TEMP: - error = pmi8998_fg_get_temperature(chip, &val->intval); - break; case POWER_SUPPLY_PROP_VOLTAGE_MIN: - val->intval = 3370000; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: + val->intval = chip->batt_min_voltage_uv; break; - case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: - case POWER_SUPPLY_PROP_CHARGE_FULL: /* TODO: Implement learning */ - val->intval = chip->batt_info.nom_cap_uah; + case POWER_SUPPLY_PROP_VOLTAGE_MAX: + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = chip->batt_max_voltage_uv; break; case POWER_SUPPLY_PROP_STATUS: error = pmi8998_get_prop_batt_status(chip, &val->intval); break; case POWER_SUPPLY_PROP_HEALTH: - val->intval = POWER_SUPPLY_HEALTH_GOOD; + error = pmi8998_get_prop_health_status(chip, &val->intval); break; + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: + case POWER_SUPPLY_PROP_CHARGE_FULL: /* TODO: Implement capacity learning */ + val->intval = chip->batt_cap_uah; + break; + case POWER_SUPPLY_PROP_TEMP: + error = pmi8998_fg_get_temperature(chip, &val->intval); + break; + case POWER_SUPPLY_PROP_TEMP_MIN: + case POWER_SUPPLY_PROP_TEMP_MAX: + case POWER_SUPPLY_PROP_TEMP_ALERT_MIN: + case POWER_SUPPLY_PROP_TEMP_ALERT_MAX: + error = pmi8998_get_temp_threshold(chip, psp, &val->intval); + break; + //POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,POWER_SUPPLY_PROP_TIME_TO_FULL_AVG - calculate time remaining for full charge - implementable + //POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG - calculate time remaining when discharging - implementable + //POWER_SUPPLY_PROP_CHARGE_NOW - requires capacity learning + //POWER_SUPPLY_PROP_CHARGE_FULL - requires capacity learning + //POWER_SUPPLY_PROP_CHARGE_COUNTER - requires capacity learning + //POWER_SUPPLY_PROP_CYCLE_COUNT - needs votables - no idea how they work + //POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT - needs votables - no idea how they work + //POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX - needs votables - no idea how they work + //POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT - needs votables - no idea how they work default: - pr_err("invalid property: %d\n", psp); + dev_err(chip->dev, "invalid property: %d\n", psp); return -EINVAL; } return error; } static const struct power_supply_desc bms_psy_desc = { - .name = "pmi8998-bms", + .name = "bms", .type = POWER_SUPPLY_TYPE_BATTERY, .properties = fg_properties, .num_properties = ARRAY_SIZE(fg_properties), .get_property = fg_get_property, }; -static int pmi8998_fg_of_battery_init(struct pmi8998_fg_chip *chip){ - struct device_node *batt_node; - struct device_node *node = chip->dev->of_node; - int rc = 0; - - batt_node = of_find_node_by_name(node, "qcom,battery-data"); - if (!batt_node) { - pr_err("No available batterydata\n"); - return rc; - } - - of_property_read_u32(batt_node, "qcom,max-voltage-uv", - &chip->batt_info.batt_max_voltage_uv_design); - - // Can be read from SRAM, hardcode in DTS for now as reading SRAM is HARD! - of_property_read_u32(batt_node, "qcom,design-capacity", - &chip->batt_info.nom_cap_uah); - - return rc; -} - irqreturn_t pmi8998_handle_usb_plugin(int irq, void *data){ struct pmi8998_fg_chip *chip = data; - dev_dbg(chip->dev, "USB IRQ called!\n"); + int rc; + unsigned int stat; + bool vbus_rising; + union power_supply_propval val; + + rc = regmap_read(chip->regmap, USBIN_BASE + INT_RT_STS, &stat); + if (rc < 0){ + dev_err(chip->dev, "Couldn't read USB status from reg! ret=%d\n", rc); + return rc; + } + vbus_rising = (bool)(stat & BIT(4)); + + if (vbus_rising) { + val.intval = POWER_SUPPLY_STATUS_CHARGING; + power_supply_set_property(chip->bms_psy, POWER_SUPPLY_PROP_STATUS, &val); + } else { + val.intval = POWER_SUPPLY_STATUS_DISCHARGING; + power_supply_set_property(chip->bms_psy, POWER_SUPPLY_PROP_STATUS, &val); + } + + dev_dbg(chip->dev, "USB IRQ: %s\n", vbus_rising ? "attached" : "detached"); power_supply_changed(chip->bms_psy); return IRQ_HANDLED; } @@ -512,13 +565,40 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } chip->chg_base = be32_to_cpu(*prop_addr); + rc = of_property_read_u32(pdev->dev.of_node, "qcom,min-voltage-uv", + &chip->batt_min_voltage_uv); + if (rc < 0) { + dev_err(chip->dev, "Error in reading qcom,min-voltage-uv, rc=%d\n", rc); + return rc; + } + + rc = of_property_read_u32(pdev->dev.of_node, "qcom,max-voltage-uv", + &chip->batt_max_voltage_uv); + if (rc < 0) { + dev_err(chip->dev, "Error in reading qcom,max-voltage-uv, rc=%d\n", rc); + return rc; + } + + rc = of_property_read_u32(pdev->dev.of_node, "qcom,battery-capacity-ua", + &chip->batt_cap_uah); + if (rc < 0) { + dev_err(chip->dev, "Error in reading qcom,battery-capacity-ua, rc=%d\n", rc); + return rc; + } + // Init memif fn inlined here (chip hardware info) - rc = pmi8998_read(chip->regmap, chip->revision, REG_MEM(chip) + DIG_MINOR, 4); + rc = pmi8998_read(chip->regmap, chip->revision, REG_MEM + DIG_MINOR, 4); if (rc) { dev_err(chip->dev, "Unable to read FG revision rc=%d\n", rc); return rc; } + rc = regmap_read(chip->regmap, PMIC_SUBTYPE, &chip->subtype); + if (rc < 0) { + dev_err(chip->dev, "Unable to read FG subtype rc=%d\n", rc); + return rc; + } + dev_dbg(chip->dev, "pmi8998 revision DIG:%d.%d ANA:%d.%d\n", chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); @@ -530,7 +610,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) * IACS_INTR_SRC_SLCT is BIT(3) */ rc = pmi8998_masked_write(chip->regmap, - REG_MEM(chip) + MEM_INTF_IMA_CFG, BIT(3), BIT(3)); + REG_MEM + MEM_INTF_IMA_CFG, BIT(3), BIT(3)); if (rc) { dev_err(chip->dev, "failed to configure interrupt source %d\n", @@ -545,14 +625,14 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } // Check and clear DMA errors - rc = pmi8998_read(chip->regmap, &dma_status, REG_MEM(chip) + 0x70, 1); + rc = pmi8998_read(chip->regmap, &dma_status, REG_MEM + 0x70, 1); if (rc < 0) { pr_err("failed to read dma_status, rc=%d\n", rc); return rc; } error_present = dma_status & (BIT(1) | BIT(2)); - rc = pmi8998_masked_write(chip->regmap, REG_MEM(chip) + 0x71, BIT(0), + rc = pmi8998_masked_write(chip->regmap, REG_MEM + 0x71, BIT(0), error_present ? BIT(0) : 0); if (rc < 0) { pr_err("failed to write dma_ctl, rc=%d\n", rc); diff --git a/drivers/power/supply/pmi8998_fg.h b/drivers/power/supply/pmi8998_fg.h index 81a90945c0e6..b44f88bc9395 100644 --- a/drivers/power/supply/pmi8998_fg.h +++ b/drivers/power/supply/pmi8998_fg.h @@ -10,7 +10,10 @@ #define MEM_INTF_RD_DATA0 0x67 #define MEM_INTF_WR_DATA0 0x63 -#define SMB2_CABLE_CONNECTED 0x06 +#define PMIC_SUBTYPE 0x105 + +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 // pm8950 / pm89988 common #define MEM_INTF_IMA_CFG 0x52 @@ -33,9 +36,9 @@ #define BATT_TEMP_LSB_MASK GENMASK(7, 0) #define BATT_TEMP_MSB_MASK GENMASK(2, 0) -#define REG_BASE(chip) (chip->base) -#define REG_BATT(chip) (chip->base + 0x100) -#define REG_MEM(chip) (chip->base + 0x400) +#define REG_BASE 0x4000 +#define REG_BATT 0x4100 +#define REG_MEM 0x4400 /* Interrupt offsets */ #define INT_RT_STS 0x10 @@ -46,9 +49,17 @@ #define PARAM_ADDR_BATT_VOLTAGE 0xa0 #define PARAM_ADDR_BATT_CURRENT 0xa2 +#define BATT_INFO_JEITA_COLD(chip) (REG_BATT + 0x62) +#define BATT_INFO_JEITA_COOL(chip) (REG_BATT + 0x63) +#define BATT_INFO_JEITA_WARM(chip) (REG_BATT + 0x64) +#define BATT_INFO_JEITA_HOT(chip) (REG_BATT + 0x65) + #define MISC_BASE 0x1600 +#define USBIN_BASE 0x1300 #define BATTERY_CHARGER_STATUS_REG(chip) (chip->chg_base + 0x06) +#define BATTERY_HEALTH_STATUS_REG(chip) (chip->chg_base + 0x07) + #define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0) #define POWER_PATH_STATUS_REG (MISC_BASE + 0x0B) @@ -87,41 +98,18 @@ static enum power_supply_property fg_properties[] = { POWER_SUPPLY_PROP_CAPACITY, POWER_SUPPLY_PROP_CURRENT_NOW, POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_MIN, - POWER_SUPPLY_PROP_TEMP, - // POWER_SUPPLY_PROP_CHARGE_NOW, - // POWER_SUPPLY_PROP_CHARGE_FULL, - POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, - POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, POWER_SUPPLY_PROP_STATUS, -}; - -struct fg_learning_data { - struct mutex learning_lock; - bool active; - int64_t cc_uah; - int learned_cc_uah; - int init_cc_pc_val; - int max_start_soc; - int max_increment; - int max_decrement; - int vbat_est_thr_uv; - int max_cap_limit; - int min_cap_limit; - int min_temp; - int max_temp; -}; - -struct battery_info { - const char *manufacturer; - const char *model; - const char *serial_num; - - int nom_cap_uah; - - int batt_max_voltage_uv_design; - int batt_max_voltage_uv; + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TEMP_MIN, + POWER_SUPPLY_PROP_TEMP_MAX, + POWER_SUPPLY_PROP_TEMP_ALERT_MIN, + POWER_SUPPLY_PROP_TEMP_ALERT_MAX, }; struct pmi8998_fg_chip { @@ -130,15 +118,16 @@ struct pmi8998_fg_chip { unsigned int chg_base; struct regmap *regmap; struct mutex lock; + unsigned int subtype; struct power_supply *bms_psy; u8 revision[4]; bool ima_supported; - struct battery_info batt_info; - - struct fg_learning_data learning_data; + int batt_cap_uah; + int batt_max_voltage_uv; + int batt_min_voltage_uv; int health; int status; From fff3a97cdc18e154fc93bc67bcfcbc0e22e495ce Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 25 Dec 2020 12:57:15 +0530 Subject: [PATCH 131/174] arm64: dts: qcom: sdm845-oneplus: enable pmi8998 fuel guage Enable the new pmi8998 fuel gauge Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 3 --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 9 ++++++++- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 4 ++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 4 ++++ 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index ad509c25cac3..d1239cc224f0 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -29,9 +29,6 @@ reg = <0x4000 0x1000>; interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "usb-plugin"; - qcom,max-voltage-uv = <4400000>; - qcom,min-voltage-uv = <3700000>; - qcom,battery-capacity-ua = <4000000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7f42e5315ecb..b9a20fed9432 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -450,6 +450,13 @@ }; }; +&pmi8998_fg { + status = "okay"; + + qcom,max-voltage-uv = <4400000>; + qcom,min-voltage-uv = <3700000>; +}; + &qupv3_id_1 { status = "okay"; }; @@ -619,7 +626,7 @@ pins = "gpio6", "gpio25", "gpio26"; function = "gpio"; drive-strength = <8>; - bias-disable = <0>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 5936b47dee5f..42cfaf3355e6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -15,6 +15,10 @@ qcom,board-id = <8 0 17819 22>; }; +&pmi8998_fg { + qcom,battery-capacity-ua = <3300000>; +}; + &display_panel { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 78a0b99144e6..fe52d888f739 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -21,6 +21,10 @@ compatible = "samsung,s6e3fc2x01"; }; +&pmi8998_fg { + qcom,battery-capacity-ua = <3700000>; +}; + &rmi4_f12 { touchscreen-y-mm = <148>; }; From 87e5901e2b811e327652d4c4c43422d402f25e7e Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sat, 6 Mar 2021 07:55:07 +0400 Subject: [PATCH 132/174] power: pmi8998_fg: Remove some trailing spaces and tabs This should be squashed. --- drivers/power/supply/pmi8998_fg.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/power/supply/pmi8998_fg.c b/drivers/power/supply/pmi8998_fg.c index 1aea6eaf30f9..aa848e5577fe 100644 --- a/drivers/power/supply/pmi8998_fg.c +++ b/drivers/power/supply/pmi8998_fg.c @@ -22,7 +22,7 @@ /** * pmi8998_read() - Read multiple registers with regmap_bulk_read - * + * * @param map The regmap to read * @param val Pointer to read values into * @param addr Address to read from @@ -43,7 +43,7 @@ static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) /** * @brief pmi8998_write() - Write multiple registers with regmap_bulk_write - * + * * @param map The regmap to write * @param val Pointer to write values into * @param addr Address to write from @@ -73,7 +73,7 @@ static int pmi8998_write(struct regmap *map, u8 *val, u16 addr, int len) /** * @brief pmi8998_masked_write() - like pmi8998_write but applies * a mask first. - * + * * @param map The regmap to write * @param val Pointer to write values into * @param addr Address to write from @@ -321,7 +321,7 @@ int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ dev_err(chip->dev, "Charging status REGMAP read failed! ret=%d\n", rc); return rc; } - + stat = stat & BATTERY_CHARGER_STATUS_MASK; dev_dbg(chip->dev, "Charging status : %d!\n", stat); @@ -338,7 +338,7 @@ int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ case DISABLE_CHARGE: *val = POWER_SUPPLY_STATUS_NOT_CHARGING; break; - default: + default: *val = POWER_SUPPLY_STATUS_UNKNOWN; break; } @@ -366,7 +366,7 @@ int pmi8998_get_prop_health_status(struct pmi8998_fg_chip *chip, int *val){ *val = POWER_SUPPLY_HEALTH_WARM; else *val = POWER_SUPPLY_HEALTH_GOOD; - + return rc; } @@ -520,7 +520,7 @@ irqreturn_t pmi8998_handle_usb_plugin(int irq, void *data){ } else { val.intval = POWER_SUPPLY_STATUS_DISCHARGING; power_supply_set_property(chip->bms_psy, POWER_SUPPLY_PROP_STATUS, &val); - } + } dev_dbg(chip->dev, "USB IRQ: %s\n", vbus_rising ? "attached" : "detached"); power_supply_changed(chip->bms_psy); @@ -578,7 +578,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) dev_err(chip->dev, "Error in reading qcom,max-voltage-uv, rc=%d\n", rc); return rc; } - + rc = of_property_read_u32(pdev->dev.of_node, "qcom,battery-capacity-ua", &chip->batt_cap_uah); if (rc < 0) { @@ -602,7 +602,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) dev_dbg(chip->dev, "pmi8998 revision DIG:%d.%d ANA:%d.%d\n", chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); - + /* * Change the FG_MEM_INT interrupt to track IACS_READY * condition instead of end-of-transaction. This makes sure From 2eea5fe9f8efcc063837d7d385c638feb3a3e810 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Fri, 5 Mar 2021 21:37:13 +0400 Subject: [PATCH 133/174] power: pmi8998_fg: Rename to qcom_fg and add support for PMI8994/6 This adds support for accessing SRAM. That includes requesting and releasing access to SRAM by setting some registers and handling the mem-avail IRQ, configuring access, and reading from/writing to it. Pre-gen3 fuel gauges require reading from SRAM to get voltage, current and temperature data. Getting capacity is identical to gen3. Tested on Xiaomi Mi Note 2 with PMI8996. --- drivers/power/supply/Kconfig | 8 +- drivers/power/supply/Makefile | 2 +- .../power/supply/{pmi8998_fg.c => qcom_fg.c} | 599 ++++++++++++++++-- .../power/supply/{pmi8998_fg.h => qcom_fg.h} | 90 ++- 4 files changed, 599 insertions(+), 100 deletions(-) rename drivers/power/supply/{pmi8998_fg.c => qcom_fg.c} (50%) rename drivers/power/supply/{pmi8998_fg.h => qcom_fg.h} (60%) diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 0eb25bc8e7e6..a6031c0e01e5 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -866,13 +866,13 @@ config CHARGER_SURFACE Microsoft Surface devices, i.e. Surface Pro 7, Surface Laptop 3, Surface Book 3, and Surface Laptop Go. -config BATTERY_PMI8998_FG - tristate "Qualcomm PMI8998 fuel gauge driver" +config BATTERY_QCOM_FG + tristate "Qualcomm PMIC fuel gauge driver" depends on MFD_SPMI_PMIC help - Say Y here to enable the Qualcomm PMI8998 Fuel Gauge driver. This + Say Y here to enable the Qualcomm PMIC Fuel Gauge driver. This adds support for battery fuel gauging and state of charge of - battery connected tothe fuel gauge. The state of charge is + battery connected to the fuel gauge. The state of charge is reported through a BMS power supply property and also sends uevents when the capacity is updated. diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 7e325b7fa246..8a200117de90 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -105,4 +105,4 @@ obj-$(CONFIG_RN5T618_POWER) += rn5t618_power.o obj-$(CONFIG_BATTERY_ACER_A500) += acer_a500_battery.o obj-$(CONFIG_BATTERY_SURFACE) += surface_battery.o obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o -obj-$(CONFIG_BATTERY_PMI8998_FG) += pmi8998_fg.o +obj-$(CONFIG_BATTERY_QCOM_FG) += qcom_fg.o diff --git a/drivers/power/supply/pmi8998_fg.c b/drivers/power/supply/qcom_fg.c similarity index 50% rename from drivers/power/supply/pmi8998_fg.c rename to drivers/power/supply/qcom_fg.c index aa848e5577fe..dc41f6072828 100644 --- a/drivers/power/supply/pmi8998_fg.c +++ b/drivers/power/supply/qcom_fg.c @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -14,14 +15,14 @@ #include #include -#include "pmi8998_fg.h" +#include "qcom_fg.h" /************************ * IO FUNCTIONS * **********************/ /** - * pmi8998_read() - Read multiple registers with regmap_bulk_read + * qcom_fg_read() - Read multiple registers with regmap_bulk_read * * @param map The regmap to read * @param val Pointer to read values into @@ -29,7 +30,7 @@ * @param len Number of registers (bytes) to read * @return int 0 on success, negative errno on error */ -static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) +static int qcom_fg_read(struct regmap *map, u8 *val, u16 addr, int len) { if ((addr & 0xff00) == 0) { pr_err("base cannot be zero base=0x%02x\n", addr); @@ -42,7 +43,7 @@ static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) } /** - * @brief pmi8998_write() - Write multiple registers with regmap_bulk_write + * @brief qcom_fg_write() - Write multiple registers with regmap_bulk_write * * @param map The regmap to write * @param val Pointer to write values into @@ -50,7 +51,7 @@ static int pmi8998_read(struct regmap *map, u8 *val, u16 addr, int len) * @param len Number of registers (bytes) to write * @return int 0 on success, negative errno on error */ -static int pmi8998_write(struct regmap *map, u8 *val, u16 addr, int len) +static int qcom_fg_write(struct regmap *map, u8 *val, u16 addr, int len) { int rc; bool sec_access = (addr & 0xff) > 0xd0; @@ -71,7 +72,7 @@ static int pmi8998_write(struct regmap *map, u8 *val, u16 addr, int len) } /** - * @brief pmi8998_masked_write() - like pmi8998_write but applies + * @brief qcom_fg_masked_write() - like qcom_fg_write but applies * a mask first. * * @param map The regmap to write @@ -80,19 +81,19 @@ static int pmi8998_write(struct regmap *map, u8 *val, u16 addr, int len) * @param len Number of registers (bytes) to write * @return int 0 on success, negative errno on error */ -static int pmi8998_masked_write(struct regmap *map, u16 addr, +static int qcom_fg_masked_write(struct regmap *map, u16 addr, u8 mask, u8 val) { int error; u8 reg; - error = pmi8998_read(map, ®, addr, 1); + error = qcom_fg_read(map, ®, addr, 1); if (error) return error; reg &= ~mask; reg |= val & mask; - error = pmi8998_write(map, ®, addr, 1); + error = qcom_fg_write(map, ®, addr, 1); return error; } @@ -111,14 +112,243 @@ static int64_t twos_compliment_extend(int64_t val, int nbytes) return val; } +/************************ + * SRAM FUNCTIONS + * **********************/ + +/** + * qcom_fg_sram_check_access() - Check if SRAM is accessible + * + * @param chip Pointer to chip + * @return bool true if accessible, false otherwise + */ +static bool qcom_fg_sram_check_access(struct qcom_fg_chip *chip) +{ + int rc; + u8 mem_if_status; + + rc = qcom_fg_read(chip->regmap, &mem_if_status, + REG_MEM + MEM_INTF_STS, 1); + + if(!(mem_if_status & MEM_INTF_AVAIL)) + return false; + + rc = qcom_fg_read(chip->regmap, &mem_if_status, + REG_MEM + MEM_INTF_CFG, 1); + + if(rc) + return false; + + return !!(mem_if_status & RIF_MEM_ACCESS_REQ); +} + +/** + * qcom_fg_sram_request_access() - Request access to SRAM and wait for it + * + * @param chip Pointer to chip + * @return int 0 on success, negative errno on error + */ +static int qcom_fg_sram_request_access(struct qcom_fg_chip *chip) +{ + int rc; + + if(!qcom_fg_sram_check_access(chip)) { + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + MEM_INTF_CFG, + RIF_MEM_ACCESS_REQ, RIF_MEM_ACCESS_REQ); + if (rc) { + dev_err(chip->dev, + "Failed to set SRAM access request bit: %d\n", rc); + return rc; + } + } + + /* Wait to get access to SRAM, and try again if interrupted */ + do { + rc = wait_for_completion_interruptible_timeout( + &chip->sram_access_granted, + msecs_to_jiffies(MEM_IF_TIMEOUT_MS)); + } while(rc == -ERESTARTSYS); + + if(rc <= 0) { + rc = -ETIMEDOUT; + return rc; + } + + return 0; +} + +/** + * qcom_fg_sram_release_access() - Release access to SRAM + * + * @param chip Pointer to chip + * @return int 0 on success, negative errno on error + */ +static int qcom_fg_sram_release_access(struct qcom_fg_chip *chip) +{ + int rc; + + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + MEM_INTF_CFG, + RIF_MEM_ACCESS_REQ, 0); + if (rc) { + dev_err(chip->dev, + "Failed to set SRAM access request bit: %d\n", rc); + return rc; + } + + reinit_completion(&chip->sram_access_granted); + + return rc; +} + +/** + * qcom_fg_sram_config_access() - Configure access to SRAM + * + * @param chip Pointer to chip + * @param write 0 for read access, 1 for write access + * @param burst 1 to access mutliple addresses successively + * @return int 0 on success, negative errno on error + */ +static int qcom_fg_sram_config_access(struct qcom_fg_chip *chip, + bool write, bool burst) +{ + int rc; + u8 intf_ctl = (write ? MEM_INTF_CTL_WR_EN : 0) + | (burst ? MEM_INTF_CTL_BURST : 0); + + rc = qcom_fg_write(chip->regmap, &intf_ctl, + REG_MEM + MEM_INTF_CTL, 1); + + if(rc) + dev_err(chip->dev, + "Failed to configure SRAM access: %d\n", rc); + + return rc; +} + +/** + * qcom_fg_sram_read() - Read data from SRAM + * + * @param chip Pointer to chip + * @param val Pointer to read values into + * @param addr Address to read from + * @param len Number of bytes to read + * @return int 0 on success, negative errno on error + */ +static int qcom_fg_sram_read(struct qcom_fg_chip *chip, + u8 *val, u16 addr, int len, int offset) +{ + int rc; + u8 *rd_data = val; + + rc = qcom_fg_sram_request_access(chip); + if(rc) { + dev_err(chip->dev, "Failed to request SRAM access: %d", rc); + return rc; + } + + dev_dbg(chip->dev, + "Reading address 0x%x with offset %d of length %d from SRAM", + addr, len, offset); + + rc = qcom_fg_sram_config_access(chip, 0, (len > 4)); + if(rc) { + dev_err(chip->dev, "Failed to configure SRAM access: %d", rc); + return rc; + } + + while(len > 0) { + /* Set SRAM address register */ + rc = qcom_fg_write(chip->regmap, (u8 *) &addr, + REG_MEM + MEM_INTF_ADDR_LSB, 2); + if(rc) { + dev_err(chip->dev, "Failed to set SRAM address: %d", rc); + return rc; + } + + rc = qcom_fg_read(chip->regmap, rd_data, + REG_MEM + MEM_INTF_RD_DATA0 + offset, len); + + addr += 4; + + if(rc) + return rc; + + rd_data += 4 - offset; + len -= 4 - offset; + offset = 0; + } + + rc = qcom_fg_sram_release_access(chip); + + return rc; +} + +/** + * qcom_fg_sram_write() - Write data to SRAM + * + * @param chip Pointer to chip + * @param val Pointer to write values into + * @param addr Address to write to + * @param len Number of bytes to write + * @return int 0 on success, negative errno on error + */ +static int qcom_fg_sram_write(struct qcom_fg_chip *chip, + u8 *val, u16 addr, int len, int offset) +{ + int rc; + u8 *wr_data = val; + + rc = qcom_fg_sram_request_access(chip); + if(rc) { + dev_err(chip->dev, "Failed to request SRAM access: %d", rc); + return rc; + } + + dev_dbg(chip->dev, + "Reading address 0x%x with offset %d of length %d from SRAM", + addr, len, offset); + + rc = qcom_fg_sram_config_access(chip, 1, (len > 4)); + if(rc) { + dev_err(chip->dev, "Failed to configure SRAM access: %d", rc); + return rc; + } + + while(len > 0) { + /* Set SRAM address register */ + rc = qcom_fg_write(chip->regmap, (u8 *) &addr, + REG_MEM + MEM_INTF_ADDR_LSB, 2); + if(rc) { + dev_err(chip->dev, "Failed to set SRAM address: %d", rc); + return rc; + } + + rc = qcom_fg_write(chip->regmap, wr_data, + REG_MEM + MEM_INTF_WR_DATA0 + offset, len); + + addr += 4; + + if(rc) + return rc; + + wr_data += 4 - offset; + len -= 4 - offset; + offset = 0; + } + + rc = qcom_fg_sram_release_access(chip); + + return rc; +} + /************************* * Battery Status RW * ***********************/ -static int pmi8998_fg_get_capacity(struct pmi8998_fg_chip *chip, int *val) +static int qcom_fg_get_capacity(struct qcom_fg_chip *chip, int *val) { u8 cap[2]; - int error = pmi8998_read(chip->regmap, cap, REG_BASE + BATT_MONOTONIC_SOC, 2); + int error = qcom_fg_read(chip->regmap, cap, REG_BASE + BATT_MONOTONIC_SOC, 2); if (error) return error; if (cap[0] != cap[1]) { @@ -128,12 +358,66 @@ static int pmi8998_fg_get_capacity(struct pmi8998_fg_chip *chip, int *val) return 0; } -static int pmi8998_fg_get_temperature(struct pmi8998_fg_chip *chip, int *val) +static int qcom_fg_get_temperature(struct qcom_fg_chip *chip, int *val) { int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_TEMP, 2); + rc = qcom_fg_sram_read(chip, readval, 0x550, 2, 2); + if(rc) { + dev_err(chip->dev, "Failed to read temperature: %d", rc); + return rc; + } + + temp = readval[1] << 8 | readval[0]; + *val = temp * 625 / 1000 - 2730; + return 0; +} + +static int qcom_fg_get_current(struct qcom_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = qcom_fg_sram_read(chip, readval, 0x5CC, 2, 3); + if(rc) { + dev_err(chip->dev, "Failed to read current: %d", rc); + return rc; + } + //handle rev 1 too + temp = readval[1] << 8 | readval[0]; + temp = twos_compliment_extend(temp, 15); + *val = div_s64((s64)temp * 152587, 1000); + return 0; +} + +static int qcom_fg_get_voltage(struct qcom_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = qcom_fg_sram_read(chip, readval, 0x5CC, 2, 1); + if(rc) { + dev_err(chip->dev, "Failed to read voltage: %d", rc); + return rc; + } + + temp = readval[1] << 8 | readval[0]; + *val = div_u64((u64)temp * 152587, 1000); + + return 0; +} + +/************************* + * Battery Status RW, Gen3 + * ***********************/ + +static int qcom_fg_gen3_get_temperature(struct qcom_fg_chip *chip, int *val) +{ + int rc, temp; + u8 readval[2]; + + rc = qcom_fg_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_TEMP, 2); if (rc) { pr_err("Failed to read temperature\n"); return rc; @@ -146,12 +430,12 @@ static int pmi8998_fg_get_temperature(struct pmi8998_fg_chip *chip, int *val) return 0; } -static int pmi8998_fg_get_current(struct pmi8998_fg_chip *chip, int *val) +static int qcom_fg_gen3_get_current(struct qcom_fg_chip *chip, int *val) { int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_CURRENT, 2); + rc = qcom_fg_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_CURRENT, 2); if (rc) { pr_err("Failed to read current\n"); return rc; @@ -163,12 +447,12 @@ static int pmi8998_fg_get_current(struct pmi8998_fg_chip *chip, int *val) return 0; } -static int pmi8998_fg_get_voltage(struct pmi8998_fg_chip *chip, int *val) +static int qcom_fg_gen3_get_voltage(struct qcom_fg_chip *chip, int *val) { int rc, temp; u8 readval[2]; - rc = pmi8998_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_VOLTAGE, 2); + rc = qcom_fg_read(chip->regmap, readval, REG_BATT + PARAM_ADDR_BATT_VOLTAGE, 2); if (rc) { pr_err("Failed to read voltage\n"); return rc; @@ -183,13 +467,13 @@ static int pmi8998_fg_get_voltage(struct pmi8998_fg_chip *chip, int *val) * Init stuff * ******************/ -static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) +static int qcom_fg_iacs_clear_sequence(struct qcom_fg_chip *chip) { int rc = 0; u8 temp; /* clear the error */ - rc = pmi8998_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, BIT(2), BIT(2)); if (rc) { pr_err("Error writing to IMA_CFG, rc=%d\n", rc); @@ -197,26 +481,26 @@ static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) } temp = 0x4; - rc = pmi8998_write(chip->regmap, &temp, REG_MEM + MEM_INTF_ADDR_LSB + 1, 1); + rc = qcom_fg_write(chip->regmap, &temp, REG_MEM + MEM_INTF_ADDR_LSB + 1, 1); if (rc) { pr_err("Error writing to MEM_INTF_ADDR_MSB, rc=%d\n", rc); return rc; } temp = 0x0; - rc = pmi8998_write(chip->regmap, &temp, REG_MEM + MEM_INTF_WR_DATA0 + 3, 1); + rc = qcom_fg_write(chip->regmap, &temp, REG_MEM + MEM_INTF_WR_DATA0 + 3, 1); if (rc) { pr_err("Error writing to WR_DATA3, rc=%d\n", rc); return rc; } - rc = pmi8998_read(chip->regmap, &temp, REG_MEM + MEM_INTF_RD_DATA0 + 3, 1); + rc = qcom_fg_read(chip->regmap, &temp, REG_MEM + MEM_INTF_RD_DATA0 + 3, 1); if (rc) { pr_err("Error writing to RD_DATA3, rc=%d\n", rc); return rc; } - rc = pmi8998_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, BIT(2), 0); if (rc) { pr_err("Error writing to IMA_CFG, rc=%d\n", rc); @@ -225,21 +509,21 @@ static int pmi8998_iacs_clear_sequence(struct pmi8998_fg_chip *chip) return rc; } -static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, +static int qcom_fg_clear_ima(struct qcom_fg_chip *chip, bool check_hw_sts) { int rc = 0, ret = 0; u8 err_sts = 0, exp_sts = 0, hw_sts = 0; bool run_err_clr_seq = false; - rc = pmi8998_read(chip->regmap, &err_sts, + rc = qcom_fg_read(chip->regmap, &err_sts, REG_MEM + MEM_INTF_IMA_ERR_STS, 1); if (rc) { dev_err(chip->dev, "failed to read IMA_ERR_STS, rc=%d\n", rc); return rc; } - rc = pmi8998_read(chip->regmap, &exp_sts, + rc = qcom_fg_read(chip->regmap, &exp_sts, REG_MEM + MEM_INTF_IMA_EXP_STS, 1); if (rc) { dev_err(chip->dev, "Error in reading IMA_EXP_STS, rc=%d\n", rc); @@ -247,7 +531,7 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, } if (check_hw_sts) { - rc = pmi8998_read(chip->regmap, &hw_sts, + rc = qcom_fg_read(chip->regmap, &hw_sts, REG_MEM + MEM_INTF_IMA_HW_STS, 1); if (rc) { dev_err(chip->dev, "Error in reading IMA_HW_STS, rc=%d\n", rc); @@ -272,7 +556,7 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, } if (run_err_clr_seq) { - ret = pmi8998_iacs_clear_sequence(chip); + ret = qcom_fg_iacs_clear_sequence(chip); if (!ret) return -EAGAIN; else @@ -282,7 +566,7 @@ static int pmi8998_clear_ima(struct pmi8998_fg_chip *chip, return rc; } -int pmi8998_get_prop_usb_online(struct pmi8998_fg_chip *chip, int *val){ +int qcom_fg_get_prop_usb_online(struct qcom_fg_chip *chip, int *val){ unsigned int stat; int rc; @@ -297,13 +581,13 @@ int pmi8998_get_prop_usb_online(struct pmi8998_fg_chip *chip, int *val){ return rc; } -int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ +int qcom_fg_get_prop_batt_status(struct qcom_fg_chip *chip, int *val){ int usb_online_val; unsigned int stat; int rc; bool usb_online; - rc = pmi8998_get_prop_usb_online(chip, &usb_online_val); + rc = qcom_fg_get_prop_usb_online(chip, &usb_online_val); if (rc < 0) { dev_err(chip->dev, "Couldn't get usb online property rc=%d\n", rc); return rc; @@ -346,7 +630,7 @@ int pmi8998_get_prop_batt_status(struct pmi8998_fg_chip *chip, int *val){ return rc; } -int pmi8998_get_prop_health_status(struct pmi8998_fg_chip *chip, int *val){ +int qcom_fg_get_prop_health_status(struct qcom_fg_chip *chip, int *val){ unsigned int stat; int rc; @@ -370,7 +654,42 @@ int pmi8998_get_prop_health_status(struct pmi8998_fg_chip *chip, int *val){ return rc; } -static int pmi8998_get_temp_threshold(struct pmi8998_fg_chip *chip, +static int qcom_fg_get_temp_threshold(struct qcom_fg_chip *chip, + enum power_supply_property psp, int *val) +{ + int rc; + u8 temp; + int offset; + + switch (psp) { + case POWER_SUPPLY_PROP_TEMP_MIN: + offset = 0; + break; + case POWER_SUPPLY_PROP_TEMP_MAX: + offset = 1; + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MIN: + offset = 2; + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MAX: + offset = 3; + break; + default: + return -EINVAL; + } + + rc = qcom_fg_sram_read(chip, &temp, 0x454, 1, offset); + if (rc < 0) { + dev_err(chip->dev, "Error in reading jeita level for psp:%d, rc=%d\n", psp, rc); + return rc; + } + + *val = (temp - 30) * 10; + + return 0; +} + +static int qcom_fg_gen3_get_temp_threshold(struct qcom_fg_chip *chip, enum power_supply_property psp, int *val) { int rc; @@ -394,7 +713,7 @@ static int pmi8998_get_temp_threshold(struct pmi8998_fg_chip *chip, return -EINVAL; } - rc = pmi8998_read(chip->regmap, &temp, reg, 1); + rc = qcom_fg_read(chip->regmap, &temp, reg, 1); if (rc < 0) { dev_err(chip->dev, "Error in reading jeita level for psp:%d, rc=%d\n", psp, rc); return rc; @@ -405,17 +724,66 @@ static int pmi8998_get_temp_threshold(struct pmi8998_fg_chip *chip, return 0; } -static void fg_get_model_name(struct pmi8998_fg_chip *chip, union power_supply_propval *val) +static int qcom_fg_set_temp_threshold(struct qcom_fg_chip *chip, + enum power_supply_property psp, int val) +{ + int rc; + u8 temp; + int offset; + + switch (psp) { + case POWER_SUPPLY_PROP_TEMP_MIN: + offset = 0; + break; + case POWER_SUPPLY_PROP_TEMP_MAX: + offset = 1; + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MIN: + offset = 2; + break; + case POWER_SUPPLY_PROP_TEMP_ALERT_MAX: + offset = 3; + break; + default: + return -EINVAL; + } + + temp = val / 10 + 30; + + rc = qcom_fg_sram_write(chip, &temp, 0x454, 1, offset); + if (rc < 0) { + dev_err(chip->dev, "Error in writing jeita level for psp:%d, rc=%d\n", psp, rc); + return rc; + } + + return 0; +} + +static int qcom_fg_gen3_set_temp_threshold(struct qcom_fg_chip *chip, + enum power_supply_property psp, int val) +{ + /* Not implemented yet */ + return -ENOTSUPP; +} + + +static void qcom_fg_get_model_name(struct qcom_fg_chip *chip, union power_supply_propval *val) { switch (chip->subtype) { + case PMI8994_SUBTYPE: + val->strval = "PMI8994 Battery"; + break; + case PMI8996_SUBTYPE: + val->strval = "PMI8996 Battery"; + break; case PMI8998_SUBTYPE: val->strval = "PMI8998 Battery"; break; case PM8998_SUBTYPE: val->strval = "PM8998 Battery"; break; - //handle pm660 and other socs that use fg3 + /* Handle other PMICs */ default: val->strval = "Unknown PMIC Battery"; } @@ -425,7 +793,7 @@ static int fg_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) { - struct pmi8998_fg_chip *chip = power_supply_get_drvdata(psy); + struct qcom_fg_chip *chip = power_supply_get_drvdata(psy); int error = 0; dev_dbg(chip->dev, "Getting property: %d", psp); @@ -435,19 +803,19 @@ static int fg_get_property(struct power_supply *psy, val->strval = "Qualcomm"; break; case POWER_SUPPLY_PROP_MODEL_NAME: - fg_get_model_name(chip, val); + qcom_fg_get_model_name(chip, val); break; case POWER_SUPPLY_PROP_TECHNOLOGY: val->intval = POWER_SUPPLY_TECHNOLOGY_LION; break; case POWER_SUPPLY_PROP_CAPACITY: - error = pmi8998_fg_get_capacity(chip, &val->intval); + error = chip->ops->get_capacity(chip, &val->intval); break; case POWER_SUPPLY_PROP_CURRENT_NOW: - error = pmi8998_fg_get_current(chip, &val->intval); + error = chip->ops->get_current(chip, &val->intval); break; case POWER_SUPPLY_PROP_VOLTAGE_NOW: - error = pmi8998_fg_get_voltage(chip, &val->intval); + error = chip->ops->get_voltage(chip, &val->intval); break; case POWER_SUPPLY_PROP_VOLTAGE_MIN: case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: @@ -458,23 +826,23 @@ static int fg_get_property(struct power_supply *psy, val->intval = chip->batt_max_voltage_uv; break; case POWER_SUPPLY_PROP_STATUS: - error = pmi8998_get_prop_batt_status(chip, &val->intval); + error = chip->ops->get_batt_status(chip, &val->intval); break; case POWER_SUPPLY_PROP_HEALTH: - error = pmi8998_get_prop_health_status(chip, &val->intval); + error = chip->ops->get_health_status(chip, &val->intval); break; case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: case POWER_SUPPLY_PROP_CHARGE_FULL: /* TODO: Implement capacity learning */ val->intval = chip->batt_cap_uah; break; case POWER_SUPPLY_PROP_TEMP: - error = pmi8998_fg_get_temperature(chip, &val->intval); + error = chip->ops->get_temperature(chip, &val->intval); break; case POWER_SUPPLY_PROP_TEMP_MIN: case POWER_SUPPLY_PROP_TEMP_MAX: case POWER_SUPPLY_PROP_TEMP_ALERT_MIN: case POWER_SUPPLY_PROP_TEMP_ALERT_MAX: - error = pmi8998_get_temp_threshold(chip, psp, &val->intval); + error = chip->ops->get_temp_threshold(chip, psp, &val->intval); break; //POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,POWER_SUPPLY_PROP_TIME_TO_FULL_AVG - calculate time remaining for full charge - implementable //POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG - calculate time remaining when discharging - implementable @@ -500,8 +868,8 @@ static const struct power_supply_desc bms_psy_desc = { .get_property = fg_get_property, }; -irqreturn_t pmi8998_handle_usb_plugin(int irq, void *data){ - struct pmi8998_fg_chip *chip = data; +irqreturn_t qcom_fg_handle_usb_plugin(int irq, void *data){ + struct qcom_fg_chip *chip = data; int rc; unsigned int stat; bool vbus_rising; @@ -527,10 +895,47 @@ irqreturn_t pmi8998_handle_usb_plugin(int irq, void *data){ return IRQ_HANDLED; } -static int pmi8998_fg_probe(struct platform_device *pdev) +irqreturn_t qcom_fg_handle_mem_avail(int irq, void *data){ + struct qcom_fg_chip *chip = data; + + if(qcom_fg_sram_check_access(chip)) { + complete_all(&chip->sram_access_granted); + dev_dbg(chip->dev, "SRAM access granted"); + } else { + dev_dbg(chip->dev, "SRAM access revoked"); + } + + return IRQ_HANDLED; +} + +/* Pre-Gen3 fuel gauge. PMI8996 and older */ +static const struct qcom_fg_ops ops_fg = { + .get_capacity = qcom_fg_get_capacity, + .get_temperature = qcom_fg_get_temperature, + .get_current = qcom_fg_get_current, + .get_voltage = qcom_fg_get_voltage, + .get_batt_status = qcom_fg_get_prop_batt_status, + .get_health_status = qcom_fg_get_prop_health_status, + .get_temp_threshold = qcom_fg_get_temp_threshold, + .set_temp_threshold = qcom_fg_set_temp_threshold, +}; + +/* Gen3 fuel gauge. PMI8998 and newer */ +static const struct qcom_fg_ops ops_fg_gen3 = { + .get_capacity = qcom_fg_get_capacity, + .get_temperature = qcom_fg_gen3_get_temperature, + .get_current = qcom_fg_gen3_get_current, + .get_voltage = qcom_fg_gen3_get_voltage, + .get_batt_status = qcom_fg_get_prop_batt_status, + .get_health_status = qcom_fg_get_prop_health_status, + .get_temp_threshold = qcom_fg_gen3_get_temp_threshold, + .set_temp_threshold = qcom_fg_gen3_set_temp_threshold, +}; + +static int qcom_fg_probe(struct platform_device *pdev) { struct power_supply_config supply_config = {}; - struct pmi8998_fg_chip *chip; + struct qcom_fg_chip *chip; const __be32 *prop_addr; int rc = 0, irq; u8 dma_status; @@ -542,6 +947,8 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } chip->dev = &pdev->dev; + chip->ops = of_device_get_match_data(&pdev->dev); + mutex_init(&chip->lock); chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); @@ -587,7 +994,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) } // Init memif fn inlined here (chip hardware info) - rc = pmi8998_read(chip->regmap, chip->revision, REG_MEM + DIG_MINOR, 4); + rc = qcom_fg_read(chip->regmap, chip->revision, REG_MEM + DIG_MINOR, 4); if (rc) { dev_err(chip->dev, "Unable to read FG revision rc=%d\n", rc); return rc; @@ -599,7 +1006,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) return rc; } - dev_dbg(chip->dev, "pmi8998 revision DIG:%d.%d ANA:%d.%d\n", + dev_dbg(chip->dev, "PMIC revision DIG:%d.%d ANA:%d.%d\n", chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR], chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]); @@ -609,7 +1016,7 @@ static int pmi8998_fg_probe(struct platform_device *pdev) * that the next transaction starts only after the hw is ready. * IACS_INTR_SRC_SLCT is BIT(3) */ - rc = pmi8998_masked_write(chip->regmap, + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + MEM_INTF_IMA_CFG, BIT(3), BIT(3)); if (rc) { dev_err(chip->dev, @@ -618,21 +1025,21 @@ static int pmi8998_fg_probe(struct platform_device *pdev) return rc; } - rc = pmi8998_clear_ima(chip, true); + rc = qcom_fg_clear_ima(chip, true); if (rc && rc != -EAGAIN) { dev_err(chip->dev, "Error clearing IMA, exception rc=%d", rc); return rc; } // Check and clear DMA errors - rc = pmi8998_read(chip->regmap, &dma_status, REG_MEM + 0x70, 1); + rc = qcom_fg_read(chip->regmap, &dma_status, REG_MEM + 0x70, 1); if (rc < 0) { pr_err("failed to read dma_status, rc=%d\n", rc); return rc; } error_present = dma_status & (BIT(1) | BIT(2)); - rc = pmi8998_masked_write(chip->regmap, REG_MEM + 0x71, BIT(0), + rc = qcom_fg_masked_write(chip->regmap, REG_MEM + 0x71, BIT(0), error_present ? BIT(0) : 0); if (rc < 0) { pr_err("failed to write dma_ctl, rc=%d\n", rc); @@ -651,39 +1058,90 @@ static int pmi8998_fg_probe(struct platform_device *pdev) platform_set_drvdata(pdev, chip); - irq = of_irq_get_byname(pdev->dev.of_node, "usb-plugin"); - if (irq < 0) { - dev_err(&pdev->dev, "Couldn't get irq usb-plugin byname\n"); - return irq; + /* Initialize IRQs */ + switch(chip->subtype) + { + case PMI8994_SUBTYPE: + case PMI8996_SUBTYPE: + irq = of_irq_get_byname(pdev->dev.of_node, "mem-avail"); + if (irq < 0) { + dev_err(&pdev->dev, "Couldn't get irq mem-avail byname\n"); + return irq; + } + + rc = devm_request_threaded_irq(chip->dev, irq, NULL, + qcom_fg_handle_mem_avail, + IRQF_ONESHOT, "mem-avail", chip); + if (rc < 0) { + pr_err("Couldn't request irq %d\n", irq); + return rc; + } + + init_completion(&chip->sram_access_granted); + break; + + case PM8998_SUBTYPE: + case PMI8998_SUBTYPE: + irq = of_irq_get_byname(pdev->dev.of_node, "usb-plugin"); + if (irq < 0) { + dev_err(&pdev->dev, "Couldn't get irq usb-plugin byname\n"); + return irq; + } + + rc = devm_request_threaded_irq(chip->dev, irq, NULL, + qcom_fg_handle_usb_plugin, + IRQF_ONESHOT, "usb-plugin", chip); + if (rc < 0) { + pr_err("Couldn't request irq %d\n", irq); + return rc; + } + + break; } - rc = devm_request_threaded_irq(chip->dev, irq, NULL, - pmi8998_handle_usb_plugin, - IRQF_ONESHOT, "usb-plugin", chip); - if (rc < 0) { - pr_err("Couldn't request irq %d\n", irq); + // Set default temperature thresholds + rc = chip->ops->set_temp_threshold(chip, + POWER_SUPPLY_PROP_TEMP_MIN, + BATT_TEMP_JEITA_COLD); + rc = chip->ops->set_temp_threshold(chip, + POWER_SUPPLY_PROP_TEMP_MAX, + BATT_TEMP_JEITA_WARM); + rc = chip->ops->set_temp_threshold(chip, + POWER_SUPPLY_PROP_TEMP_ALERT_MIN, + BATT_TEMP_JEITA_COOL); + rc = chip->ops->set_temp_threshold(chip, + POWER_SUPPLY_PROP_TEMP_ALERT_MAX, + BATT_TEMP_JEITA_HOT); + if(rc == -ENOTSUPP) { + dev_warn(chip->dev, + "Setting temperature thresholds not supported"); + } + else if(rc < 0) { + dev_err(chip->dev, + "Setting temperature thresholds failed: %d\n", rc); return rc; } return 0; } -static int pmi8998_fg_remove(struct platform_device *pdev) +static int qcom_fg_remove(struct platform_device *pdev) { return 0; } static const struct of_device_id fg_match_id_table[] = { - { .compatible = "qcom,pmi8998-fg" }, + { .compatible = "qcom,pmi8994-fg", .data = &ops_fg }, + { .compatible = "qcom,pmi8998-fg", .data = &ops_fg_gen3 }, { /* sentinal */ } }; MODULE_DEVICE_TABLE(of, fg_match_id_table); static struct platform_driver qcom_fg_driver = { - .probe = pmi8998_fg_probe, - .remove = pmi8998_fg_remove, + .probe = qcom_fg_probe, + .remove = qcom_fg_remove, .driver = { - .name = "pmi8998-fg", + .name = "qcom-fg", .of_match_table = fg_match_id_table, }, }; @@ -692,5 +1150,6 @@ module_platform_driver(qcom_fg_driver); MODULE_AUTHOR("Caleb Connolly "); MODULE_AUTHOR("Joel Selvaraj "); -MODULE_DESCRIPTION("Qualcomm PMI8998 Fuel Guage Driver"); +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Qualcomm PMIC Fuel Gauge Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/supply/pmi8998_fg.h b/drivers/power/supply/qcom_fg.h similarity index 60% rename from drivers/power/supply/pmi8998_fg.h rename to drivers/power/supply/qcom_fg.h index b44f88bc9395..2bc6df2fdd9d 100644 --- a/drivers/power/supply/pmi8998_fg.h +++ b/drivers/power/supply/qcom_fg.h @@ -3,19 +3,18 @@ /**** Registers *****/ -// pmi8998 v2 specific -#define BATT_INFO_CHARGE_MAX_DESIGN 0x4a +#define PMIC_SUBTYPE 0x105 + +#define PMI8994_SUBTYPE 0x0a +#define PMI8996_SUBTYPE 0x13 +#define PM8998_SUBTYPE 0x14 +#define PMI8998_SUBTYPE 0x15 + + +/* SRAM */ +#define MEM_INTF_STS 0x10 #define MEM_INTF_CFG 0x50 -#define MEM_INTF_ADDR_LSB 0x61 -#define MEM_INTF_RD_DATA0 0x67 -#define MEM_INTF_WR_DATA0 0x63 - -#define PMIC_SUBTYPE 0x105 - -#define PM8998_SUBTYPE 0x14 -#define PMI8998_SUBTYPE 0x15 - -// pm8950 / pm89988 common +#define MEM_INTF_CTL 0x51 #define MEM_INTF_IMA_CFG 0x52 #define MEM_INTF_IMA_OPR_STS 0x54 #define MEM_INTF_IMA_EXP_STS 0x55 @@ -23,7 +22,18 @@ #define MEM_INTF_BEAT_COUNT 0x57 #define MEM_INTF_IMA_ERR_STS 0x5f #define MEM_INTF_IMA_BYTE_EN 0x60 +#define MEM_INTF_ADDR_LSB 0x61 +#define MEM_INTF_RD_DATA0 0x67 +#define MEM_INTF_WR_DATA0 0x63 +#define MEM_INTF_AVAIL BIT(0) +#define MEM_INTF_CTL_BURST BIT(7) +#define MEM_INTF_CTL_WR_EN BIT(6) +#define RIF_MEM_ACCESS_REQ BIT(7) + + +/* Battery info */ +#define BATT_INFO_CHARGE_MAX_DESIGN 0x4a #define BATT_INFO_THERM_C1 0x5c #define BATT_INFO_VBATT_LSB 0xa0 #define BATT_INFO_VBATT_MSB 0xa1 @@ -36,45 +46,58 @@ #define BATT_TEMP_LSB_MASK GENMASK(7, 0) #define BATT_TEMP_MSB_MASK GENMASK(2, 0) -#define REG_BASE 0x4000 -#define REG_BATT 0x4100 -#define REG_MEM 0x4400 + +/* Base addresses */ +#define REG_BASE 0x4000 +#define REG_BATT 0x4100 +#define REG_MEM 0x4400 + /* Interrupt offsets */ #define INT_RT_STS 0x10 #define INT_EN_CLR 0x16 -// Param addresses -#define PARAM_ADDR_BATT_TEMP 0x50 -#define PARAM_ADDR_BATT_VOLTAGE 0xa0 -#define PARAM_ADDR_BATT_CURRENT 0xa2 + +/* Param addresses */ +#define PARAM_ADDR_BATT_TEMP 0x50 +#define PARAM_ADDR_BATT_VOLTAGE 0xa0 +#define PARAM_ADDR_BATT_CURRENT 0xa2 + + +#define MISC_BASE 0x1600 +#define USBIN_BASE 0x1300 + #define BATT_INFO_JEITA_COLD(chip) (REG_BATT + 0x62) #define BATT_INFO_JEITA_COOL(chip) (REG_BATT + 0x63) #define BATT_INFO_JEITA_WARM(chip) (REG_BATT + 0x64) #define BATT_INFO_JEITA_HOT(chip) (REG_BATT + 0x65) -#define MISC_BASE 0x1600 -#define USBIN_BASE 0x1300 +#define BATT_TEMP_JEITA_COLD 100 +#define BATT_TEMP_JEITA_COOL 50 +#define BATT_TEMP_JEITA_WARM 400 +#define BATT_TEMP_JEITA_HOT 450 #define BATTERY_CHARGER_STATUS_REG(chip) (chip->chg_base + 0x06) -#define BATTERY_HEALTH_STATUS_REG(chip) (chip->chg_base + 0x07) +#define BATTERY_HEALTH_STATUS_REG(chip) (chip->chg_base + 0x07) #define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0) #define POWER_PATH_STATUS_REG (MISC_BASE + 0x0B) +#define MEM_IF_TIMEOUT_MS 5000 + enum wa_flags { PMI8998_V1_REV_WA, PMI8998_V2_REV_WA, }; -enum pmi8998_rev_offsets { +enum pmic_rev_offsets { DIG_MINOR = 0x0, DIG_MAJOR = 0x1, ANA_MINOR = 0x2, ANA_MAJOR = 0x3, }; -enum pmi8998_rev { +enum pmic_rev { DIG_REV_1 = 0x1, DIG_REV_2 = 0x2, DIG_REV_3 = 0x3, @@ -112,18 +135,35 @@ static enum power_supply_property fg_properties[] = { POWER_SUPPLY_PROP_TEMP_ALERT_MAX, }; -struct pmi8998_fg_chip { +struct qcom_fg_chip; + +struct qcom_fg_ops { + int (*get_capacity)(struct qcom_fg_chip *chip, int *); + int (*get_temperature)(struct qcom_fg_chip *chip, int *); + int (*get_current)(struct qcom_fg_chip *chip, int *); + int (*get_voltage)(struct qcom_fg_chip *chip, int *); + int (*get_batt_status)(struct qcom_fg_chip *chip, int *); + int (*get_health_status)(struct qcom_fg_chip *chip, int *); + int (*get_temp_threshold)(struct qcom_fg_chip *chip, + enum power_supply_property psp, int *); + int (*set_temp_threshold)(struct qcom_fg_chip *chip, + enum power_supply_property psp, int); +}; + +struct qcom_fg_chip { struct device *dev; unsigned int base; unsigned int chg_base; struct regmap *regmap; struct mutex lock; unsigned int subtype; + const struct qcom_fg_ops *ops; struct power_supply *bms_psy; u8 revision[4]; bool ima_supported; + struct completion sram_access_granted; int batt_cap_uah; int batt_max_voltage_uv; From ec6f66ad8944f459ba00790f8910cf19127a0039 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 27 Jul 2021 13:33:19 +0300 Subject: [PATCH 134/174] [ANNOTATION] Import WIP "Qualcomm SPMI Fuel Gauge" driver Drop pmi8994 DTS changes though. https://gitlab.com/sdm845-mainline/linux/-/commits/driver/pmi8998_fg/ From 6c3db94d2e8773ad0a76ac0f42f48e40d6a43a5b Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Wed, 7 Oct 2020 23:06:21 +0300 Subject: [PATCH 135/174] [HACK] scripts: Stop appending "+" to localversion This always gets added and doesn't look nice in the version string, so it's purely for aesthetic reasons :p --- scripts/setlocalversion | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/setlocalversion b/scripts/setlocalversion index af4754a35e66..a42f4008a9dc 100755 --- a/scripts/setlocalversion +++ b/scripts/setlocalversion @@ -139,7 +139,7 @@ elif [ "${LOCALVERSION+set}" != "set" ]; then # If the variable LOCALVERSION is set (including being set # to an empty string), we don't want to append a plus sign. scm=$(scm_version --short) - res="$res${scm:++}" + #res="$res${scm:++}" fi echo "$res" From 927111b0f5bfe4a69b7260af7759fc078416f0c8 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 12 Jan 2021 19:50:09 +0200 Subject: [PATCH 136/174] [HACK] ath10k: Fake MSA ready event after event server arrival This finally allowed me to get past the 2 ath10k_info()'s in qmi.c! However, this doesn't fix everything; it seems you *have* to run diag-router from https://github.com/andersson/diag to calm the firmware down and stop constantly crashing; need to look into a way to get Wi-Fi working later without needing this debug crap to be running. --- drivers/net/wireless/ath/ath10k/qmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c index 80fcb917fe4e..46b8a13ce4d3 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c @@ -1004,6 +1004,8 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work) switch (event->type) { case ATH10K_QMI_EVENT_SERVER_ARRIVE: ath10k_qmi_event_server_arrive(qmi); + // HACK: Fake MSA being ready + ath10k_qmi_event_msa_ready(qmi); break; case ATH10K_QMI_EVENT_SERVER_EXIT: ath10k_qmi_event_server_exit(qmi); From 34121e605596aaefa1686e370fc2ff2790013aec Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 23 Apr 2021 03:58:38 +0300 Subject: [PATCH 137/174] dt-bindings: Document bindings for all MSM8998 devices --- Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 04ff0b55bb85..9c10ab8dc07c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -41,6 +41,7 @@ description: | sa8155p sc7180 sc7280 + msm8998 sdm630 sdm660 sdm845 @@ -210,6 +211,16 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - asus,novago-tp370ql + - hp,envy-x2 + - lenovo,miix-630 + - oneplus,cheeseburger + - oneplus,dumpling + - qcom,msm8998-mtp + - const: qcom,msm8998 + - items: - enum: - xiaomi,lavender From 8f429d89780852a1595dcc2eb771baf24cbb05c6 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 27 Apr 2021 20:24:20 +0300 Subject: [PATCH 138/174] drm/msm: Mention DSI 10nm PHY support for MSM8998 --- drivers/gpu/drm/msm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 1eae5a9645f4..2f17400ac60b 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -112,7 +112,7 @@ config DRM_MSM_DSI_14NM_PHY Choose this option if DSI PHY on 8996 is used on the platform. config DRM_MSM_DSI_10NM_PHY - bool "Enable DSI 10nm PHY driver in MSM DRM (used by SDM845)" + bool "Enable DSI 10nm PHY driver in MSM DRM (used by MSM8998/SDM845)" depends on DRM_MSM_DSI default y help From 88d6e9641918273fc870a21cd7555cbc88a3dc53 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sun, 25 Apr 2021 17:33:06 +0300 Subject: [PATCH 139/174] power: supply: qcom_fg: Report online property --- drivers/power/supply/qcom_fg.c | 4 ++++ drivers/power/supply/qcom_fg.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/power/supply/qcom_fg.c b/drivers/power/supply/qcom_fg.c index dc41f6072828..7e3bfad0de0c 100644 --- a/drivers/power/supply/qcom_fg.c +++ b/drivers/power/supply/qcom_fg.c @@ -594,6 +594,7 @@ int qcom_fg_get_prop_batt_status(struct qcom_fg_chip *chip, int *val){ } dev_dbg(chip->dev, "USB ONLINE val : %d\n", usb_online_val); usb_online = (bool)usb_online_val; + chip->online = usb_online; if (!usb_online) { *val = POWER_SUPPLY_STATUS_DISCHARGING; @@ -828,6 +829,9 @@ static int fg_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_STATUS: error = chip->ops->get_batt_status(chip, &val->intval); break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = chip->online; + break; case POWER_SUPPLY_PROP_HEALTH: error = chip->ops->get_health_status(chip, &val->intval); break; diff --git a/drivers/power/supply/qcom_fg.h b/drivers/power/supply/qcom_fg.h index 2bc6df2fdd9d..2617d0203e57 100644 --- a/drivers/power/supply/qcom_fg.h +++ b/drivers/power/supply/qcom_fg.h @@ -125,6 +125,7 @@ static enum power_supply_property fg_properties[] = { POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_CHARGE_FULL, POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, @@ -171,4 +172,5 @@ struct qcom_fg_chip { int health; int status; + bool online; }; From bdfeaa075cbfc264fc19d3753773c482288cae1b Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 27 Jul 2021 14:04:12 +0300 Subject: [PATCH 140/174] arm64: dts: qcom: msm8998: add IPA information Add support for the MSM8998 SoC, which includes IPA version 3.1. --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 6d59a5c6f403..ecdc85e05c89 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -906,6 +906,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; smp2p-slpi { @@ -1741,6 +1752,50 @@ }; }; + ipa: ipa@1e40000 { + compatible = "qcom,msm8998-ipa"; + + iommus = <&anoc2_smmu 0x18e0 0x0>, + <&anoc2_smmu 0x18e2 0x0>; + reg = <0x1e40000 0x7000>, + <0x1e47000 0x2000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 333 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core"; + +/* Elder's proposed interconnects: + <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0> +*/ + interconnects = <&a2noc MASTER_IPA &bimc SLAVE_EBI>, + <&a2noc MASTER_IPA &snoc SLAVE_IMEM>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_IPA>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x01f40000 0x40000>; From 193be10420a3c45db414c8bc2c4551ed736badf3 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 28 Jan 2022 18:39:57 +0200 Subject: [PATCH 141/174] drm/msm: Add A540 device support --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fb261930ad1c..9daa0980a1a0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -356,6 +356,11 @@ MODULE_FIRMWARE("qcom/a530_zap.mdt"); MODULE_FIRMWARE("qcom/a530_zap.b00"); MODULE_FIRMWARE("qcom/a530_zap.b01"); MODULE_FIRMWARE("qcom/a530_zap.b02"); +MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a540_zap.mdt"); +MODULE_FIRMWARE("qcom/a540_zap.b00"); +MODULE_FIRMWARE("qcom/a540_zap.b01"); +MODULE_FIRMWARE("qcom/a540_zap.b02"); MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); MODULE_FIRMWARE("qcom/a630_zap.mbn"); From 51418997adb3025d2c4d160d52e347eb9ed7c27b Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 21 May 2021 04:31:36 +0300 Subject: [PATCH 142/174] Input: synaptics-rmi4 - add support for F1A RMI4 F1A supports the simple capacitive buttons function, it's used for example on embedded devices such as smartphones for capacitive Android back and recents buttons. --- drivers/input/rmi4/Kconfig | 8 ++ drivers/input/rmi4/Makefile | 1 + drivers/input/rmi4/rmi_bus.c | 3 + drivers/input/rmi4/rmi_driver.h | 1 + drivers/input/rmi4/rmi_f1a.c | 180 ++++++++++++++++++++++++++++++++ 5 files changed, 193 insertions(+) create mode 100644 drivers/input/rmi4/rmi_f1a.c diff --git a/drivers/input/rmi4/Kconfig b/drivers/input/rmi4/Kconfig index 16119f760d11..cb98262e78a5 100644 --- a/drivers/input/rmi4/Kconfig +++ b/drivers/input/rmi4/Kconfig @@ -82,6 +82,14 @@ config RMI4_F12 touchpads. For sensors that support relative pointing, F12 also provides mouse input. +config RMI4_F1A + bool "RMI4 Function 1A (Simple capacitive buttons)" + depends on OF + help + Say Y here if you want to add support for RMI4 function 1A. + + Function 1A provides GPIO capacitive button support for RMI4 devices. + config RMI4_F30 bool "RMI4 Function 30 (GPIO LED)" help diff --git a/drivers/input/rmi4/Makefile b/drivers/input/rmi4/Makefile index 02f14c846861..70f942196aa2 100644 --- a/drivers/input/rmi4/Makefile +++ b/drivers/input/rmi4/Makefile @@ -8,6 +8,7 @@ rmi_core-$(CONFIG_RMI4_2D_SENSOR) += rmi_2d_sensor.o rmi_core-$(CONFIG_RMI4_F03) += rmi_f03.o rmi_core-$(CONFIG_RMI4_F11) += rmi_f11.o rmi_core-$(CONFIG_RMI4_F12) += rmi_f12.o +rmi_core-$(CONFIG_RMI4_F1A) += rmi_f1a.o rmi_core-$(CONFIG_RMI4_F30) += rmi_f30.o rmi_core-$(CONFIG_RMI4_F34) += rmi_f34.o rmi_f34v7.o rmi_core-$(CONFIG_RMI4_F3A) += rmi_f3a.o diff --git a/drivers/input/rmi4/rmi_bus.c b/drivers/input/rmi4/rmi_bus.c index 50a0134b6901..fc39ba462ab0 100644 --- a/drivers/input/rmi4/rmi_bus.c +++ b/drivers/input/rmi4/rmi_bus.c @@ -360,6 +360,9 @@ static struct rmi_function_handler *fn_handlers[] = { #ifdef CONFIG_RMI4_F12 &rmi_f12_handler, #endif +#ifdef CONFIG_RMI4_F1A + &rmi_f1a_handler, +#endif #ifdef CONFIG_RMI4_F30 &rmi_f30_handler, #endif diff --git a/drivers/input/rmi4/rmi_driver.h b/drivers/input/rmi4/rmi_driver.h index 1c6c6086c0e5..a05b8f9d7a46 100644 --- a/drivers/input/rmi4/rmi_driver.h +++ b/drivers/input/rmi4/rmi_driver.h @@ -133,6 +133,7 @@ extern struct rmi_function_handler rmi_f01_handler; extern struct rmi_function_handler rmi_f03_handler; extern struct rmi_function_handler rmi_f11_handler; extern struct rmi_function_handler rmi_f12_handler; +extern struct rmi_function_handler rmi_f1a_handler; extern struct rmi_function_handler rmi_f30_handler; extern struct rmi_function_handler rmi_f34_handler; extern struct rmi_function_handler rmi_f3a_handler; diff --git a/drivers/input/rmi4/rmi_f1a.c b/drivers/input/rmi4/rmi_f1a.c new file mode 100644 index 000000000000..11834778112f --- /dev/null +++ b/drivers/input/rmi4/rmi_f1a.c @@ -0,0 +1,180 @@ +// FIXME: Too much stuff is hardcoded in currently! +#include +#include +#include +#include "rmi_driver.h" + +/* Query 1 */ +//#define F1A_BUTTONS_COUNT 0b00011111 /* BIT(1) */ + +#define MAX_NAME_LEN 256 +#define F1A_MAX_BUTTONS 8 + +struct f1a_data { + struct rmi_function *fn; + + unsigned char button_count; + u32 button_map[F1A_MAX_BUTTONS]; + struct input_dev *input; + char input_name[MAX_NAME_LEN]; + char input_phys[MAX_NAME_LEN]; + u8 button_data_buffer; +}; + +static int rmi_f1a_initialize(struct f1a_data *f1a) +{ + struct rmi_function *fn = f1a->fn; + struct device *dev = &fn->dev; + //u8 query[2]; + int error; + + /*error = rmi_read_block(fn->rmi_dev, fn->fd.query_base_addr, query, 2); + if (error) { + dev_err(dev, "Failed to read query register (%d).\n", error); + return error; + } + printk("%s: query0: 0x%x, query1: 0x%x\n", __func__, query[0], query[1]);*/ + + error = of_property_read_variable_u32_array(dev_of_node(dev), + "syna,codes", f1a->button_map, 1, F1A_MAX_BUTTONS); + if (error < 0) { + dev_err(dev, "Failed to parse syna,codes from OF device tree (%d).\n", error); + return error; + } + // FIXME: button_count = query[1] & F1A_BUTTONS_COUNT; + f1a->button_count = 0; + for (f1a->button_count = 0; f1a->button_count < F1A_MAX_BUTTONS; f1a->button_count++) + if (f1a->button_map[f1a->button_count] == 0) + break; + rmi_dbg(RMI_DEBUG_FN, dev, "%s: %d button codes defined\n", __func__, f1a->button_count); + + return 0; +} + +static int rmi_f1a_register_device(struct f1a_data *f1a) +{ + struct rmi_function *fn = f1a->fn; + struct device *dev = &fn->dev; + struct rmi_device *rmi_dev = fn->rmi_dev; + struct input_dev *input_dev; + int i, rc; + + input_dev = input_allocate_device(); + if (!input_dev) { + dev_err(dev, "Failed to allocate input device.\n"); + return -ENOMEM; + } + + f1a->input = input_dev; + snprintf(f1a->input_name, MAX_NAME_LEN, "%s.fn%02x", + dev_name(&rmi_dev->dev), fn->fd.function_number); + input_dev->name = f1a->input_name; + snprintf(f1a->input_phys, MAX_NAME_LEN, "%s/input0", input_dev->name); + input_dev->phys = f1a->input_phys; + input_dev->dev.parent = &rmi_dev->dev; + input_set_drvdata(input_dev, f1a); + + /* set up any input events */ + set_bit(EV_SYN, input_dev->evbit); + set_bit(EV_KEY, input_dev->evbit); + + /* manage button map using input subsystem */ + input_dev->keycode = f1a->button_map; + input_dev->keycodesize = sizeof(f1a->button_map); /* f1a->button_count */ + input_dev->keycodemax = f1a->button_count; + + /* set bits for each button */ + for (i = 0; i < f1a->button_count; i++) { + set_bit(f1a->button_map[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, f1a->button_map[i]); + } + + rc = input_register_device(input_dev); + if (rc < 0) { + dev_err(dev, "Failed to register input device.\n"); + goto error_free_device; + } + + return 0; + +error_free_device: + input_free_device(input_dev); + return rc; +} + +static int rmi_f1a_probe(struct rmi_function *fn) +{ + struct device *dev = &fn->dev; + struct f1a_data *f1a; + int error; + + rmi_dbg(RMI_DEBUG_FN, dev, "%s\n", __func__); + + f1a = devm_kzalloc(dev, sizeof(struct f1a_data), GFP_KERNEL); + if (!f1a) + return -ENOMEM; + + f1a->fn = fn; + + error = rmi_f1a_initialize(f1a); + if (error < 0) + return error; + + error = rmi_f1a_register_device(f1a); + if (error < 0) + return error; + + dev_set_drvdata(dev, f1a); + return 0; +} + +static int rmi_f1a_config(struct rmi_function *fn) +{ + fn->rmi_dev->driver->set_irq_bits(fn->rmi_dev, fn->irq_mask); + return 0; +} + +static irqreturn_t rmi_f1a_attention(int irq, void *ctx) +{ + struct rmi_function *fn = ctx; + struct device *dev = &fn->dev; + struct rmi_device *rmi_dev = fn->rmi_dev; + struct f1a_data *f1a = dev_get_drvdata(dev); + int error, button; + + // TODO: use rmi_read_block() to accomodate up to 8 buttons? + error = rmi_read(rmi_dev, fn->fd.data_base_addr, &(f1a->button_data_buffer)); + if (error < 0) { + dev_err(dev, "Failed to read button data registers (%d).\n", error); + return error; + } + /*rmi_dbg(RMI_DEBUG_FN, dev, "%s: button_data=0x%x\n", __func__, f1a->button_data_buffer);*/ + + /* generate events for buttons that change state */ + // TODO: Implement button_data_buffer as array + button_reg = button / 8 + for (button = 0; button < f1a->button_count; button++) { + int button_shift; + bool button_status; + /* bit shift to get button's status */ + button_shift = button % 8; + button_status = ((f1a->button_data_buffer >> button_shift) & 0x01) != 0; + + rmi_dbg(RMI_DEBUG_FN, dev, "button %d (code %d) -> %d\n", + button, f1a->button_map[button], button_status); + /* generate an event here */ + input_report_key(f1a->input, f1a->button_map[button], button_status); + } + input_sync(f1a->input); /* sync after groups of events */ + + return IRQ_HANDLED; +} + +struct rmi_function_handler rmi_f1a_handler = { + .driver = { + .name = "rmi4_f1a", + }, + .func = 0x1a, + .probe = rmi_f1a_probe, + .config = rmi_f1a_config, + .attention = rmi_f1a_attention, +}; From 1628ae181fc9c081504c48537867158bc6eae563 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sun, 25 Jul 2021 04:39:01 +0300 Subject: [PATCH 143/174] ASoC: codecs: tfa989x: Add support for tfa9890 This speaker amp model appears to be rather popular on phones and is used for example by the OnePlus 5/5T. --- sound/soc/codecs/tfa989x.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/sound/soc/codecs/tfa989x.c b/sound/soc/codecs/tfa989x.c index dc86852752c5..2a6cc9fffadd 100644 --- a/sound/soc/codecs/tfa989x.c +++ b/sound/soc/codecs/tfa989x.c @@ -40,12 +40,15 @@ #define TFA989X_I2S_SEL_REG 0x0a #define TFA989X_I2S_SEL_REG_SPKR_MSK GENMASK(10, 9) /* speaker impedance */ #define TFA989X_I2S_SEL_REG_DCFG_MSK GENMASK(14, 11) /* DCDC compensation */ +#define TFA989X_INTERRUPT_OUT_REG1 0x40 #define TFA989X_PWM_CONTROL 0x41 #define TFA989X_CURRENTSENSE1 0x46 #define TFA989X_CURRENTSENSE2 0x47 #define TFA989X_CURRENTSENSE3 0x48 #define TFA989X_CURRENTSENSE4 0x49 +#define TFA989X_UNKREG1 0x59 /* TODO: What's this? */ +#define TFA9890_REVISION 0x80 #define TFA9895_REVISION 0x12 #define TFA9897_REVISION 0x97 @@ -188,6 +191,30 @@ static struct snd_soc_dai_driver tfa989x_dai = { .ops = &tfa989x_dai_ops, }; +static int tfa9890_init(struct regmap *regmap) +{ + int ret; + unsigned int val; + + /* some other registers must be set for optimal amplifier behaviour */ + ret = regmap_write(regmap, TFA989X_INTERRUPT_OUT_REG1, 0x5a6b); + if (ret) + return ret; + + regmap_read(regmap, TFA989X_UNKREG1, &val); + val |= 0x3; + regmap_write(regmap, TFA989X_UNKREG1, val); + + regmap_write(regmap, TFA989X_INTERRUPT_OUT_REG1, 0x0000); + + return regmap_write(regmap, TFA989X_CURRENTSENSE2, 0x7be1); +} + +static const struct tfa989x_rev tfa9890_rev = { + .rev = TFA9890_REVISION, + .init = tfa9890_init, +}; + static const struct reg_sequence tfa9895_reg_init[] = { /* some other registers must be set for optimal amplifier behaviour */ { TFA989X_BAT_PROT, 0x13ab }, @@ -376,6 +403,7 @@ static int tfa989x_i2c_probe(struct i2c_client *i2c) } static const struct of_device_id tfa989x_of_match[] = { + { .compatible = "nxp,tfa9890", .data = &tfa9890_rev }, { .compatible = "nxp,tfa9895", .data = &tfa9895_rev }, { .compatible = "nxp,tfa9897", .data = &tfa9897_rev }, { } From af1277a4886e1b0f8ce805ea28f798527831cb85 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sat, 20 Nov 2021 22:14:36 +0200 Subject: [PATCH 144/174] module: demote invalid ELF header magic error message to pr_debug This happens anytime busybox modprobe loads a compressed module and looks especially ugly on postmarketOS for example (or basically any initramfs); this error is rather pointless since the module is loaded anyway afterwards. Upstream (busybox) has no plans to do anything about this error getting spammed: https://www.mail-archive.com/busybox@busybox.net/msg27078.html --- kernel/module.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/module.c b/kernel/module.c index 46a5c2ed1928..8644c992af29 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -2977,7 +2977,7 @@ static int elf_validity_check(struct load_info *info) } if (memcmp(info->hdr->e_ident, ELFMAG, SELFMAG) != 0) { - pr_err("Invalid ELF header magic: != %s\n", ELFMAG); + pr_debug("Invalid ELF header magic: != %s\n", ELFMAG); goto no_exec; } if (info->hdr->e_type != ET_REL) { From b800af63ddde4768a5f90b7f322a8befc9dfab53 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 27 Jul 2021 14:13:34 +0300 Subject: [PATCH 145/174] [ANNOTATION] Apply miscellaneous hacks and patches From 4c36b04925e17f422441da234dbaf7d8767325cb Mon Sep 17 00:00:00 2001 From: Danct12 Date: Wed, 28 Apr 2021 02:23:45 +0700 Subject: [PATCH 146/174] arm64: dts: msm8998-fxtec-pro1: Configure PMI8998 fuel gauge This will account for battery statistics reporting on the Fxtec Pro1 (QX1000) --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 737bcabf1a21..277d46124588 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -461,6 +461,14 @@ regulator-max-microvolt = <1100000>; }; +&pmi8998_fg { + status = "okay"; + + qcom,max-voltage-uv = <4400000>; + qcom,min-voltage-uv = <3700000>; + qcom,battery-capacity-ua = <3150000>; +}; + &pm8998_gpio { unknown_pin_a: unk-active { pins = "gpio5"; From 9cb6c347195e508f945565d823fd9bd39c959492 Mon Sep 17 00:00:00 2001 From: Danct12 Date: Thu, 29 Apr 2021 00:21:49 +0700 Subject: [PATCH 147/174] arm64: dts: msm8998-fxtec-pro1: Enable PMI8998 haptics --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 277d46124588..49fba9598658 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -455,6 +455,12 @@ status = "ok"; }; +&pmi8998_haptics { + status = "okay"; + + qcom,wave-play-rate-us = <5000>; +}; + /* HACK! Push GPU voltage high until GPU CPR is hooked up */ &pm8005_s1 { regulator-min-microvolt = <988000>; From 28a64dcdc102f319040e18289b2090d79a699ab4 Mon Sep 17 00:00:00 2001 From: Danct12 Date: Sun, 2 May 2021 06:51:56 +0700 Subject: [PATCH 148/174] arm64: dts: msm8998-fxtec-pro1: Add remoteproc configuration --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 49fba9598658..4909cba58cff 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -285,6 +285,7 @@ zap-shader { memory-region = <&zap_shader_region>; + firmware-name = "qcom/a540_zap.mbn"; }; }; @@ -447,6 +448,22 @@ status = "ok"; }; +&remoteproc_adsp { + status = "okay"; + + firmware-name = "qcom/msm8998/fxtec/adsp.mbn"; +}; + +&remoteproc_mss { + firmware-name = "qcom/msm8998/fxtec/mba.mbn", "qcom/msm8998/fxtec/modem.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + + firmware-name = "qcom/msm8998/fxtec/slpi_v2.mbn"; +}; + &mmcc { status = "ok"; }; From 9f0b72f7d8199584d15b2cc5cd524d0e335f1231 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Tue, 27 Jul 2021 15:13:42 +0300 Subject: [PATCH 149/174] [ANNOTATION] Apply some F(x)tec Pro1 patches From 18b60e1e080a986a853009956edef37e44eb122f Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sun, 21 Jun 2020 21:52:02 +0300 Subject: [PATCH 150/174] drm/panel: Add panel driver for Samsung S6E3FA5 The S6E3FA5 is 5.5" 1080x1920 MIPI DSI command mode AMOLED LCD display found on OnePlus 5 (2017) smartphones. The panel needs to be enabled from a device tree using the "samsung,s6e3fa5" compatible. This driver was generated using the following & includes some minor cleanup (such as s/to_s6e3fa5/to_s6e3fa5_panel/g): $ python3 lmdpdg.py cheeseburger.dtb -r vddio Signed-off-by: Jami Kettunen --- drivers/gpu/drm/panel/Kconfig | 15 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-samsung-s6e3fa5.c | 340 ++++++++++++++++++ 3 files changed, 356 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6e3fa5.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 9989a316fe88..a8157b2bdd6d 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -449,6 +449,21 @@ config DRM_PANEL_SAMSUNG_S6D27A1 This panel can be found in Samsung Galaxy Ace 2 GT-I8160 mobile phone. +config DRM_PANEL_SAMSUNG_S6E3FA5 + tristate "Samsung S6E3FA5 DSI command mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y here if you want to enable support for Samsung S6E3FA5 AMOLED + command mode panel as found in OnePlus 5 (2017) devices. The panel has a + FHD (1080x1920) resolution and uses 24 bit RGB per pixel. It provides a + MIPI DSI interface to the host and has a built-in LED backlight. + + To compile this driver as a module, choose M here: the module + will be called panel-samsung-s6e3fa5. + config DRM_PANEL_SAMSUNG_S6E3HA2 tristate "Samsung S6E3HA2 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d99fbbce49d1..5ef4bad6f59b 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FA5) += panel-samsung-s6e3fa5.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3fa5.c b/drivers/gpu/drm/panel/panel-samsung-s6e3fa5.c new file mode 100644 index 000000000000..daa2929d9314 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-s6e3fa5.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2021 Jami Kettunen + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include