Some qcom platforms make some GPIOs or pins unavailable for use
by non-secure operating systems, and thus reading or writing the
registers for those pins will cause access control issues and
reset the device. With a DT/ACPI property to describe the set of
pins that are available for use, parse the available pins and set
the irq valid bits for gpiolib to know what to consider 'valid'.
This should avoid any issues with gpiolib. Furthermore, implement
the pinmux_ops::request function so that pinmux can also make
sure to not use pins that are unavailable.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PMIC often require the I2C bus, and the PMIC regulators might be
necessary to power on eMMC/SD-card or other supplies required
for successful boot. Make sure I2C driver for i.MX devices is
built-in.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Some qcom platforms make some GPIOs or pins unavailable for use by
non-secure operating systems, and thus reading or writing the registers
for those pins will cause access control issues. Add support for a DT
property to describe the set of GPIOs that are available for use so that
higher level OSes are able to know what pins to avoid reading/writing.
Non-DT platforms can add support by directly updating the
chip->valid_mask.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We don't need to clear out these bits when we set them immediately
after. Use kmalloc_array() to skip clearing the bits.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We're going to use similar code to allocate and set all the bits in a
mask for valid gpios to use. Extract the code from the irqchip version
so it can be reused.
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some qcom platforms make some GPIOs or pins unavailable for use
by non-secure operating systems, and thus reading or writing the
registers for those pins will cause access control issues.
Introduce a DT property to describe the set of GPIOs that are
available for use so that higher level OSes are able to know what
pins to avoid reading/writing.
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This series enables more devices working on droid4 to make it easier
for people and distros to use out of the box.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlqz3MERHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNBZhAA5E4KkoNvZSlKv2oLoUQ0CuOA/F9WIKJ3
bRcCNuLZSRSrrI7V739B69cR7e2HbSz4u4REYMdNwWI79IJBdlStqoy4UX2PMV0N
jshHWR7GqOBWn3JLhCWXKmeo3ezq9LQiiIR7YfawD1evy+2CzgvjuEmJOk+FTGEF
+K6A+fI/J5aTt/UcSXBgmhgjWjEoJp0NeDK1aSKB1GLid7owj5xjHqqbbkL2yin4
Sn3Vs5diQbgAoypTxOlpObMSjv293gmlS/EmB2CPKdav0M178UxMd6O9zfbQV4Bc
2iqxcIGUt558V9xAyGhv46Z6u4BlfzxaUVf4QksBM++Up9vwFYMkArUm0PUW30Wg
x0VZkdqZ5Tc1IFjZ9cgrfOGLeyWvqqd5LX5enpUJVlUbjJv+pWzU9/mhGZxnCaxv
Q8IUGgYRKwSsz2s95thACPmVa3vY9hOxcJe2KrlMzB8tDekerMFVL70W0WO2gnuH
xYptRrwpioRbAny74vIssWnl4UaaJAKkrVRMeSbLyZ+J88JReHMuWyHPEfIVrIGw
D4jWWWGHKd4gQ/h/dCmj2TU0Q2IHb8sUyx08GCngpsQT+jRHGW2ldDcsle9PYvwy
aiXcQwWy+9J7hJvk1q/gWMJtS04EanvfIP7OsPMNzrxOhSD25zKZFh4voYQVU2TQ
q6hx/TW16MI=
=sOYq
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.17/defconfig-pt2-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "Second set of defconfig changes for omap variants for v4.17" from Tony Lindgren:
This series enables more devices working on droid4 to make it easier
for people and distros to use out of the box.
* tag 'omap-for-v4.17/defconfig-pt2-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: multi_v7_defconfig: Enable CPCAP related options mostly as loadable modules
ARM: omap2plus_defconfig: Add UINPUT
ARM: omap2plus_defconfig: Enable MDM6600 USB PHY
ARM: omap2plus_defconfig: Add AUDIO_GRAPH_CARD
ARM: omap2plus_defconfig: Enable PWM_VIBRA
DRM driver rather than the old fbdev driver.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJasF+5AAoJEEEQszewGV1zJgkQAJTBwdiHz27RVKEONPkPcnFd
v95Molxg55Zyj38jJiLx4TVbNuIdshafh8GD584Au4Pc7mkqLoYnqPKJXRMAshPG
k77UJgJkbUYhY1/WrxIi9WmuPr7UEaKz1xCl37cKU9tu7tNMm5K89xAsj9Kk9/D+
PgAMza/G4h13UiEN/HWa4uwzjuy+HQWPji2kNJm8k3Vt/fd7eFfUK8POBJPLXP9z
FCg5CncgRfbpExM1wt305yBX5RxNJsL86wV/BiOGPeaJ1zvx6jOQsCjp527SehMi
w6icPRAb4pRibDmtMXudLxh/YiZd3RsrIktC8HHdg48cdEf8x8/30POM5sy5sIqs
uQABdCIRQQI2tLF2ljIt5LKFmVykC/JTYWF0t+0faV6GICL2NuXiiRY8jINgK+rD
dRoNtqz+0LH0p0Kkb3diyP8kt0p8O9iso0SlliKkrfvGW8Kcy8rok/qB0CbQnE2u
nNycoarV48P+IH7Q1AMEca6SI5/rs3j0v0v1/oc6UoPmx6VGcNwUbfI/ylpo0ckC
MMEborBmQBKnm9BosTRgweDuLMuz94nZti82KgoNvoqPyukcmoYFYqqfuak6aaVi
EAE3MFNl+pte1rUx/YBO4ks9LgoxMOezY1VNZYE7hM6OqOB8U1RlHB2vjQN7mFpK
KupmpNphbEi010ls2v8C
=Yh10
-----END PGP SIGNATURE-----
Merge tag 'armsoc-versatile-drm-defconfig' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
Pull "defconfig changes for Versatile DRM" from Linus Walleij:
This augments the RealView and Versatile defconfig to use the PL111
DRM driver rather than the old fbdev driver.
* tag 'armsoc-versatile-drm-defconfig' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: defconfig: Configure Versatile boards to use PL111 DRM
ARM: defconfig: Update Versatile defconfig
ARM: defconfig: Switch RealView boards to use P111 DRM
ARM: defconfig: Update RealView defconfig
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Acked-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Smatch complains that "tmp" can be uninitialized if we do a zero size
write.
Fixes: 02a5d6925c ("ALSA: pcm: Avoid potential races between OSS ioctls and read/write")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
If we failed to create the top debugfs directory, we must not try to
create the child nodes. We currently only check if gpio_mockup_dbg_dir
is not NULL, but it can also contain an errno if debugfs is disabled
in build options. Use IS_ERR_OR_NULL() instead.
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Pyra-Handheld originally used the tca6424 but recently we have
replaced it by the pin and package compatible pcal6524. So let's
add this to the bindings and the driver.
And while we are at it, the pcal9555a does not have a compatible entry
either but is already supported by the device id table.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Enable an optional bus clock provided by DT.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new challenge is to remove VLAs from the kernel
(see https://lkml.org/lkml/2018/3/7/621)
This patch replaces a VLA with an appropriate call to kmalloc_array.
Signed-off-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new challenge is to remove VLAs from the kernel
(see https://lkml.org/lkml/2018/3/7/621)
This patch replaces several a VLA with an appropriate call to
kmalloc_array.
Signed-off-by: Laura Abbott <labbott@redhat.com>
Reviewed-and-tested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We need to enable MMC_SDHCI option in both omap2plus_defconfig and
multi_v7_defconfig so systems are able to mount root when the dts files
get updated for sdhci.
Then let's update omap2plus_defconfig so we can patch it easier. And as
Arnd noticed earlier, just running make savedefconfig will accidentally
drop few Kconfig options. This is happening because some options are no
longer available as loadable modules like LIRC. Or new dependencies have
been added such as SND_OSSEMUL for selecting SOUND_OSS_CORE.
So we first move the unchanged options around to their make savedefconfig
suggested place, then update the options to prevent make savedefconfig
dropping some options accidentally, and then finally drop the unused
options.
And after that we enable options DRM_OMAP and 8250_OMAP. These both have
been around for years now. And we do have 8250_OMAP warn about console
being redirected with SERIAL_8250_OMAP_TTYO_FIXUP option that is enabled
by default. Some users may need to update their inittab to use ttyS*
instead of ttyO* though. If this turns out to be a problem, we may want
to introduce a separate compatible for 8250-omap. But I think we're good
to go with the SERIAL_8250_OMAP_TTYO_FIXUP warning now. Let's not update
multi_v7_defconfig yet though and first see how 8250_OMAP change plays
out.
We also enable few new options for PM on am335x and am437x, and CEC in
omap2plus_defconfig. Naturally similar options can be later on added to
multi_v7_defconfig, but in this series we only enable OTG, MUSB and the
related PHYs in multi_v7_defconfig to make it more usable for distros.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlqr41kRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNxjQ/+MgYwuKg0LqS08IAWjhvX/IMusflvEeDg
GT7hnBSV/8O9yqSwwqKYAKimxIZQxrYfEd6Bhv7RZqRfP91VruM+WRAi1ka1aglB
uVRmoIlGV8hcvys84y0S3xyNUlX5GKit3EYtYjP/qZfJceonZyf89U2GD6tGIrb4
uSsGhnqGjJ9cektWHG8SHrBfoxSGDmjWjdzcar6B4/oybwnvdCcjqlbu1+qfmvRC
GICglk9ud2EeisCzSk7bvQIjVHsgziL9czoeyb37I0IeKfG+7RS5mUjdCM35KF5f
OYgWkE1aqimhWG7ktZgI3VQQ89yNT3d1erhO8ZEsHTCS47vHJ4oYi6JXY+20Fp+0
UQKhKNWmv7GHkH60Sgd85dK3p7NuuBEzTcNJjMbJLzyPYWnphk64W6wylwiwTSW0
JWue4rax4t9akfaFfctF7k9F5Cskxj++t7aIg2xJutzEnuXR8L/p+u3dmEKEq9Jl
0dfhrwM+ceznXNACgVsZK4QUnHQCp/WPIWZc7YEWrCjfgNU/Q4j3n4DyPhZ2gEXS
h8l1ESLjUDoPy5GoX6Mfx06G2ImSOLdvFArWmVfi/uhPsaozi3cmrBEvCIRFRDg7
8vWB1r+aK928mL6zUmmpCv5YoZl7f7Fxnu4vBDbGn3FDKLWUaVXesdU9GmTc0jq3
KT55Il7PVxo=
=JiEi
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.17/defconfig-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "Defconfig updates for omap variants for v4.17 merge window"
from Tony Lindgren:
We need to enable MMC_SDHCI option in both omap2plus_defconfig and
multi_v7_defconfig so systems are able to mount root when the dts files
get updated for sdhci.
Then let's update omap2plus_defconfig so we can patch it easier. And as
Arnd noticed earlier, just running make savedefconfig will accidentally
drop few Kconfig options. This is happening because some options are no
longer available as loadable modules like LIRC. Or new dependencies have
been added such as SND_OSSEMUL for selecting SOUND_OSS_CORE.
So we first move the unchanged options around to their make savedefconfig
suggested place, then update the options to prevent make savedefconfig
dropping some options accidentally, and then finally drop the unused
options.
And after that we enable options DRM_OMAP and 8250_OMAP. These both have
been around for years now. And we do have 8250_OMAP warn about console
being redirected with SERIAL_8250_OMAP_TTYO_FIXUP option that is enabled
by default. Some users may need to update their inittab to use ttyS*
instead of ttyO* though. If this turns out to be a problem, we may want
to introduce a separate compatible for 8250-omap. But I think we're good
to go with the SERIAL_8250_OMAP_TTYO_FIXUP warning now. Let's not update
multi_v7_defconfig yet though and first see how 8250_OMAP change plays
out.
We also enable few new options for PM on am335x and am437x, and CEC in
omap2plus_defconfig. Naturally similar options can be later on added to
multi_v7_defconfig, but in this series we only enable OTG, MUSB and the
related PHYs in multi_v7_defconfig to make it more usable for distros.
* tag 'omap-for-v4.17/defconfig-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: multi_v7_defconfig: Enable USB gadget configfs as loadable module
ARM: multi_v7_defconfig: Enable various USB PHYs found on omap variants
ARM: multi_v7_defconfig: Enable OTG and MUSB as loadable modules
ARM: omap2plus_defconfig: Enable 8250_OMAP
ARM: omap2plus_defconfig: Switch to use omapdrm by default
ARM: omap2plus_defconfig: Enable CEC
ARM: omap2plus_defconfig: Enable am335x and am437x PM options
ARM: omap2plus_defconfig: Drop unneeded options
ARM: omap2plus_defconfig: Add SND_OSSEMUL
ARM: omap2plus_defconfig: Update LIRC options
ARM: omap2plus_defconfig: Select MFD_TI_LMU
ARM: omap2plus_defconfig: Add SERIAL_DEV for bluetooth
ARM: omap2plus_defconfig: Update for moved options
ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
ARM: multi_v7_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
UniPhier SoCs have the following pins for hardware flow control of UART:
XRTS, XCTS
and for modem control of UART:
XDTR, XDSR, XDCD, XRI
The port number with the flow control is SoC-dependent.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Updates to shmobile defconfig:
* Redresh defconfig to ease future maintenence overhead
* Disable CONFIG_EMBEDDED
Geert Uytterhoeven says "CONFIG_EXPERT exposes too many config options
that do not matter for development. E.g. it prohibits using the default
values for the various SH_SCI options. However, CONFIG_EMBEDDED selects
CONFIG_EXPERT, so it cannot be disabled.
Hence disable CONFIG_EMBEDDED, and compensate for the loss of
CONFIG_DEBUG_KERNEL by enabling the latter.
Actual impact, all harmless:
- CONFIG_NAMESPACES=y (plus a few related CONFIG_*_NS options),
- CONFIG_SYSCTL_SYSCALL=n,
- CONFIG_SERIAL_SH_SCI_NR_UARTS changed from 20 to 18,
- Some HID support became enabled,
- CONFIG_DEBUG_MEMORY_INIT=y,"
* Enable RZA1 pin controller
This allows the Genmai board with RZ/A1 (r7s72100) SoC to once
again boot using the shmobile defconfig.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlqrxKEACgkQ189kaWo3
T74k2hAAijFk6suGGzLl+03XL/iT/C95iOFgkzJlbQB1OiU4WFlfrOfq2CXEZwIw
ccAKiVDhaw2WEFDRrAlLDx95yP7vrzQnCDPLE8CM/ulWLFTbNgdfwNska0blE+++
kE/o6ljyutc5TScDZU/aKJoA/VJ48ud/N7nf2X4Lnkp+ClaFq/DOiI/fo78yKm56
XlMN6V7p2vUUna6yvFJQMgX27rDFDGSujZnZX3XKLEPlLLCQS0gFzSKmX5matyL9
j3QtCgFqENSWsOxjpWCfyTyaa5Ovs65LeYR352itKWIfqemRmcNkyhoVcQmkhz57
T41ZXULCYs7R5gCY3gywBhIZ7hwhFJq/RnAnHBDZJ9i3QdtRlVLNzgvqTGpQ7SWR
j9j8n+Nnopj4mdqaM3ri80NDMiVjfQnzAbAN5UXbYgTAlKbsBSQkX9hBhl5Vst4B
uvNe4dNWodVS3wCBea9cw7aRbkBnZ3fElbkNX0KaRMtLinjNj0dXkTIcLTJz1P6g
baGeC+gZnk20OqMEM0CHn/FjWFofJ7QcBmmTyhf+IBb6nScR8Fjku8AKeFM6zsls
Zz3Xzfc8DJ08RGLHCuu9hwB1WREPIcE8rXrpuFj/LBCHtbb7T/dCGoqiJN6oy+Ti
LOoT7E2eTgVJSI3p+LYhigSDiGN3eczlbxIdMqdXOv/piPyqI+k=
=+vqH
-----END PGP SIGNATURE-----
Merge tag 'renesas-defconfig-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC Defconfig Updates for v4.17" from Simon Horman:
Updates to shmobile defconfig:
* Redresh defconfig to ease future maintenence overhead
* Disable CONFIG_EMBEDDED
Geert Uytterhoeven says "CONFIG_EXPERT exposes too many config options
that do not matter for development. E.g. it prohibits using the default
values for the various SH_SCI options. However, CONFIG_EMBEDDED selects
CONFIG_EXPERT, so it cannot be disabled.
Hence disable CONFIG_EMBEDDED, and compensate for the loss of
CONFIG_DEBUG_KERNEL by enabling the latter.
Actual impact, all harmless:
- CONFIG_NAMESPACES=y (plus a few related CONFIG_*_NS options),
- CONFIG_SYSCTL_SYSCALL=n,
- CONFIG_SERIAL_SH_SCI_NR_UARTS changed from 20 to 18,
- Some HID support became enabled,
- CONFIG_DEBUG_MEMORY_INIT=y,"
* Enable RZA1 pin controller
This allows the Genmai board with RZ/A1 (r7s72100) SoC to once
again boot using the shmobile defconfig.
* tag 'renesas-defconfig-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: defconfig: Disable CONFIG_EMBEDDED
ARM: shmobile: defconfig: Refresh
ARM: shmobile: Enable RZA1 pin controller
Enable the following to allow them to be more widely exercised:
* Newly added R8A77965 and R8A77980 SoCs
* PWM and USB as used on R-Car Gen3 SoCs
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlqrsFAACgkQ189kaWo3
T74aUA//XqcEz2mbp+CnO6tfAhRnWP9tAQ4MTOvs9TaWR0k97dFIWskVta5Q78eE
NHsHtmsck0WX+MsBq/aLJ6Vch2QsUn+e/KcaV2UyjLOeL4g4KJYLF2S0iVoiNRW+
7HmL0Lv5HyI64fGRHzO8BrrGFEYm0l54eRkg74GiQoLApyJmd/2sMsgxT7cWVpp7
pjQzTfIzI+Z0h5S83paCInZVaLztmvTnm1ZVoxjHwgtHOHgjmm+6Tn5YDyv5AxG1
xkfYH5rREOPpdj7ZcLktzQ7XPfXqGiwT3qPmx8MuXSRrG4AcTaNSYtqfr2S6yLm5
PlY0352xLSt+sBZw3va0sobcZOGxkPAmwwycw6yU0FST/hSgpbVIKmCetFD2aYIg
jltBUzRN5ST1A0/i9IAG1lruwYyzzVH/h40AQcH4CT5HvLI8k1e0Omp0N2eJie4c
1esYFW453l1+VyHPGan7Nmj/dgh8pDvu1GQyqdEPnMoP1YnkiMkhc9JuMDTrARWS
KdRLc9ysPUpHsyEh1RH/0nlc0262tw7l+HEQiPCT8iaY+x6iYLoxwXkRz8KYiwN9
MrZo3eqOjJdL5FXO8C/Z577jOYaZv8/do9FeEQdmVdqObgnDcJdKYenFxBXpr3RX
mruqjrctjcUwQ632ZSR0gf/su7E4rS3qpH+X8T8D6RxbER232fg=
=heZq
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-defconfig-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM64 Based SoC Defconfig Updates for v4.17" from Simon Horman:
Enable the following to allow them to be more widely exercised:
* Newly added R8A77965 and R8A77980 SoCs
* PWM and USB as used on R-Car Gen3 SoCs
* tag 'renesas-arm64-defconfig-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: defconfig: enable R8A77965 SoC
arm64: defconfig: Enable PWM and USB for R-Car
arm64: defconfig: enable R8A77980 SoC
Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so
really all that's involved is letting io-pgtable know the appropriate
upper bound for T0SZ.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Implement SMMUv3.1 support for 52-bit physical addresses. Since a 52-bit
OAS implies 64KB translation granule support, permitting level 1 block
entries there is simple, and the rest is just extending address fields.
Tested-by: Nate Watterson <nwatters@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Bring io-pgtable-arm in line with the ARMv8.2-LPA feature allowing
52-bit physical addresses when using the 64KB translation granule.
This will be supported by SMMUv3.1.
Tested-by: Nate Watterson <nwatters@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
As with registers and tables, use GENMASK and the bitfield accessors
consistently for queue fields, to save some lines and ease maintenance
a little. This now leaves everything in a nice state where all named
field definitions expect to be used with bitfield accessors (although
since single-bit fields can still be used directly we leave some of
those uses as-is to avoid unnecessary churn), while the few remaining
*_MASK definitions apply exclusively to in-place values.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
As with registers, use GENMASK and the bitfield accessors consistently
for table fields, to save some lines and ease maintenance a little. This
also catches a subtle off-by-one wherein bit 5 of CD.T0SZ was missing.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The FIELD_{GET,PREP} accessors provided by linux/bitfield.h allow us to
define multi-bit register fields solely in terms of their bit positions
via GENMASK(), without needing explicit *_SHIFT and *_MASK definitions.
As well as the immediate reduction in lines of code, this avoids the
awkwardness of values sometimes being pre-shifted and sometimes not,
which means we can factor out some common values like memory attributes.
Furthermore, it also makes it trivial to verify the definitions against
the architecture spec, on which note let's also fix up a few field names
to properly match the current release (IHI0070B).
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Before trying to add the SMMUv3.1 support for 52-bit addresses, make
things bearable by cleaning up the various address mask definitions to
use GENMASK_ULL() consistently. The fact that doing so reveals (and
fixes) a latent off-by-one in Q_BASE_ADDR_MASK only goes to show what a
jolly good idea it is...
Tested-by: Nate Watterson <nwatters@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Currently, the arm-smmu-v3 driver expects to allocate MSIs for all SMMUs
with FEAT_MSI set. This results in unwarranted "failed to allocate MSIs"
warnings being printed on systems where FW was either deliberately
configured to force the use of SMMU wired interrupts -or- is altogether
incapable of describing SMMU MSI topology (ACPI IORT prior to rev.C).
Remedy this by checking msi_domain before attempting to allocate SMMU
MSIs.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Nate Watterson <nwatters@codeaurora.org>
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
It is annoyingly non-obvious when DMA transactions silently go missing
due to undetected SMMU faults. Help skip the first few debugging steps
in those situations by making it clear when we have neither wired IRQs
nor MSIs with which to raise error conditions.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Enable the BPMP thermal and CPU frequency drivers as well as make sure
that the Tegra SMMU is enabled by default because there's no fun without
it. Also enable initial Tegra194 support.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlqr0O4THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zocYJD/sFwO8dYXUhaRH9rS586XhNzxdMaRFe
q6/NDZ/K0KQ92BMvMDYYJBn8TqeuesEDCv08DWizYO8Bjpw1jcJyKZe3so631kak
CvAI8RZHVAe/E7jKLxvS+WcYxblMfZ9/4k9/ASVK7VreodNwRx07ftHaLv41tXUl
prgIf8xaeRAjs8pWAOYVT5wjMVK/1qORyZty0C93BapawMGDKLl6+geVyb8JlH2K
RQ1VNbMzeLfOHLNuU/34cViO4LaGlesjIxuVtKqmsp0qBFoqqtLfCtdpZ5BZj519
3FGwXdO5KZMQ8SosNmE8nfdU7fixDSjmu67Kei185Huko9F+jFLNsMsefBYOG9Hh
EmU0+KPJTpcEUlWi//Vr3VRXJ+1iwLrAmgCYYgTPSApasTs5jBPdM2PM1bxDdkqc
zB7daX8DAK5mb7Hfld70ZpfuWGMkHqNabDcnvL5bDOMVgFH0animARxX/Gr4ktCa
KBp4zwlv7xJq9yLIMbvOgCwjEWqMAYrPHPaQ15AgMkzucb32j7WCpnk+M2YmXuOh
pgzziU27pGO5D/NbHjSVku4O/XZWjFiCHy2tbYtFEt0pz4QLGRG/jm2CA1woAIVp
J5NDKqZ8irfyk5ZIKUA6lhkg2SxZ9E/Ua8WyvF07DjpPykGrNDwRcazh/LYXryYh
raRtzJij4wdoJA==
=Lnk+
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.17-arm64-defconfig' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
Pull "arm64: Default configuration updates for v4.17-rc1" from Thierry Reding:
Enable the BPMP thermal and CPU frequency drivers as well as make sure
that the Tegra SMMU is enabled by default because there's no fun without
it. Also enable initial Tegra194 support.
* tag 'tegra-for-4.17-arm64-defconfig' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable the Tegra SMMU by default
arm64: defconfig: Enable CONFIG_TEGRA_BPMP_THERMAL
arm64: defconfig: Enable CONFIG_ARM_TEGRA186_CPUFREQ
arm64: defconfig: Enable NVIDIA Tegra194 support
When selecting SOC_IMX6SLL but not SOC_IMX6SL, we get a link error:
arch/arm/mach-imx/mach-imx6sl.o: In function `imx6sl_init_late':
mach-imx6sl.c:(.init.text+0x14): undefined reference to `imx6sl_cpuidle_init'
This adds the missing line to the Makefile to also build the cpuidle
support that we need here.
Fixes: dee5dee2a5 ("ARM: imx: Add basic msl support for imx6sll")
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The cpuidle support calls cpu_suspend(), which is compiled conditionally,
and fails to link unless something selects CONFIG_ARM_CPU_SUSPEND.
arch/arm/mach-imx/cpuidle-imx6sx.o: In function `imx6sx_enter_wait':
cpuidle-imx6sx.c:(.text+0x6c): undefined reference to `cpu_suspend'
This adds an explicit select statement here.
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs power
domain (called CPUS-PORT in user manual).
This commit introduces support for the main pin controller on H6.
The pin bank A and B are not wired out and hidden from the SoC's
documents, however it's shown that the "ATE" (an AC200 chip
co-packaged with the H6 die) is connected to the main SoC die via these
pin banks. The information about these banks is just copied from the BSP
pinctrl driver, but re-formatted to fit the mainline pinctrl driver
format. The GPIO functions are dropped, as they're impossible to use --
except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add SFP module support for Clearfog using the SFP phylink support.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The internal RTC does not work correctly on these Linksys boards based
on Marvell SoCs. For me it only shows Wed Dec 31 23:59:59 1969 and for
others it is off by 3 minutes in 10 minutes running, this was reported
by multiple users. On the Linksys Mamba device the device tree comment
says that no crystal is connected to the internal RTC, this is probably
also true for the other devices.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some
refactors in the sunxi pinctrl framework are needed.
This commit introduces a IRQ bank conversion function, which replaces
the "(bank_base + bank)" code in IRQ register access.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
