Commit graph

504537 commits

Author SHA1 Message Date
Kai Huang
88178fd4f7 KVM: x86: Add new dirty logging kvm_x86_ops for PML
This patch adds new kvm_x86_ops dirty logging hooks to enable/disable dirty
logging for particular memory slot, and to flush potentially logged dirty GPAs
before reporting slot->dirty_bitmap to userspace.

kvm x86 common code calls these hooks when they are available so PML logic can
be hidden to VMX specific. SVM won't be impacted as these hooks remain NULL
there.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-29 15:31:41 +01:00
Kai Huang
1c91cad423 KVM: x86: Change parameter of kvm_mmu_slot_remove_write_access
This patch changes the second parameter of kvm_mmu_slot_remove_write_access from
'slot id' to 'struct kvm_memory_slot *' to align with kvm_x86_ops dirty logging
hooks, which will be introduced in further patch.

Better way is to change second parameter of kvm_arch_commit_memory_region from
'struct kvm_userspace_memory_region *' to 'struct kvm_memory_slot * new', but it
requires changes on other non-x86 ARCH too, so avoid it now.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-29 15:31:37 +01:00
Kai Huang
9b51a63024 KVM: MMU: Explicitly set D-bit for writable spte.
This patch avoids unnecessary dirty GPA logging to PML buffer in EPT violation
path by setting D-bit manually prior to the occurrence of the write from guest.

We only set D-bit manually in set_spte, and leave fast_page_fault path
unchanged, as fast_page_fault is very unlikely to happen in case of PML.

For the hva <-> pa change case, the spte is updated to either read-only (host
pte is read-only) or be dropped (host pte is writeable), and both cases will be
handled by above changes, therefore no change is necessary.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-29 15:31:33 +01:00
Kai Huang
f4b4b18086 KVM: MMU: Add mmu help functions to support PML
This patch adds new mmu layer functions to clear/set D-bit for memory slot, and
to write protect superpages for memory slot.

In case of PML, CPU logs the dirty GPA automatically to PML buffer when CPU
updates D-bit from 0 to 1, therefore we don't have to write protect 4K pages,
instead, we only need to clear D-bit in order to log that GPA.

For superpages, we still write protect it and let page fault code to handle
dirty page logging, as we still need to split superpage to 4K pages in PML.

As PML is always enabled during guest's lifetime, to eliminate unnecessary PML
GPA logging, we set D-bit manually for the slot with dirty logging disabled.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-29 15:31:29 +01:00
Kai Huang
3b0f1d01e5 KVM: Rename kvm_arch_mmu_write_protect_pt_masked to be more generic for log dirty
We don't have to write protect guest memory for dirty logging if architecture
supports hardware dirty logging, such as PML on VMX, so rename it to be more
generic.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-29 15:30:38 +01:00
Steven Rostedt (Red Hat)
64d982838e ktest: Rename start_monitor_and_boot to start_monitor_and_install
The function start_monitor_and_boot is a misnomer. It use to, but
now it starts the monitor and installs. It does not boot. Rename it
before I get confused by it again.

Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2015-01-29 09:02:07 -05:00
Steven Rostedt (Red Hat)
38fa3dc15c ktest: Show times for build, install, boot and test
Seeing the times for how long a build, install, reboot and the
test takes is helpful for analyzing the test process. Seeing
how different changes affect the timings.

Show the build, install, boot and test times when at the end of
the test, or between each interval for tests that do those
mulitple times (like bisect and patchcheck).

Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2015-01-29 09:02:06 -05:00
Ping Cheng
500d4160ab HID: wacom: add support for Cintiq 27QHD and 27QHD touch
These devices have accelerometers. To report accelerometer coordinates, a new
property, INPUT_PROP_ACCELEROMETER, is added.

Signed-off-by: Ping Cheng <pingc@wacom.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2015-01-29 14:05:05 +01:00
Ping Cheng
a2f71c6c87 HID: wacom: consolidate input capability settings for pen and touch
After PAD moved to its own interface, there were duplicated statements in
wacom_setup_pentouch_input_capabilities. Merge them together to reduce future
maintenance effort.

Signed-off-by: Ping Cheng <pingc@wacom.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2015-01-29 14:05:04 +01:00
Ping Cheng
9b61aa864a HID: wacom: make sure touch arbitration is applied consistently
stylus_in_proximity is used to make sure no touch event is sent while pen is in
proximity. touch_down is used to make sure a touch up event is sent when pen
comes into proximity while touch is down.

Two touch routines didn't store touch_down. One touch routine forgot to check
stylus_in_proximity before sending touch events. This patch fixes those issues.

Signed-off-by: Ping Cheng <pingc@wacom.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2015-01-29 14:05:04 +01:00
Rob Herring
35a8578e8b dts: versatile: Add sysregs node
The Versatile boards have the same sysregs as other ARM Ltd boards. Add
the nodes in order to enable support for 24MHz counter as sched_clock.

This is a minimal node definition as the existing sub node definition
used on VExpress has some issues raised by Linus W.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:16 +01:00
Rob Herring
f2fa0299d3 clocksource: versatile: Adapt for Versatile AB and PB boards
The same 24MHz counter is also present on Versatile AB and PB boards, so
add the compatible string for them.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:16 +01:00
Rob Herring
1a18554b96 dt/bindings: Add binding for Versatile system registers
Add binding for Versatile board system registers found in the FPGA of the
Versatile/AB and Versatile/PB boards.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:15 +01:00
Baruch Siach
9b8bb7736b clocksource: Driver for Conexant Digicolor SoC timer
Add clocksource driver to the Conexant CX92755 SoC, part of the Digicolor SoCs
series. Hardware provides 8 timers, A to H. Timer A is dedicated to a future
watchdog driver so we don't use it here. Use timer B for sched_clock, and timer
C for clock_event.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:15 +01:00
Baruch Siach
9ff99be7dc clocksource: devicetree: Document Conexant Digicolor timer binding
The Conexant CX92755 SoC provides 8 32-bit timers as part of its so called
"Agent Communication" block. Timers can be configures either as free running or
one shot. Each timer has a dedicated interrupt source in the CX92755 interrupts
controller. The first timer (Timer A) can also be configured as watchdog.

This commit adds devicetree binding definition of this hardware module. The
binding defined here should be reusable for other SoCs in the Digicolor series.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:14 +01:00
Daniel Lezcano
468b8c4cf3 clockevents: rockchip: Add rockchip timer for rk3288
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.

This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.

The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.

Programing sequence:

1. Timer initialization:
 * Disable the timer by writing '0' to the CONTROLREG register
 * Program the timer mode by writing the mode to the CONTROLREG register
 * Set the interrupt mask

2. Setting the count value:
 * Load the count value to the registers COUNT0 and COUNT1 (not used).

3. Enable the timer
 * Write '1' to the CONTROLREG register with the mode (free running or user)

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-29 14:02:13 +01:00
Oleksij Rempel
8d8bd7be8b ARM: clocksource: Add asm9260_timer driver
In some cases asm9260 looks similar to iMX2x. One of exceptions is
timer controller. So this patch introduces new driver for this special case.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:06 +01:00
Barry Song
5833ac9865 clocksource: marco: Rename marco to atlas7
marco project is replaced by atlas7 and we should obliterate
its all traces.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-01-29 14:02:06 +01:00
Chang Rebecca Swee Fun
920dfd8247 gpio: sch: Consolidate similar algorithms
Consolidating similar algorithms into common functions to make
GPIO SCH simpler and manageable.

Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 13:46:29 +01:00
Tomeu Vizoso
6234f38016 PM / devfreq: tegra: add devfreq driver for Tegra Activity Monitor
The ACTMON block can monitor several counters, providing averaging and firing
interrupts based on watermarking configuration. This implementation monitors
the MCALL and MCCPU counters to choose an appropriate frequency for the
external memory clock.

This patch is based on work by Alex Frid <afrid@nvidia.com> and Mikko
Perttunen <mikko.perttunen@kapsi.fi>.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
2015-01-29 21:25:48 +09:00
Marcin Wojtas
1140011ee9 mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.

This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not
inverted.
- Set the Sample FeedBack Clock field to 0x1

[gregory.clement@free-electrons.com: port from 3.10]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 13:08:46 +01:00
Gregory CLEMENT
d58a2ea5cb mmc: sdhci-pxav3: Extend binding with SDIO3 conf reg for the Armada 38x
The SDHCI unit used on the Armada 38x needs using an extra register to
do specific clock adjustments in order to support the SDR50 and DDR50
modes. This patch extends the binding to allow using this register.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 13:08:22 +01:00
Marcin Wojtas
a39128bcd6 mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ERR-7878951
According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
different capabilities than the ones shown in its registers:

- it doesn't support the voltage switching: it can work either with
  3.3V or 1.8V supply
- it doesn't support the SDR104 mode
- SDR50 mode doesn't need tuning

The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the
capabilities accordingly.

[gregory.clement@free-electrons.com: port from 3.10]

Fixes: 5491ce3f79 ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc: <stable@vger.kernel.org> # v3.15+

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 13:08:02 +01:00
Gregory CLEMENT
d4b803c559 mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.

This commit is based on the work done by Marcin Wojtas<mw@semihalf.com>

Fixes: 5491ce3f79 ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 13:07:41 +01:00
Peter Rosin
9c7da1a57b ASoC: pcm512x: Use the correct range constraints for S24_LE
This was overlooked in the late change to remove the I2S padding bits
from S24_LE mode. The patch also limits S32_LE mode to 384kHz, the
maximum according to the datasheets.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-01-29 12:02:29 +00:00
Peter Rosin
2599a9609c ASoC: pcm512x: Fixup warning splat
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-01-29 12:02:29 +00:00
Arnd Bergmann
4c121129c9 ASoC: rt5677: fix SPI dependency
The rt5677 codec has gained code that requires SPI to work correctly,
but there is no provision in Kconfig to prevent the driver from
being used when SPI is disabled or a loadable module, resulting
in this build error:

sound/built-in.o: In function `rt5677_spi_write':
:(.text+0xa7ba0): undefined reference to `spi_sync'
sound/built-in.o: In function `rt5677_spi_driver_init':
:(.init.text+0x253c): undefined reference to `spi_register_driver'

ERROR: "spi_sync" [sound/soc/codecs/snd-soc-rt5677-spi.ko] undefined!
ERROR: "spi_register_driver" [sound/soc/codecs/snd-soc-rt5677-spi.ko] undefined!

This makes the SPI portion of the driver depend on the SPI subsystem,
and disables the function that uses SPI for firmware download if SPI
is disabled. The latter may not be the correct solution, but I could
not come up with a better one.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: af48f1d08a ("ASoC: rt5677: Support DSP function for VAD application")
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-01-29 11:52:21 +00:00
Arnd Bergmann
f9a7ba3269 ASoC: davinci: fix DM365_EVM codec selection
An earlier bug fix of mine made the SND_DM365_VOICE_CODEC symbol
tristate to avoid creating an undefined reference from the
davinci-vcif.c driver to the davinci_soc_platform_register
function that may be in a module.

However, this may now lead to a different error on randconfig
kernels:

"warning: SND_DM365_VOICE_CODEC creates inconsistent choice state"

This happens because we now have a choice statement with
one bool and one tristate option, and the latter might not
support being set to 'y' because of dependencies.

This new change turns the other option into 'tristate' as well,
which avoids the problem.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 19926c6de0 ("ASoC: davinci: vcif must be a module if SND_DAVINCI_SOC is")
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-01-29 11:51:29 +00:00
Laurent Pinchart
eb2ed66fe5 drm/irq: Don't disable vblank interrupts when already disabled
The .enable_vblank() operation is only called when vblank interrupts are
disabled, but no similar check exists when disabling vblank interrupts.
This leads to .disable_vblank() being called with vblank interrupts
already disabled and the device possibly runtime suspended. As the
operation is called with a spinlock held drivers can't runtime resume
the device there and thus must avoid touching device registers in that
case, requiring vblank refcounting.

As the DRM core tracks whether vblank interrupts are enabled just skip
the .disable_vblank() call when the interrupts are already disabled.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-29 12:50:03 +01:00
Jisheng Zhang
3396e73611 mmc: sdhci: switch voltage before sdhci_set_ios in runtime resume
I observed the Host Control2 register isn't correctly restored
after runtime resuming on BG2Q. For example, the register reads
as 0x800c before runtime suspend, but it's set as 0x8004 after runtime
resuming. This could results in a non working host.

The reason is the Host Control2 is incorrectly reset when switching
voltage. We fix this by following the same sequence during initialization.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 11:28:06 +01:00
Rajkumar Manoharan
6c3d7d7859 ath10k: fix target wakeup timeout
During drv_start/drv_stop stress testing in ARM platform,
sometimes target is taking more that 5ms to wake up. Similar
behaviour also noted during driver load and unload iterations.
On such cases, the wakup duration lies between 5-6ms. Hence
increasing pci wakup timeout 10ms to be more safer. With this
changes, able to complete power down/up >100 iterations without
any issues.

Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:26:28 +02:00
Yanbo Li
d68bb12ab4 ath10k: Enable the MCS8 and MCS9 at 2.4G band
Enable the MCS8 and MCS9 support for 2.4G band, it will
use these data rate with other devices having the same
capability.

Signed-off-by: Yanbo Li <yanbol@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:25:17 +02:00
Pavan Kunapuli
352ee868dd mmc: tegra: Write xfer_mode, CMD regs in together
If there is a gap between xfer mode and command register writes,
tegra SDMMC controller can sometimes issue a spurious command before
the CMD register is written. To avoid this, these two registers need
to be written together in a single write operation.

This is implemented as an NVQUIRK as it applies to T114, T124 and
T132.

Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 11:21:58 +01:00
Michal Kazior
46725b1533 ath10k: disable sta keepalive
Firmware revisions providing sta keepalive service
have it enabled by default.

mac80211 already does idle connection polling so
it makes no sense to duplicate this in ath10k.
mac80211 wouldn't even know of the offloaded
keepalive NullFunc frames.

This prevents sending out some extraneous frames
on the air.

Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com>
Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:15:45 +02:00
Alexey Skidanov
0501be6429 mmc: Resolve BKOPS compatability issue
This patch is coming to fix compatibility issue of BKOPS_EN  field of EXT_CSD.
In eMMC-5.1, BKOPS_EN was changed, and now it has two operational bits:
Bit 0 - MANUAL_EN
Bit 1 - AUTO_EN
In previous eMMC revisions, only Bit 0 was supported.

Signed-off-by: Alexey Skidanov <alexey.skidanov@sandisk.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 11:15:12 +01:00
Janusz Dziedzic
6e8b188ba7 ath10k: implement sta keepalive command
New wmi-tlv firmware for qca6174 has STA keepalive
service available. The service can provide
automatic idle connection polling via NullFunc
frames to AP when acting as a client.

Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com>
Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:15:00 +02:00
Michal Kazior
7fc979a79d ath10k: use per-vif wmm param setup if possible
New wmi-tlv firmware for qca6174 supports this.

This should fix issues related to multi-vif WMM.

Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:12:41 +02:00
Michal Kazior
6d492fe2d8 ath10k: implement per-vdev wmm param setup command
New wmi-tlv firmware for qca6174 supports this.
This will be used soon.

Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:12:02 +02:00
Michal Kazior
5e752e42f6 ath10k: move wmm param storage to vif
mac80211 already requests WMM per vif but firmware
wasn't able to handle this until now. However new
wmi-tlv firmware for qca6174 is capable of this.

This prepares per-vif WMM param setup.

Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-29 12:11:44 +02:00
Jisheng Zhang
14460dbaf7 mmc: sdhci-pxav3: fix setting of pdata->clk_delay_cycles
Current code checks "clk_delay_cycles > 0" to know whether the optional
"mrvl,clk_delay_cycles" is set or not. But of_property_read_u32() doesn't
touch clk_delay_cycles if the property is not set. And type of
clk_delay_cycles is u32, so we may always set pdata->clk_delay_cycles as a
random value.

This patch fix this problem by check the return value of of_property_read_u32()
to know whether the optional clk-delay-cycles is set or not.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Cc: <stable@vger.kernel.org> # v3.6+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-01-29 11:10:11 +01:00
Magnus Damm
e1ec9a49d1 pinctrl: sh-pfc: sh7372: Remove DT binding documentation
Remove the DT compatible string entry for the now unsupported sh7372 SoC.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:43:57 +01:00
Magnus Damm
62476634d7 pinctrl: sh-pfc: sh7372: Remove PFC support
Remove sh7372 PFC support as part of the sh7372 and Mackerel
legacy code removal.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:40:38 +01:00
Axel Lin
68d77d5168 gpio: tz1090-pdc: Use resource_size to fix off-by-one resource size calculation
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:34:13 +01:00
Axel Lin
74b18de94c gpio: ge: Convert to use devm_kstrdup
Use devm_kstrdup to simplify the error handling path.
Also return -ENOMEM instead of 0 if devm_kstrdup fails.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:33:15 +01:00
Olliver Schinagl
ef3b2bd6f3 gpio: correctly use const char * const
On my previous patch I was overly hasty and made the suffixes string
array
const char const *suffixes, instaed of const char * const suffixes. This
patch corrects that

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29 10:29:53 +01:00
Jesper Nilsson
dd82094cce CRIS: Fix missing NR_CPUS in menuconfig
The time Kconfig expects that NR_CPUS is defined.

This patch removes this config warning:
"kernel/time/Kconfig:163:warning: range is invalid"

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2015-01-29 10:10:08 +01:00
Jesper Nilsson
00c5794d2d CRISv32: Avoid warning of unused variable
Avoids the warning about:
warning: 'bite_in_progress' defined but not used [-Wunused-variable]

Variable is only used if the Kconfig CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
is set.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2015-01-29 10:10:08 +01:00
Jesper Nilsson
134115cd60 CRIS: Avoid warning in cris mm/fault.c
Move declaration of waitqueue to beginning of block,
avoids warning about mixing declarations and code.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2015-01-29 10:10:08 +01:00
Jesper Nilsson
4806f8bb8d CRIS: Export csum_partial_copy_nocheck
Allows that symbol to be used in modules, and fixes
the following on allmodconfig:

ERROR: "csum_partial_copy_nocheck" [net/ipv6/ipv6.ko] undefined!

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2015-01-29 10:10:08 +01:00
Rafał Miłecki
3f7bb3f34c b43: AC-PHY: prepare place for developing new PHY support
There are new (not anymore?) Broadcom 802.11ac wireless cards based on
chipsets like BCM4352 and BCM4360. They use a new PHY type (called
simply AC) that will require new specific code.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:54:43 +02:00