This adds GPIO support for the SSD201 and SSD202D chips.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
- New SoC support: i.MX8 ULP.
- New board support: i.MX8MM/MN based TQMa8Mx boards, iMX8MN BSH SMM S2,
i.MX8 ULP EVK.
- A series from Adam Ford to enable Camera and USB support for
imx8mm-beacon device.
- Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards.
- A series from Biwen Li to update LS1028A devices around RTC, flextimer
and PWM support.
- A series from Joakim Zhang to update ENET/FEC suppport on i.MX8M
devices.
- A couple of changes from Lucas Stach to update nitrogen8-som Ethernet
PHY and I2C1 pad configuration.
- A series from Martin Kepplinger to split out a shared imx8mq-librem5-r3
dtsi for Librem5 devices.
- Add cache descriptions for i.MX8 SoCs.
- A series from Vladimir Oltean to update ls1028a-rdb device tree in
order to share the DTS between Linux and U-Boot.
- Random device addtion to various i.MX8 and LX2160A based devices.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmG9hc4UHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM5tZAf/chwOQUH6gwyc76vb2mzcMlYq4jPN
vMxJZ6fJBf+QglOrGfSznl11SHNCGs+NBDvRkJt9JLKj1fHh/jUTZf5HCRnK62lH
YB+w2XxlthufTPujkVXM10Dsx65Up67Mo3ZN5/3M6Fd+w/P8YUzPEL0jD2dm7CDM
rKqe57kcJ6ZaJgASuPdVh51fwpmbCNOQZCRgg4Y+sunXzUVyjA/jOUaeQojg+m2e
TTe80CH+3fugipWkotAa8ypxAJEbeEsPvVB711UxTY28rE2BqDkcPMyOiq+9HW+M
AoqPeyeZffyJGwLblLCQTZzMEuWU9G87H+fda7b8sg7yFPvjefaj+4DbdA==
=ARjB
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAm/QACgkQmmx57+YA
GNk/4g/9GG9YYbOHzLDSit6I92eAwMhIxCE7ls2RrB/JBIi1v13qZ85YTPw9w1Bc
klRXP46fI6dVl7R7t0Vt2zt5MpuNnKAMZsHQR+UvB/Zll4RC7n29NEpWyFW0i4Yv
/G28Whmp1sQs8szrWwvOlxWMY3fSlQMKM4vrtJUU6Che5ec+PwgsRL2rWf5/cnJh
E9HqQ3eJMyP8cdayRnlUCI8yWAdXHkeDQhl7Mu97eX4l7Ka2OkDseEZY+HgRmQSv
Ee3X1EPxFHau9f842NtIwNz54Vdibfh+UHCzMeWOtDZXF8bhWVYp13joPNDM7AWM
0oYMh966t/JuU4cPCQxed61C9Laxg42TkCbfuU7dC5pqKlCdSZSKOmLe7c6vw3Vf
IGQwVgMh8/c3oJAbbPqWz+kfCg3O2KNzA3MnsQuizoLEwa5R4msqtk6FZ5uqR6d/
RYL9eZKzeZWPXwth1KCEx+qLFWuRxC5cdK181Hc/Srm3bzNf/6vfCcReRCvlfOiE
lU1kzHLOKtfUeWSEK3WFnWuTbU68NaH8rUZXpuTlV1kYEeBf/mD4aTOUW9hOh0v6
EYwpk2QYPBcUUYR2KC6gfyJTTwihn3FR8+RiJR+VFjlhNrNHbrNmp3Vo19yjgu/Y
brbFPEitQPnvXdrGAIfck9vHhO9VJ3xygo9SMowGsaRuFLunW/0=
=zQ1O
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree change for 5.17:
- New SoC support: i.MX8 ULP.
- New board support: i.MX8MM/MN based TQMa8Mx boards, iMX8MN BSH SMM S2,
i.MX8 ULP EVK.
- A series from Adam Ford to enable Camera and USB support for
imx8mm-beacon device.
- Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards.
- A series from Biwen Li to update LS1028A devices around RTC, flextimer
and PWM support.
- A series from Joakim Zhang to update ENET/FEC suppport on i.MX8M
devices.
- A couple of changes from Lucas Stach to update nitrogen8-som Ethernet
PHY and I2C1 pad configuration.
- A series from Martin Kepplinger to split out a shared imx8mq-librem5-r3
dtsi for Librem5 devices.
- Add cache descriptions for i.MX8 SoCs.
- A series from Vladimir Oltean to update ls1028a-rdb device tree in
order to share the DTS between Linux and U-Boot.
- Random device addtion to various i.MX8 and LX2160A based devices.
* tag 'imx-dt64-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (56 commits)
arm64: dts: imx8mp-evk: configure multiple queues on eqos
arm64: dts: ls1028a-qds: add overlays for various serdes protocols
arm64: dts: ls1028a-qds: enable lpuart1
arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus
arm64: dts: ls1028a-rdb: enable pwm0
arm64: dts: ls1028a: add flextimer based pwm nodes
arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
arm64: dts: ls1028a: Add PCIe EP nodes
arm64: dts: lx2162a-qds: add interrupt line for RTC node
arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes
arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes
arm64: dts: lx2160a-qds: Add mdio mux nodes
arm64: dts: lx2160a: add optee-tz node
arm64: dts: lx2160a-rdb: Add Inphi PHY node
arm64: dts: imx8mm: don't assign PLL2 in SoC dtsi
arm64: dts: nitrogen8-som: correct i2c1 pad-ctrl
arm64: dts: nitrogen8-som: correct network PHY reset
arm64: dts: imx8mn-bsh-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property
arm64: dts: imx8ulp: add power domain entry for usdhc
...
Link: https://lore.kernel.org/r/20211218071427.26745-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board support: TQ-Systems MBa6x, Y Soft IOTA Crux/Crux+ board,
JOZ Access Point, Phytec PEB-WLBT-05 support, BSH SMM-M2 IMX6ULZ
SystemMaster.
- Update SPBA bus node name to match binding schema.
- A series from Christoph Niedermaier to update imx6qdl-dhcom board
around Ethernet and USB support.
- A series from Giulio Benetti to clean up undocumented/unused fixed
clock compatibles.
- A series from Laurent Pinchart to update i.MX7 MIPI_CSI support.
- A couple of changes from Russell to update phy-mode for
vf610-zii-dev-rev-b board.
- Add Wacom digitizer support for imx7d-remarkable2 device.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmG9f3QUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM6v0Qf9EgOkEu4fn/GBbOXBBuh3bWMdw4vB
bJLQ4Ry6iqo/EDscbTWyjjVxlnIYRDa1D8d9ndZcs2wHY0TQhG87/KmH43iHmOAw
vdvIHoe3cgQuFrk15k/bgi2MQm9g8MayugK5xshiLQvOOpSUCBQHuk4oLyRACR3q
m1dpwe5CNaVABjuwZKHlmZq0DNGvN2QJosUbKyl6j8Bxo98I3sjHno0uNHfNaoPP
B7XUOozHf1mAoTBHVb22Ej0Zbpy5FiprOYZKhP7rvuQOnRhg7NcByIhd/s8uQAjA
t3Owq1VCZVEC98sHaZcN2qdAs8n42S+hPHT0WuV0v7SaV4hDCGxXipvxfg==
=uwuV
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAm5kACgkQmmx57+YA
GNnxRhAAuIK0GcrbM4v2jOnXUCBLRrJXZSPqI0Z1DrHIq5JPgqzR7jUcDnoV7T54
Q6b+Bt6XvRJPZlkr9M4p166Qd62KnzSZyxg23Wb0feF6R9TFCrXUeQjmGiBZqB1O
wNDm41Pv6EX7OOBPdRMfhbhPP+ezstJiMRxO99JfupwSPrcMJkgj6KzVdOwgvAg+
J1n33COkczYXJlt7LLADdaucBlB1IerKfRSPy0+mZszC2js2dJqCzVNwkwMXjBTy
5qmB5oBEoUQzeISgPjxp7xMQi57XBhk2UP5c2XWMvZ/OhgRpbWRZU5kBfTlRKXBV
VbdvEUpGHbAghXFwUnxQx/OC465wAgYyN+Rek7ZfWQ7VnD5XM1t2nYjCKOZPujcL
Kfe3HE8ssKyEp0gE3/ZfmMZehwzhXVf6r2wvqEiJAp7Nhigy4pE4A6AGNswVEY/i
Et/MLVOwhdOVlj7dCZfVg7SdlQouhFm8EmrR0zRCJKsdMid2l3MkU/eo7Zl8Slzu
LS6MyCs1T/2+i+HdZgoSFnqvBLqIUtqeTIvhw5zggar/i/nH2JXkJV4A7CuAWB6h
inUJAB9/2B5egqdTIPATI4T6nTu37wZOBl9ZGuijXyRa9wMVtwPr4lySkFFJyFIK
0a3TnHxQjdbDHFoO0kvfB4Yk65Z+rtpnZlPPJgVMn3GSz4ND1tw=
=cSJH
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm device tree change for 5.17:
- New board support: TQ-Systems MBa6x, Y Soft IOTA Crux/Crux+ board,
JOZ Access Point, Phytec PEB-WLBT-05 support, BSH SMM-M2 IMX6ULZ
SystemMaster.
- Update SPBA bus node name to match binding schema.
- A series from Christoph Niedermaier to update imx6qdl-dhcom board
around Ethernet and USB support.
- A series from Giulio Benetti to clean up undocumented/unused fixed
clock compatibles.
- A series from Laurent Pinchart to update i.MX7 MIPI_CSI support.
- A couple of changes from Russell to update phy-mode for
vf610-zii-dev-rev-b board.
- Add Wacom digitizer support for imx7d-remarkable2 device.
* tag 'imx-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (36 commits)
ARM: dts: imx6: phytec: Add PEB-WLBT-05 support
ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter
ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board
ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layer
ARM: dts: imx7d-remarkable2: add wacom digitizer device
ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMaster
ARM: dts: imx6qdl-dhcom: Identify the PHY by ethernet-phy-id0007.c0f0
ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs
ARM: dts: imx6qdl: drop "fsl,imx-ckih1"
ARM: dts: imx6qdl: drop "fsl,imx-ckil"
ARM: dts: imx6qdl: drop "fsl,imx-osc"
ARM: dts: imx53: drop "fsl,imx-ckih2"
ARM: dts: imx53: drop "fsl,imx-ckih1"
ARM: dts: imx53: drop "fsl,imx-ckil"
ARM: dts: imx53: drop "fsl,imx-osc"
ARM: dts: imx51: drop "fsl,imx-ckih2"
ARM: dts: imx51: drop "fsl,imx-ckih1"
ARM: dts: imx51: drop "fsl,imx-ckil"
ARM: dts: imx51: drop "fsl,imx-osc"
ARM: dts: imx50: drop "fsl,imx-ckih2"
...
Link: https://lore.kernel.org/r/20211218071427.26745-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
"spidev" is not a real device, but a Linux implementation detail. It has
never been documented either. The kernel has WARNed on the use of it for
over 6 years. Time to remove its usage from the tree.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20211217221232.3664417-1-robh@kernel.org'
Reviwed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* New Platforms:
- J721s2 SoC, SoM and Common Processor Board support
* New features:
- CAN support on AM64 EVM and SK
- TimeSync Router on AM64
* Fixes:
- Correct d-cache-sets info on J7200
- Fix L2 cache-sets value for J721e/J7200/AM64
- Fixes for dtbs_check warnings wrt serdes_ln_ctrl node on J721e/J7200
- Disable McASP on IoT2050 board to fix dtbs_check warnings
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmG8nQoQHHZpZ25lc2hy
QHRpLmNvbQAKCRDERh5FfJEW423oB/wMWRML3F6+LKGkDpm6Dme6oV24NzhnACBl
CQ0me3NpQEq4QELPasRwc9E4WOLGCGtDS1HByCrpCELFI7ET9ebwgo7yxl9nvJm+
nzSGwWY9/n3wtXhEc68r0if12WRuu59YTrhf+Q5GNF6uh4iv5aSmAfdSQmUljER5
hs1mZVAQflbxhsG5XR+OUGUvxQZ6Uy8F0OjW++a+ci3QtmQ9y+FUCIMdeLMvXD4C
efaWtFtselePPqN3AJMRddAgo/rbzXWBaX57LG8oMz4a223Ima7FpVB0sgzsnYh8
+qG1JqFC88SR9Prjp7n8oaBdopL+ZXOZvernLWonFIGvvodK57ZM
=DYkC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAmXgACgkQmmx57+YA
GNlR3g/+MjiqccCspohN8BRhsOTpDtq7NBM+F/oqwKzr9sktpwWeMz6dI1hjPihz
spyixzw10lcHdO3me1B8jOV2+Cek8zZzhDHK0tBXZU4AO+lNmgsjyxWs953TMcg8
eklBb3TpocHfGEuJSzPfTAD1B9QRB3Bl7kMztwE9uNKUCJiXCToIs63i/8QaCjIG
kNzJOCdndw07h4Ms+6MTlDLbpivFnedU43YyrtYGCovg5tlv02B8452KpbfHAIUf
MuuCAIYHm/ZAZa8aOfQ3ZsxwwXCYVu77uG14CTQKChOJeOZ9xzf5WFsRtY4EjJFW
bixwAQ9ZxFuFm8vXPz5vHkNh0nDGdHV2LJ7SVCoFZ/zcxXROH8+ol9/XtHsaShRh
C5+Ekz8GWvWnVCaeon53vzMXneVRoK6YvxtS1P87uuaM8IH3U8lktmHaJMlD/qdl
mGLyJs4GRt3tKdqlLB3FvUb1tWSLSZ84fuRHVb/FXY9M/driZYgGymH7axTWJtSE
m3rB2EMvbYWfdV69J8T0JSPmLwRY9lkJxSvnJulXB/J0yuvqHesrXoZHbiqxkZiM
adYT/ub6a03yRwoCFowTtOfBGyHOG7SLwrdHQ5dam0dCHjc0SGgJZj+gnHWh0asC
+/JMhePTxD1fH0UmElRHY1L1of6iWguWXTFgNZhHUxbCj/z+dSU=
=R9bG
-----END PGP SIGNATURE-----
Merge tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt
Devicetree changes for TI K3 platforms for v5.17 merge window:
* New Platforms:
- J721s2 SoC, SoM and Common Processor Board support
* New features:
- CAN support on AM64 EVM and SK
- TimeSync Router on AM64
* Fixes:
- Correct d-cache-sets info on J7200
- Fix L2 cache-sets value for J721e/J7200/AM64
- Fixes for dtbs_check warnings wrt serdes_ln_ctrl node on J721e/J7200
- Disable McASP on IoT2050 board to fix dtbs_check warnings
* tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arch: arm64: ti: Add support J721S2 Common Processor Board
arm64: dts: ti: Add initial support for J721S2 System on Module
arm64: dts: ti: Add initial support for J721S2 SoC
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
dt-bindings: arm: ti: Add bindings for J721s2 SoC
arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level
arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK
arm64: dts: ti: k3-am64-main: Add support for MCAN
arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes
arm64: dts: ti: k3-j721e: Add support for MCAN nodes
arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes
arm64: dts: ti: k3-am65-mcu: Add Support for MCAN
arm64: dts: ti: k3-am64-main: add timesync router node
arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
arm64: dts: ti: k3-j721e: Fix the L2 cache sets
arm64: dts: ti: k3-j7200: Fix the L2 cache sets
arm64: dts: ti: k3-am642: Fix the L2 cache sets
arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node
arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node
arm64: dts: ti: k3-j721e: correct cache-sets info
Link: https://lore.kernel.org/r/20211217172806.10023-2-vigneshr@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.
Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmG8sbwTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zob2pEACAt4T5USKGU6CR8Zv0A2drxxpPejhI
ph4KMl1+YPwlxP9knZlEKns1XXFc4XXX5CaQK9ndiYRvpOVpa95WPcReLZoi9veh
PBXgNAtryx+IePVkmQWqQ9R9Y7IZ8qOoVRxCgV9xwbRTEEQiwf9FdKQg8A4TV7i5
vq4LYurUV/b6PoXX5U7zlFnWfd5MU4K4ledWW9/6cGKW1vTjlZPiKian5NfGdgpX
sQGR6zXSpiRKgTJCB+CKU3s9aaHHENNfjrop6upEo/G2nETp4EdGCsQn8KguOtf5
KUcZzOxeUow99I25V1y0fFKkOfGWsSnOYUoEzoZ97H1kCIFCzeYChV7RJ0uxPsdK
jzUXh8xRl++Y/C/DfKnN/sIicqyVr1H9qyNZ00LCbCMWcYb3B8wwIjCOMG1YIJV7
5bhvmH0wVeNZYdwaynkfZUpKYsirz6IrMeWBsCb85zC5efuWS5oI/MB2JhezlH4A
AJR9ZZ5OgqYNvnm0khNtU1tzkeoEzzHK2E12PVcCztvACyhCArkCIS/ctyS4kLkL
BC/KWHuVb9SNIKXQYPv+mql5PHz5urcCaDSBZ2JM1D6pKZmp0MlEeR5IDsRF8MBJ
4qhFvBrGC0p4byvLi4doXnvzJKeZDHTaHOpfr0cmQlXiG6XgJioxFIW9LGb8e4fL
12152x5QFWoa5A==
=/fm0
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAl+0ACgkQmmx57+YA
GNn1KBAAkbKi5H+qUJYMwsKfoobIAs3x40vkm1k0QVei4fa/1NLbwb2lP4yS/Us3
jUQqaa5XtnMRXfeScpc/Nw6o80llgwVyxZbxbdJ+0ffkthLHoCryBPAVe5o45z8d
4ZtHKpJSe9APBjDYi1JKBWWq0dqR/o7BWgxasoqdZ/xs2WwufKt+4P7YMtSRVXfo
QyW4f4c2R5QX7ITfYZpNvMYgk6Bd1eoqZzwAUNoXP8urOUEOqse3/3V7ZbFAivCO
V8CPZDhDE3mcC0nM1RxlBmeBbLAWRpr+JLcasEfYJS82wet3C/9HQCwB2UUZ+MKQ
3I+Os6k6y8qZnfYHFeL5CiPW/oq2SWukykrFYKdLs0RwP13Ekaj5pR43xOj9IGTP
lVu1pcN1sZWxqT5Q3XyilEZTeaTt8bseScJuEm2fCrBrSX+H7ioOwlteM9UGfrzE
tDjIeZQcyTwT7/54cNQzhyuw1mF8G51YZqmXfTLb+wgblK8ZgyvlA9y1DzONpiDA
w08+TTc3X6r6zM1Sd06PSyRauiGwIO1kouEN22UewTmQmRmsrTX8OOm4lw8ZXbcX
xPwMHl60Np3dYYzNawFEkswKHwVPXyvmMtJGsn/zZtwdozT78k24nkKz1aClt+td
M1IyQjCWRdV052zBQ8EM+2iFfPbT9EfMKiIIPsZAxOVhpztpjv4=
=vtaC
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.17-rc1
The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.
Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.
* tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (47 commits)
arm64: tegra: Add host1x hotflush reset on Tegra210
arm64: tegra: Hook up MMC and BPMP to memory controller
arm64: tegra: Add memory controller on Tegra234
arm64: tegra: Add EMC general interrupt on Tegra194
arm64: tegra: Update SDMMC4 speeds for Tegra194
arm64: tegra: Add dma-coherent for Tegra194 VIC
arm64: tegra: Rename Ethernet PHY nodes
arm64: tegra: Remove unused only-1-8-v properties
arm64: tegra: Sort Tegra210 XUSB clocks correctly
arm64: tegra: Add missing TSEC properties on Tegra210
arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: Rename GPIO hog nodes to match schema
arm64: tegra: Remove unsupported regulator properties
arm64: tegra: Rename TCU node to "serial"
arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
arm64: tegra: Drop unused properties for Tegra194 PCIe
arm64: tegra: Fix Tegra194 HSP compatible string
arm64: tegra: Drop unsupported nvidia,lpdr property
...
Link: https://lore.kernel.org/r/20211217162253.1801077-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Remove the unneeded assignment of ret before returning it.
- Remove an unneeded blank line
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Add the gpio offsets for the SSD201 and SSD202D chips.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Add a compatible string for "ssd20xd" for the SigmaStar SSD201
and SSD202D chips. These chips are the same die with different
memory bonded so they don't need their own strings.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
1. Exynos ChipID: add Exynos7885 support.
2. Exynos PMU: add Exynos850 support.
3. Minor bindings cleanup.
4. Add Exynos USIv2 (Universal Serial Interface) driver. The USI block is
a shared IP block between I2C, UART/serial and SPI. Basically one has
to choose which feature the USI block will support and later the
regular I2C/serial/SPI driver will bind and work.
This merges also one commit with dt-binding headers from my dts64
pull request.
Together with a future serial driver change, this will break the ABI.
Affected: Serial on ExynosAutov9 SADK and out-of-tree ExynosAutov9 boards
Why: To properly and efficiently support the USI with new hierarchy
of USI-{serial,SPI,I2C} devicetree nodes.
Rationale:
Recently added serial and USI support was short-sighted and did not
allow to smooth support of other features (SPI and I2C). Adding
support for USI-SPI and USI-I2C would effect in code duplication.
Adding support for different USI versions (currently supported is
USIv2 but support for v1 is planned) would cause even more code
duplication and create a solution difficult to maintain.
Since USI-serial and ExynosAutov9 have been added recently, are
considered fresh development features and there are no supported
products using them, the code/solution is being refactored in
non-backwards compatible way. The compatibility is not broken yet.
It will be when serial driver changes are accepted.
The ABI break was discussed with only known users of ExynosAutov9 and
received their permission.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmHAa1EQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1+/HEACSadLl5gVkHa2IDfnG5q8b0rWK2/qLNsKR
YTLDB3XnLWMEZs7TMDqT6OtTKaQSJOlUAVKL5ZkZ9W0DNcG0mWcMdIPJ2HH8nv9Q
oVwJnOpDVFRal/zligg6JO1Rwly9ZFJryg5o1k3Ii979wzRf5v4Wu/d7PdVQ53VB
tmeL2tCE9Cf3LlnGi1Pnjcr9c/Jab62XFTXb/Hp62tXhtfCysVktaVLilTEnVP6D
VJm842bLVLLGYmerUe7XvnmL7cpN07VzCCXl8QtiXQ92Sgf4hSLmn7CcwyfkVl0O
vEhK8CrHgx4TenDUnF6DGec/64H+1f26BN0APbJWwoLX7jt595yZspmGhsHL6gmE
lLNnl0mey5ExuNJTlEXpt4DJNjElA7s6C6kizoFwtIsdJWpnxLM+TB9CuqG2rS0o
nRqEX1uIEYYIx4y3LK334Sctwnh0J90J40LrOzRNII2fwDa5THsckudgxCitUi+0
xeX8NelVCAZrrzVWydCrDim7cT/VHPE1BC97vcVcViFFFjJt1clwn+gajGz7ffrt
zm+XjubkaGWr81GivQK+axmZhg78229RjY2TYjFiDy7sPUnbDpT3JRxLv1Nh/xh8
7nrzZoy0sZTdJ4j4n1+UkykoOzWJ96GifqIlqZBPOIHhVC0zSgGQFrQ8hKF1fdWb
2BqdvGErUg==
=2Ed8
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAlD4ACgkQmmx57+YA
GNndpw//awblW/2vJ2hayxPCwQknzNXeEHn2jSQJ8j92Ep+Z90oyeiA7woPBepl2
QxgLJlNRt7GGbLEH3R0wpx0kg5w4ZroHG1dyUxPfF/EFfnHpuCLNuUFnj8Cl/fPw
14o2VLI7NBZFxK4pZYlrTX0QUWEnDET6G/LO3IL+/YelU8aBQZVBfb9Hvj9OnI1h
juIPrfwaUNbl37HwfQU5FftQYJnOcy0EBiSOaqPoYpyIHguxU1QZ5mZy5M0iytGV
HZFFYOfAs2l7kD+CVchtnGeIyWUinW7d4hRTS4qi4QP51pnaAefFnxHLKz9RwgMf
FCKZUax4/t7ifDu9b2sqiT8htToY8/xpoHyi2YjQTvyM3vOTi2OLWtWbLv4fnybi
L1MCAogcG/GCcTYECyGjSnfFV5c5CYIWEPqCJ50x4odj288OGSvtEZ2Q27j/HCvk
dlhrAQyL+fIWt+U7LM9FnJRSwgD1fplvtXncuVl7J3oA8uXYZg5tw6LIFBkxQTMG
Qypc5nxVtZK3Qz1Q59Q9zzZTE0amHr0m2uYGS6JOnIG6sbeApSLlxSW4+NMOLSMx
BOfSZa1etm1TBx3fI0O0HjUb4MOnUwDoWrUrV5MkJohFtqvAoQMQejtjt11+ffGn
SOTLAGE2VDTzCkAJs3gSLsESq6uB0wQFUiT68CyrR4ify61qZSs=
=pxdx
-----END PGP SIGNATURE-----
Merge tag 'samsung-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung SoC drivers changes for v5.17
1. Exynos ChipID: add Exynos7885 support.
2. Exynos PMU: add Exynos850 support.
3. Minor bindings cleanup.
4. Add Exynos USIv2 (Universal Serial Interface) driver. The USI block is
a shared IP block between I2C, UART/serial and SPI. Basically one has
to choose which feature the USI block will support and later the
regular I2C/serial/SPI driver will bind and work.
This merges also one commit with dt-binding headers from my dts64
pull request.
Together with a future serial driver change, this will break the ABI.
Affected: Serial on ExynosAutov9 SADK and out-of-tree ExynosAutov9 boards
Why: To properly and efficiently support the USI with new hierarchy
of USI-{serial,SPI,I2C} devicetree nodes.
Rationale:
Recently added serial and USI support was short-sighted and did not
allow to smooth support of other features (SPI and I2C). Adding
support for USI-SPI and USI-I2C would effect in code duplication.
Adding support for different USI versions (currently supported is
USIv2 but support for v1 is planned) would cause even more code
duplication and create a solution difficult to maintain.
Since USI-serial and ExynosAutov9 have been added recently, are
considered fresh development features and there are no supported
products using them, the code/solution is being refactored in
non-backwards compatible way. The compatibility is not broken yet.
It will be when serial driver changes are accepted.
The ABI break was discussed with only known users of ExynosAutov9 and
received their permission.
* tag 'samsung-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: soc: samsung: keep SoC driver bindings together
soc: samsung: Add USI driver
dt-bindings: soc: samsung: Add Exynos USI bindings
soc: samsung: exynos-pmu: Add Exynos850 support
dt-bindings: samsung: pmu: Document Exynos850
soc: samsung: exynos-chipid: add Exynos7885 SoC support
soc: samsung: exynos-chipid: describe which SoCs go with compatibles
Link: https://lore.kernel.org/r/20211220115405.30434-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver
to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add
i.MX8MN display related domain support.
- Add optional continuous burst clock support for imx-weim bus driver.
- Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in
gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and
MIX domain.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmG9dygUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7+jwgAle7/Po7Qs0JVrUwkJOWAjNxveXjv
keEC5o+svPOLIToX1lA+bY2CKlok2n6IIiEkpbgc+C+prTip0zJnJUFFHxuOeMkl
+/EWTthCAddLwXCdmU6c5HSw8XJ9rkH3YDvd46GkPnZuUiZVVmTYkuZQ25qCbPpE
f1kCg2RNVruZAOYHmMsoU+WMH3q40dvGSDVXbcHpNZ19qHooUyk/4jcXGlBJKXDo
iGosWLdqMy0vbK4cWFzorPFyTpaF1qq/o7AppfexT1h0f6aLnuKnBA5JXY4y4bvd
e+6EZ0VwvtdZBqMNaZLHqltCVA/Y0q2gXGryKUM6n7mGdv/LYictLHPudA==
=WKrF
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAjj4ACgkQmmx57+YA
GNlesQ/9HT8YKAUTsFRYbzKaK0tduZX9eFS8kIF6NlhTqD5IIYhwG4zZGhezRBdM
Xt1DztCKqI5/okIn5mtHa/nPOoXd8mElivqt+z/rNIvdB+QkeVbCAOQvHUXeNS1F
+sy8PTHLLGZNOGWGzKB4bFtJnc6yawwjz4EukG59cnC+AUePdo3DTT7Xnhf45j+j
SSYdG2wgcQ5OW9okKov+AcoupFosrC3Zcuswf2lPcxOfZY0x6yalXXfmerRUZR+g
JKTA3bFVLBG2o7nHcJp9ePh0K03+SfaaT5sSAbFm1DxL4hhtcPQJ2uq7I1kVBWKh
8gBAy5Q+dNNZI/OQxM5TGB3EiQ20qBEdkxDxW2bUwAuG+Qyazgv5gRp5doU7FQnP
Kl2f3TkM6/KRJNT3RytesTBSynisC9b4BuzpgFtfCBjK4/LEZSzSG07KHhP+k3pT
b0FWQlw9+Rvj/stChWZgVRC6G3ALi7NYf5NLrGhsKjEdrAYBHwoh8OniwI4NyqdK
14qWkPb9ctvh6J1IGQ7c2qG+iXSMc9oogG7dmb9Vas2RI/tMeEOJSWdmEY6TZbSP
40e3Wews2RlU+lT8291Kuq2Dyj0YbK7dZ38ymy9cVHKvixr5QUEHxkJzICcDPqPQ
rLdy/VwoSSDqkgNGcdXDdestnEXK7xvhgl/u3zT5RkcxfYxA3Q0=
=74GG
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.17:
- A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver
to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add
i.MX8MN display related domain support.
- Add optional continuous burst clock support for imx-weim bus driver.
- Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in
gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and
MIX domain.
* tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
bus: imx-weim: optionally enable continuous burst clock
soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active
soc: imx: gpcv2: Synchronously suspend MIX domains
Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* irq/misc-5.17:
: .
: Misc irqchip fixes:
:
: - Disable GICv4.1 RD's VPE table at boot time to avoid RAS errors
: - Fix Ingenic TCU's u32/unsigned long abuse
: - Some GICv2m constifying
: - Mark imx_gpcv2_instance as __ro_after_init
: - Enable a few missing IRQs on Spear
: - Conversion to platform_get_irq_optional() for the Renesas irqchips
: .
irqchip/renesas-intc-irqpin: Use platform_get_irq_optional() to get the interrupt
irqchip/renesas-irqc: Use platform_get_irq_optional() to get the interrupt
irqchip/gic-v4: Disable redistributors' view of the VPE table at boot time
irqchip/ingenic-tcu: Use correctly sized arguments for bit field
irqchip/gic-v2m: Add const to of_device_id
irqchip/imx-gpcv2: Mark imx_gpcv2_instance with __ro_after_init
irqchip/spear-shirq: Add support for IRQ 0..6
Signed-off-by: Marc Zyngier <maz@kernel.org>
The barrier is there for power_off rather than power_state.
Probably typo in commit 358b28f09f ("arm/arm64: KVM: Allow
a VCPU to fully reset itself").
Signed-off-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211208193257.667613-3-tabba@google.com
The comment for kvm_reset_vcpu() refers to the sysreg table as
being the table above, probably because of the code extracted at
commit f4672752c3 ("arm64: KVM: virtual CPU reset").
Fix the comment to remove the potentially confusing reference.
Signed-off-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211208193257.667613-2-tabba@google.com
Replace the hardcoded value with the existing definition.
No functional change intended.
Signed-off-by: Fuad Tabba <tabba@google.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211208192810.657360-1-tabba@google.com
When a trap 7 (Instruction access rights) occurs, this means the CPU
couldn't execute an instruction due to missing execute permissions on
the memory region. In this case it seems the CPU didn't even fetched
the instruction from memory and thus did not store it in the cr19 (IIR)
register before calling the trap handler. So, the trap handler will find
some random old stale value in cr19.
This patch simply overwrites the stale IIR value with a constant magic
"bad food" value (0xbaadf00d), in the hope people don't start to try to
understand the various random IIR values in trap 7 dumps.
Noticed-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
This set of changes contains some preparatory work that is shared by
several branches and trees to support DVFS via power domains.
There's also a bit of cleanup and improvements to reboot on chips that
use PSCI.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmG8sGYTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zocR8EACMoED5WAU1C+No9Bd9c7h2iru4LhUg
wnobzGX0ZOPn/O3873rBqIiZDrJoVDJvqbh761pt35BigqJrAcegQaoMgBsvTl11
SAg6EpaQ2a/O7bPRj7V58XjxjlhoK+638PAuk7mzIDPibpnfZaNdJgI59/BEVVCd
BQ7452z3LnPh9cFzCeqCMhvoJ2kTNgJvjGZ/EfOJE+tocwT+Fx83zzfM1kyflRr3
2yBJwSi3k/D5KK38OT+uPvHqduqsci/aTel2AlLtNvFJ2iPg7ax3G6ak2MHgq/ac
noYL1kIiCBx3QQ3npiBKGnq2D1JBzX2mbbJxZrcGYZDW3D+2z1xPPtGNGCPiRMYQ
DSnR3AoRegKQZn6Jy+b44kLn0NhrI58qR/PXCzpggl+yCnIAAaBObr+bSYYxlr/u
sO189kVg1IYIILime9a5nxUvYalWSgXB/sUqQXjfJIMsDAHYmws3QqNw7Z628wxx
2ddWSKGrjkq+n3z0uR8xiQTdTGqeagYK+2yE4aVTfv65lsjBIlU75FhgsJUaGpBL
5Y2sSGB6ysPdxtoH0ol+vckZq3tSyZbqgoty5dOOHoEm+YeBSyXjaZwYTaLYIgd+
cUNKEsOBul1ZbT/ca2pEt+yTrKGrYgI7maa5ocwEYrvp4QFkHcNts5UmEwp+22pQ
8JqmzeJH92E4LA==
=f+T3
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHAh0oACgkQmmx57+YA
GNkwHhAAo+oITzjXFoHwCw97u6xOv9CxH6OFRSz2kbxBGHtniGx/lg7cxTIif4HX
4bnvUv3nQqoRMJ2hlGXp0QCjfXVTJXnk3Nduf74aEN2fkclFuR/PBOl4py0imubs
9ZVXpSSB4VSpXrtujAnlhO4nEEiFR0rXSTcJbUz3hqjVgatRm9pAGZmU0u5x/K0M
idM46H+dDInWb53n/eJaj+GHoAJ18+yH62ck1OJqGSitaAfalGMFKRFHIqu8K95q
ifadcrbFJo0711KKPRwgQPVgB1j7zFOjkaHDR7CjrsToRSVWbFwCgC6+nVg5X74h
/wjvKq61pNvK7HavYIXWeUCzDqGbH404OjaksIYSw2Te2mJTOA0qOqh0edi6w6Y2
kVUcnqM5zt/TYaXsZdlxX1lTItAOQiV0yEuq/zPYBJ0ecgvhKOR0GHUseVsfVPrz
NxEZGEAgkSrHbSITd1arPgOuvL9FwlqsmWi6ZV6n+o/hiYlz9G2YoHK2tcaKd8wX
FqmgtKOPnoYg3h+7PoSahNLWEbEZEt8v6w6ezERm9U+ntl/sYISk1OCwwHCyqpfP
hA7J9GlK3f2aYmE0eT828bov1PIFudpdgL0HFadEAKdpfn3G0kYf0wQ2UZ6J+XrW
ZbcWhPzSTjKIDLWyrbRYu5Zo7I8uBVAA/eFopMRGbbn27ZgjrsM=
=gToI
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.17-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.17-rc1
This set of changes contains some preparatory work that is shared by
several branches and trees to support DVFS via power domains.
There's also a bit of cleanup and improvements to reboot on chips that
use PSCI.
* tag 'tegra-for-5.17-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Rename core power domain
soc/tegra: pmc: Rename 3d power domains
soc/tegra: regulators: Prepare for suspend
soc/tegra: fuse: Use resource-managed helpers
soc/tegra: fuse: Reset hardware
soc/tegra: pmc: Add reboot notifier
soc/tegra: Don't print error message when OPPs not available
Link: https://lore.kernel.org/r/20211217162253.1801077-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a selftest to attempt to enter L2 with invalid guests state by
exiting to userspace via I/O from L2, and then using KVM_SET_SREGS to set
invalid guest state (marking TR unusable is arbitrary chosen for its
relative simplicity).
This is a regression test for a bug introduced by commit c8607e4a08
("KVM: x86: nVMX: don't fail nested VM entry on invalid guest state if
!from_vmentry"), which incorrectly set vmx->fail=true when L2 had invalid
guest state and ultimately triggered a WARN due to nested_vmx_vmexit()
seeing vmx->fail==true while attempting to synthesize a nested VM-Exit.
The is also a functional test to verify that KVM sythesizes TRIPLE_FAULT
for L2, which is somewhat arbitrary behavior, instead of emulating L2.
KVM should never emulate L2 due to invalid guest state, as it's
architecturally impossible for L1 to run an L2 guest with invalid state
as nested VM-Enter should always fail, i.e. L1 needs to do the emulation.
Stuffing state via KVM ioctl() is a non-architctural, out-of-band case,
hence the TRIPLE_FAULT being rather arbitrary.
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20211207193006.120997-5-seanjc@google.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Update the documentation for kvm-intel's emulate_invalid_guest_state to
rectify the description of KVM's default behavior, and to document that
the behavior and thus parameter only applies to L1.
Fixes: a27685c33a ("KVM: VMX: Emulate invalid guest state by default")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20211207193006.120997-4-seanjc@google.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Synthesize a triple fault if L2 guest state is invalid at the time of
VM-Enter, which can happen if L1 modifies SMRAM or if userspace stuffs
guest state via ioctls(), e.g. KVM_SET_SREGS. KVM should never emulate
invalid guest state, since from L1's perspective, it's architecturally
impossible for L2 to have invalid state while L2 is running in hardware.
E.g. attempts to set CR0 or CR4 to unsupported values will either VM-Exit
or #GP.
Modifying vCPU state via RSM+SMRAM and ioctl() are the only paths that
can trigger this scenario, as nested VM-Enter correctly rejects any
attempt to enter L2 with invalid state.
RSM is a straightforward case as (a) KVM follows AMD's SMRAM layout and
behavior, and (b) Intel's SDM states that loading reserved CR0/CR4 bits
via RSM results in shutdown, i.e. there is precedent for KVM's behavior.
Following AMD's SMRAM layout is important as AMD's layout saves/restores
the descriptor cache information, including CS.RPL and SS.RPL, and also
defines all the fields relevant to invalid guest state as read-only, i.e.
so long as the vCPU had valid state before the SMI, which is guaranteed
for L2, RSM will generate valid state unless SMRAM was modified. Intel's
layout saves/restores only the selector, which means that scenarios where
the selector and cached RPL don't match, e.g. conforming code segments,
would yield invalid guest state. Intel CPUs fudge around this issued by
stuffing SS.RPL and CS.RPL on RSM. Per Intel's SDM on the "Default
Treatment of RSM", paraphrasing for brevity:
IF internal storage indicates that the [CPU was post-VMXON]
THEN
enter VMX operation (root or non-root);
restore VMX-critical state as defined in Section 34.14.1;
set to their fixed values any bits in CR0 and CR4 whose values must
be fixed in VMX operation [unless coming from an unrestricted guest];
IF RFLAGS.VM = 0 AND (in VMX root operation OR the
“unrestricted guest” VM-execution control is 0)
THEN
CS.RPL := SS.DPL;
SS.RPL := SS.DPL;
FI;
restore current VMCS pointer;
FI;
Note that Intel CPUs also overwrite the fixed CR0/CR4 bits, whereas KVM
will sythesize TRIPLE_FAULT in this scenario. KVM's behavior is allowed
as both Intel and AMD define CR0/CR4 SMRAM fields as read-only, i.e. the
only way for CR0 and/or CR4 to have illegal values is if they were
modified by the L1 SMM handler, and Intel's SDM "SMRAM State Save Map"
section states "modifying these registers will result in unpredictable
behavior".
KVM's ioctl() behavior is less straightforward. Because KVM allows
ioctls() to be executed in any order, rejecting an ioctl() if it would
result in invalid L2 guest state is not an option as KVM cannot know if
a future ioctl() would resolve the invalid state, e.g. KVM_SET_SREGS, or
drop the vCPU out of L2, e.g. KVM_SET_NESTED_STATE. Ideally, KVM would
reject KVM_RUN if L2 contained invalid guest state, but that carries the
risk of a false positive, e.g. if RSM loaded invalid guest state and KVM
exited to userspace. Setting a flag/request to detect such a scenario is
undesirable because (a) it's extremely unlikely to add value to KVM as a
whole, and (b) KVM would need to consider ioctl() interactions with such
a flag, e.g. if userspace migrated the vCPU while the flag were set.
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20211207193006.120997-3-seanjc@google.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Revert a relatively recent change that set vmx->fail if the vCPU is in L2
and emulation_required is true, as that behavior is completely bogus.
Setting vmx->fail and synthesizing a VM-Exit is contradictory and wrong:
(a) it's impossible to have both a VM-Fail and VM-Exit
(b) vmcs.EXIT_REASON is not modified on VM-Fail
(c) emulation_required refers to guest state and guest state checks are
always VM-Exits, not VM-Fails.
For KVM specifically, emulation_required is handled before nested exits
in __vmx_handle_exit(), thus setting vmx->fail has no immediate effect,
i.e. KVM calls into handle_invalid_guest_state() and vmx->fail is ignored.
Setting vmx->fail can ultimately result in a WARN in nested_vmx_vmexit()
firing when tearing down the VM as KVM never expects vmx->fail to be set
when L2 is active, KVM always reflects those errors into L1.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 21158 at arch/x86/kvm/vmx/nested.c:4548
nested_vmx_vmexit+0x16bd/0x17e0
arch/x86/kvm/vmx/nested.c:4547
Modules linked in:
CPU: 0 PID: 21158 Comm: syz-executor.1 Not tainted 5.16.0-rc3-syzkaller #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
RIP: 0010:nested_vmx_vmexit+0x16bd/0x17e0 arch/x86/kvm/vmx/nested.c:4547
Code: <0f> 0b e9 2e f8 ff ff e8 57 b3 5d 00 0f 0b e9 00 f1 ff ff 89 e9 80
Call Trace:
vmx_leave_nested arch/x86/kvm/vmx/nested.c:6220 [inline]
nested_vmx_free_vcpu+0x83/0xc0 arch/x86/kvm/vmx/nested.c:330
vmx_free_vcpu+0x11f/0x2a0 arch/x86/kvm/vmx/vmx.c:6799
kvm_arch_vcpu_destroy+0x6b/0x240 arch/x86/kvm/x86.c:10989
kvm_vcpu_destroy+0x29/0x90 arch/x86/kvm/../../../virt/kvm/kvm_main.c:441
kvm_free_vcpus arch/x86/kvm/x86.c:11426 [inline]
kvm_arch_destroy_vm+0x3ef/0x6b0 arch/x86/kvm/x86.c:11545
kvm_destroy_vm arch/x86/kvm/../../../virt/kvm/kvm_main.c:1189 [inline]
kvm_put_kvm+0x751/0xe40 arch/x86/kvm/../../../virt/kvm/kvm_main.c:1220
kvm_vcpu_release+0x53/0x60 arch/x86/kvm/../../../virt/kvm/kvm_main.c:3489
__fput+0x3fc/0x870 fs/file_table.c:280
task_work_run+0x146/0x1c0 kernel/task_work.c:164
exit_task_work include/linux/task_work.h:32 [inline]
do_exit+0x705/0x24f0 kernel/exit.c:832
do_group_exit+0x168/0x2d0 kernel/exit.c:929
get_signal+0x1740/0x2120 kernel/signal.c:2852
arch_do_signal_or_restart+0x9c/0x730 arch/x86/kernel/signal.c:868
handle_signal_work kernel/entry/common.c:148 [inline]
exit_to_user_mode_loop kernel/entry/common.c:172 [inline]
exit_to_user_mode_prepare+0x191/0x220 kernel/entry/common.c:207
__syscall_exit_to_user_mode_work kernel/entry/common.c:289 [inline]
syscall_exit_to_user_mode+0x2e/0x70 kernel/entry/common.c:300
do_syscall_64+0x53/0xd0 arch/x86/entry/common.c:86
entry_SYSCALL_64_after_hwframe+0x44/0xae
Fixes: c8607e4a08 ("KVM: x86: nVMX: don't fail nested VM entry on invalid guest state if !from_vmentry")
Reported-by: syzbot+f1d2136db9c80d4733e8@syzkaller.appspotmail.com
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20211207193006.120997-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Attempting to compile on a non-x86 architecture fails with
include/kvm_util.h: In function ‘vm_compute_max_gfn’:
include/kvm_util.h:79:21: error: dereferencing pointer to incomplete type ‘struct kvm_vm’
return ((1ULL << vm->pa_bits) >> vm->page_shift) - 1;
^~
This is because the declaration of struct kvm_vm is in
lib/kvm_util_internal.h as an effort to make it private to
the test lib code. We can still provide arch specific functions,
though, by making the generic function symbols weak. Do that to
fix the compile error.
Fixes: c8cc43c1ea ("selftests: KVM: avoid failures due to reserved HyperTransport region")
Cc: stable@vger.kernel.org
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-Id: <20211214151842.848314-1-drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The kvm_run struct's if_flag is a part of the userspace/kernel API. The
SEV-ES patches failed to set this flag because it's no longer needed by
QEMU (according to the comment in the source code). However, other
hypervisors may make use of this flag. Therefore, set the flag for
guests with encrypted registers (i.e., with guest_state_protected set).
Fixes: f1c6366e30 ("KVM: SVM: Add required changes to support intercepts under SEV-ES")
Signed-off-by: Marc Orr <marcorr@google.com>
Message-Id: <20211209155257.128747-1-marcorr@google.com>
Cc: stable@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
After dropping mmu_lock in the TDP MMU, restart the iterator during
tdp_iter_next() and do not advance the iterator. Advancing the iterator
results in skipping the top-level SPTE and all its children, which is
fatal if any of the skipped SPTEs were not visited before yielding.
When zapping all SPTEs, i.e. when min_level == root_level, restarting the
iter and then invoking tdp_iter_next() is always fatal if the current gfn
has as a valid SPTE, as advancing the iterator results in try_step_side()
skipping the current gfn, which wasn't visited before yielding.
Sprinkle WARNs on iter->yielded being true in various helpers that are
often used in conjunction with yielding, and tag the helper with
__must_check to reduce the probabily of improper usage.
Failing to zap a top-level SPTE manifests in one of two ways. If a valid
SPTE is skipped by both kvm_tdp_mmu_zap_all() and kvm_tdp_mmu_put_root(),
the shadow page will be leaked and KVM will WARN accordingly.
WARNING: CPU: 1 PID: 3509 at arch/x86/kvm/mmu/tdp_mmu.c:46 [kvm]
RIP: 0010:kvm_mmu_uninit_tdp_mmu+0x3e/0x50 [kvm]
Call Trace:
<TASK>
kvm_arch_destroy_vm+0x130/0x1b0 [kvm]
kvm_destroy_vm+0x162/0x2a0 [kvm]
kvm_vcpu_release+0x34/0x60 [kvm]
__fput+0x82/0x240
task_work_run+0x5c/0x90
do_exit+0x364/0xa10
? futex_unqueue+0x38/0x60
do_group_exit+0x33/0xa0
get_signal+0x155/0x850
arch_do_signal_or_restart+0xed/0x750
exit_to_user_mode_prepare+0xc5/0x120
syscall_exit_to_user_mode+0x1d/0x40
do_syscall_64+0x48/0xc0
entry_SYSCALL_64_after_hwframe+0x44/0xae
If kvm_tdp_mmu_zap_all() skips a gfn/SPTE but that SPTE is then zapped by
kvm_tdp_mmu_put_root(), KVM triggers a use-after-free in the form of
marking a struct page as dirty/accessed after it has been put back on the
free list. This directly triggers a WARN due to encountering a page with
page_count() == 0, but it can also lead to data corruption and additional
errors in the kernel.
WARNING: CPU: 7 PID: 1995658 at arch/x86/kvm/../../../virt/kvm/kvm_main.c:171
RIP: 0010:kvm_is_zone_device_pfn.part.0+0x9e/0xd0 [kvm]
Call Trace:
<TASK>
kvm_set_pfn_dirty+0x120/0x1d0 [kvm]
__handle_changed_spte+0x92e/0xca0 [kvm]
__handle_changed_spte+0x63c/0xca0 [kvm]
__handle_changed_spte+0x63c/0xca0 [kvm]
__handle_changed_spte+0x63c/0xca0 [kvm]
zap_gfn_range+0x549/0x620 [kvm]
kvm_tdp_mmu_put_root+0x1b6/0x270 [kvm]
mmu_free_root_page+0x219/0x2c0 [kvm]
kvm_mmu_free_roots+0x1b4/0x4e0 [kvm]
kvm_mmu_unload+0x1c/0xa0 [kvm]
kvm_arch_destroy_vm+0x1f2/0x5c0 [kvm]
kvm_put_kvm+0x3b1/0x8b0 [kvm]
kvm_vcpu_release+0x4e/0x70 [kvm]
__fput+0x1f7/0x8c0
task_work_run+0xf8/0x1a0
do_exit+0x97b/0x2230
do_group_exit+0xda/0x2a0
get_signal+0x3be/0x1e50
arch_do_signal_or_restart+0x244/0x17f0
exit_to_user_mode_prepare+0xcb/0x120
syscall_exit_to_user_mode+0x1d/0x40
do_syscall_64+0x4d/0x90
entry_SYSCALL_64_after_hwframe+0x44/0xae
Note, the underlying bug existed even before commit 1af4a96025 ("KVM:
x86/mmu: Yield in TDU MMU iter even if no SPTES changed") moved calls to
tdp_mmu_iter_cond_resched() to the beginning of loops, as KVM could still
incorrectly advance past a top-level entry when yielding on a lower-level
entry. But with respect to leaking shadow pages, the bug was introduced
by yielding before processing the current gfn.
Alternatively, tdp_mmu_iter_cond_resched() could simply fall through, or
callers could jump to their "retry" label. The downside of that approach
is that tdp_mmu_iter_cond_resched() _must_ be called before anything else
in the loop, and there's no easy way to enfornce that requirement.
Ideally, KVM would handling the cond_resched() fully within the iterator
macro (the code is actually quite clean) and avoid this entire class of
bugs, but that is extremely difficult do while also supporting yielding
after tdp_mmu_set_spte_atomic() fails. Yielding after failing to set a
SPTE is very desirable as the "owner" of the REMOVED_SPTE isn't strictly
bounded, e.g. if it's zapping a high-level shadow page, the REMOVED_SPTE
may block operations on the SPTE for a significant amount of time.
Fixes: faaf05b00a ("kvm: x86/mmu: Support zapping SPTEs in the TDP MMU")
Fixes: 1af4a96025 ("KVM: x86/mmu: Yield in TDU MMU iter even if no SPTES changed")
Reported-by: Ignat Korchagin <ignat@cloudflare.com>
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20211214033528.123268-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Some users of iova.h still expect that dma-mapping.h is also included.
Re-add the include until these users are updated to fix compile
failures in the iommu tree.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/20211220123448.19996-1-joro@8bytes.org
Signed-off-by: Joerg Roedel <jroedel@suse.de>
