Add binding for the Google Spherion board, which is used for Acer
Chromebook 514 (CB514-2H).
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220629155956.1138955-2-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Group devices like Chip ID or SoC information under "hwinfo" directory.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220705155038.454251-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Update the PRUSS bindings for the PRUSSM instance present in
AM625 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220602120613.2175-3-kishon@ti.com
Re-arrange "compatible" string in alphabetic order to decrease the
chance of conflicts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220602120613.2175-2-kishon@ti.com
Add bindings for the Qualcomm Bandwidth Monitor device providing
performance data on interconnects. The bindings describe only BWMON CPU
(version 4), e.g. the instance which appeared for the first on Qualcomm
MSM8998 SoC and is also used on SDM845. This BWMON device sits between
CPU and Last Level Cache Controller.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220704121730.127925-2-krzysztof.kozlowski@linaro.org
The change adds device tree bindings for camera clock controller
found on SM8450 SoC.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062622.2757831-2-vladimir.zapolskiy@linaro.org
Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250
bindings. Update the documentation with the new compatible.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-4-robert.foss@linaro.org
The conditional block for variants with a second clock should have set
minItems, not maxItems, which was already 2. Since clock-names requires
two items, this typo should not have caused any problems.
Fixes: edd14218bd ("dt-bindings: dmaengine: Convert Allwinner A31 and A64 DMA to a schema")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220702031903.21703-1-samuel@sholland.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
ExynosAutov9 gained a reboot-mode node, so document the property to fix
warning:
exynosautov9-sadk.dtb: system-controller@10460000: 'reboot-mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220706160257.27579-3-krzysztof.kozlowski@linaro.org
Preferred coding for referencing other schemas is to use absolute path.
Quotes over path are also not needed.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220706160257.27579-2-krzysztof.kozlowski@linaro.org
Compatibles can come in two formats. Either "vendor,ip-soc" or
"vendor,soc-ip". Add a DT schema documenting preferred policy and
enforcing it for all new compatibles, except few existing patterns. The
schema also disallows wild-cards used in SoC compatibles.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220705161340.493474-1-krzysztof.kozlowski@linaro.org
The main additions this time around are:
1. The capability to trace full SCMI message headers and payloads.
The recent unearthing of chain of old firmware issues motivated
this effort so that it is easier to trace them and debug quicker
than it took this time around in absence of such tracing.
2. SCMI System power control driver to handle platform's requests for a
graceful shutdown. Though the system power control protocol has been
around since the begining of SCMI, it lacked the timeout information
that was added in SCMI v3.1 that enables kernel to take appropriate
action within the timeout and doesn't have to rely on any other
user inputs(which was blocking factor for addition of this driver
earlier)
3. Support for SCMI Power Capping protocol that was introduced in SCMI v3.1
This protocol is intended for controlling and monitoring the power
consumption of power capping domains. The firmware also provides the
hierarchy of powercap domains by providing parent domain information.
It also contains a bug fix in the old SCPI driver addressing possible
user-after-free issues.
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Merge tag 'scmi-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
Arm SCMI updates for v5.20
The main additions this time around are:
1. The capability to trace full SCMI message headers and payloads.
The recent unearthing of chain of old firmware issues motivated
this effort so that it is easier to trace them and debug quicker
than it took this time around in absence of such tracing.
2. SCMI System power control driver to handle platform's requests for a
graceful shutdown. Though the system power control protocol has been
around since the begining of SCMI, it lacked the timeout information
that was added in SCMI v3.1 that enables kernel to take appropriate
action within the timeout and doesn't have to rely on any other
user inputs(which was blocking factor for addition of this driver
earlier)
3. Support for SCMI Power Capping protocol that was introduced in SCMI v3.1
This protocol is intended for controlling and monitoring the power
consumption of power capping domains. The firmware also provides the
hierarchy of powercap domains by providing parent domain information.
It also contains a bug fix in the old SCPI driver addressing possible
user-after-free issues.
* tag 'scmi-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: Use fast channel tracing
include: trace: Add SCMI fast channel tracing
firmware: arm_scmi: Add SCMI v3.1 powercap fast channels support
firmware: arm_scmi: Generalize the fast channel support
firmware: arm_scmi: Add SCMI v3.1 powercap protocol basic support
dt-bindings: firmware: arm,scmi: Add support for powercap protocol
firmware: arm_scmi: Add SCMI System Power Control driver
firmware: arm_scmi: Add devm_protocol_acquire helper
firmware: arm_scmi: Add SCMI v3.1 System Power extensions
firmware: arm_scmi: Support only one single system power device
firmware: arm_scmi: Use new SCMI full message tracing
include: trace: Add SCMI full message tracing
firmware: arm_scpi: Ensure scpi_info is not assigned if the probe fails
firmware: arm_scmi: Remove usage of the deprecated ida_simple_xxx API
firmware: arm_scmi: Fix response size warning for OPTEE transport
firmware: arm_scmi: Relax CLOCK_DESCRIBE_RATES out-of-spec checks
Link: https://lore.kernel.org/r/20220706115045.2272678-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
with reality
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Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for v5.20
It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
with reality
* tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: lan966x: Add UDPHS support
dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
ARM: dts: lan966x: Add mcan1 node.
ARM: dts: at91: sama7g5: add reset-controller node
ARM: dts: at91: use generic name for reset controller
ARM: dts: at91: sama5d2: fix compilation warning
ARM: dts: at91: sama5d2: fix compilation warning
Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
on rk356x in general plus necessary board-specific changes on Rock-3A,
Quartz64-A, rk3568-evb, BPI-R2-Pro.
A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and
PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number
of additional peripherals to this board (sfc node, sdr-104 support, fan).
And finally touch panel support for rockpro64 and some misc dt cleanups
(node names for dtschema and styling).
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Merge tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the Radxa Rock Pi S, enablement of graphics support and hdmi-audio
on rk356x in general plus necessary board-specific changes on Rock-3A,
Quartz64-A, rk3568-evb, BPI-R2-Pro.
A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and
PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number
of additional peripherals to this board (sfc node, sdr-104 support, fan).
And finally touch panel support for rockpro64 and some misc dt cleanups
(node names for dtschema and styling).
* tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
arm64: dts: rockchip: enable hdmi tx audio on rock-3a
arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10
arm64: dts: rockchip: align gpio-key node names with dtschema
arm64: dts: rockchip: rock-pi-s add more peripherals
arm64: dts: rockchip: add ROCK Pi S DTS support
dt-bindings: arm: rockchip: Add Radxa ROCK Pi S
arm64: dts: rockchip: Add missing space around regulator-name on rk3368-orion-r68
arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
arm64: dts: rockchip: configure thermal shutdown for BPI-R2-Pro
arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
arm64: dts: rockchip: enable vop2 and hdmi tx on BPI-R2-Pro
arm64: dts: rockchip: set display regulators to always-on on BPI-R2-Pro
arm64: dts: rockchip: add RTC to BPI-R2 Pro
arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
arm64: dts: rockchip: Add HDMI audio nodes to rk356x
arm64: dts: rockchip: adjust whitespace around '='
arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a
arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
arm64: dts: rockchip: rk356x: Add HDMI nodes
...
Link: https://lore.kernel.org/r/40088956.J2Yia2DhmK@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Allwinner D1 contains USB controllers which claim to be compatible
with the OHCI specification version 1.0a.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702195249.54160-4-samuel@sholland.org
The Allwinner D1 contains USB controllers which claim to be compatible
with the EHCI specification version 1.0.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702195249.54160-3-samuel@sholland.org
The MUSB controller in the Allwinner D1 has 10 endpoints, making it
compatible with the A33 variant of the hardware.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702195249.54160-2-samuel@sholland.org
V536 and newer Allwinner SoCs contain an updated I2C controller which
includes an offload engine for master mode. The controller retains the
existing register interface, so the A31 compatible still applies.
Add the V536 compatible and use it as a fallback for other SoCs with the
updated hardware. This includes two SoCs that were already documented
(H616 and A100) and two new SoCs (R329 and D1).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702052544.31443-1-samuel@sholland.org
Add samsung,exynosautov9-usi dedicated compatible for representing USI
of Exynos Auto v9 SoC.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220701015226.32781-2-chanho61.park@samsung.com
Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact
carrier board into YAML DT binding document. This system is a general purpose
DIN Rail Controller design.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The USB device controller available in the Microchip LAN9662 SOC
is the same IP as the one present in the SAMA5D3 SOC.
Add the LAN9662 compatible string and set the SAMA5D3 compatible
string as a fallback for the LAN9662.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-3-herve.codina@bootlin.com
Like for stm32mp15, when stm32 RCC node is used to interact with a secure
context (using clock SCMI protocol), a different path has to be used for
yaml verification.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
When adding the bindings for the D1 display engine, I missed the
condition for the number of pipelines. D1 has two mixers, so it
will have two pipeline references.
Fixes: ae5a5d26c1 ("dt-bindings: display: Add D1 display engine compatibles")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702032921.22433-1-samuel@sholland.org
During the conversion the bindings lost list of required properties.
Fixes: c58db2abb1 ("spi: convert Xilinx Zynq UltraScale+ MPSoC GQSPI bindings to YAML")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220704130618.199231-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
During the conversion the bindings lost list of required properties.
Fixes: aa7968682a ("spi: convert Cadence SPI bindings to YAML")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220704130618.199231-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Document Xiaomi Mi 5s Plus (xiaomi-natrium) smartphone which is based on
Snapdragon 821 SoC.
Signed-off-by: Alec Su <ae40515@yahoo.com.tw>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220606024706.22861-2-ae40515@yahoo.com.tw
The RISC-V PLIC specification unfortunately allows PLIC implementations
to ignore edges seen while an edge-triggered interrupt is being handled:
Depending on the design of the device and the interrupt handler,
in between sending an interrupt request and receiving notice of its
handler’s completion, the gateway might either ignore additional
matching edges or increment a counter of pending interrupts.
Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus
it also needs to inform software about each interrupt's trigger type, so
the driver can use the right interrupt flow.
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-4-samuel@sholland.org
Renesas RZ/Five (R9A07G043) SoC is equipped with NCEPLIC100 RISC-V
platform level interrupt controller from Andes Technology. NCEPLIC100
ignores subsequent EDGE interrupts until the previous EDGE interrupt is
completed, due to this issue we have to follow different interrupt flow
for EDGE and LEVEL interrupts.
This patch documents Renesas RZ/Five (R9A07G043) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-2-samuel@sholland.org
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
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Merge tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.20
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
* tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add internal eMMC support to jackpotlte
dt-bindings: clock: Add indices for Exynos7885 TREX clocks
dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS
arm64: dts: exynos: enable secondary ufs devices ExynosAutov9 SADK
arm64: dts: exynos: add secondary ufs devices in ExynosAutov9
arm64: dts: fsd: use local header for pinctrl register values
arm64: dts: exynos: use local header for pinctrl register values
arm64: dts: exynos: align MMC node name with dtschema
arm64: dts: exynos: adjust DT style of ufs nodes in ExynosAutov9
arm64: dts: exynos: adjust whitespace around '='
arm64: dts: fsd: add ufs device node
arm64: dts: exynos: add watchdog in ExynosAutov9
arm64: dts: exynos: add syscon reboot/reboot_mode support in ExynosAutov9
dt-bindings: soc: add samsung,boot-mode definitions
arm64: dts: fsd: Add cpu cache information
Link: https://lore.kernel.org/r/20220624080746.31947-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the
Canaan k210 is wired up for a width of 4.
Quoting Serge:
The modern DW APB SSI controllers of v.4.* and newer also support the
enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core
version is auto-detected at run-time there is no way to create a
DT-schema correctly constraining the Rx/Tx SPI bus widths.
/endquote
As such, drop the restriction on only supporting a bus width of 1.
Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Niklas Cassel <niklas.cassel@wdc.com>
Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie
Signed-off-by: Mark Brown <broonie@kernel.org>
The core schema already sets a 'ref' for properties ending with 'names'.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220517070113.18023-2-krzysztof.kozlowski@linaro.org
Add the CRD (Compute Reference Design?) and the Lenovo Thinkpad X13s to
the valid device compatibles found on the sc8280xp platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220629041438.1352536-2-bjorn.andersson@linaro.org
Merge series from Stephan Gerhold <stephan.gerhold@kernkonzept.com>:
Fix the voltage range for the pm8916_pldo in the qcom_smd-regulator
driver and add definitions for the regulators available in PM8909.
Document the "qcom,rpm-pm8909-regulators" compatible for describing
the regulators available in the PM8909 PMIC (controlled via the RPM
firmware).
PM8909 is very similar to the existing PM8916 but lacks 3 of the
regulators (s3, s4 and l16).
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220623094614.1410180-3-stephan.gerhold@kernkonzept.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This MII converter can be found on the RZ/N1 processor family. The MII
converter ports are declared as subnodes which are then referenced by
users of the PCS driver such as the switch.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/20220624144001.95518-5-clement.leger@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Define "samsung,exynosautov9-spi" for Exynos Auto v9's spi.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andi Shyti <andi@etezian.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20220629102304.65712-4-chanho61.park@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org>
