In preparation for enabling the stackleak plugin on arm64,
we need a way to get the bounds of the current stack. Extend
on_accessible_stack to get this information.
Acked-by: Alexander Popov <alex.popov@linux.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
[will: folded in fix for allmodconfig build breakage w/ sdei]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Trivial fix to spelling mistake in usbg_us_strings array
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
When PRI queue occurs overflow, driver should update the OVACKFLG to
the PRIQ consumer register, otherwise subsequent PRI requests will not
be processed.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Miao Zhong <zhongmiao@hisilicon.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Currently we check if the number of context banks is not equal to
num_context_interrupts. However, there are booloaders such as, one
on sdm845 that reserves few context banks and thus kernel views
less than the total available context banks.
So, although the hardware definition in device tree would mention
the correct number of context interrupts, this number can be
greater than the number of context banks visible to smmu in kernel.
We should therefore error out only when the number of context banks
is greater than the available number of context interrupts.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Suggested-by: Tomasz Figa <tfiga@chromium.org>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[will: drop useless printk]
Signed-off-by: Will Deacon <will.deacon@arm.com>
When run on a 64-bit system in selftest, the v7s driver may obtain page
table with physical addresses larger than 32-bit. Level-2 tables are 1KB
and are are allocated with slab, which doesn't accept the GFP_DMA32
flag. Currently map() truncates the address written in the PTE, causing
iova_to_phys() or unmap() to access invalid memory. Kasan reports it as
a use-after-free. To avoid any nasty surprise, test if the physical
address fits in a PTE before returning a new table. 32-bit systems,
which are the main users of this page table format, shouldn't see any
difference.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Commit 4b123757ee ("iommu/io-pgtable-arm: Make allocations
NUMA-aware") added a NUMA hint to page table allocation, but the pgtable
selftest doesn't provide an SMMU device parameter. Since dev_to_node
doesn't accept a NULL argument, add a special case for selftest.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The trace module parameter controls output of debugging messages in the
UVC function driver. Move it from the webcam module to the UVC function
module where it belongs. This allows ConfigFS-based UVC gadgets to
control tracing.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
In order to speed up compilation, only include the headers that are
strictly required within other headers. To that end, use forward
structure declaration and move #include statements to .c file as
appropriate.
While at it, sort headers alphabetically, and remove unneeded __KERNEL__
guards.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The UVC gadget userspace API (V4L2 events and custom ioctls) is defined
in a header internal to the kernel. Move it to a new public header to
make it accessible to userspace.
The UVC_INTF_CONTROL and UVC_INTF_STREAMING macros are not used, so
remove them in the process.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The smallest rb size supported today is 4k rx buffers.
22560 devices use 2k rxb's, so allow using 2k buffers.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
In 22560 devices the firmware will do all the hw configurations,
but that's not ready yet.
Update the correct registers in the driver until the FW is ready
and does it by itself.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
22560 devices RFH uses different structures, which act similar
to the legacy rxq management lists - free and used list.
The iwl_rx_transfer_desc struct is part of the free list,
and consists of pointers to the empty rb's the driver wants to
pass to the fw.
The iwl_rx_completion_desc struct is part of the used list,
and consists of pointers to the buffer the fw filled up
with new rx, both commands and data, for the host.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
22560 devices use a new tx cmd api. Update the code to use
the new api.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
22560 devices tfd queue max size is 2^16. Allow a configurable
max size in the driver for supporting different devices.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Nowadays, the tfd queue max size is 2^8, and the reserved size in the
command header sequence field for the tfd entry index is 8 bits,
allowing an injective function from the hw pointers to the tfd entry index
in the sequence field.
In 22560 devices the tfd queue max size is 2^16, meaning that
the hw pointers are 16 bit long (allowing to point to each entry
in the tfd queue). However, the reserved space in the sequence field for
the tfd entry doesn't change, and we are limited to 8 bit.
This requires cancelling the injective function from hw pointer to
tfd entry in the sequence number.
Use iwl_pcie_get_cmd_index to wrap the hw pointer's to the n_window
size, which is maximum 256 in tx queues, and so, keep the injective
function between the window wrapped hw pointers to tfd entry index in
the sequence.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
In 22560 devices the ROM sendis an interrupt to the host
once the IML reading is done.
Handle this interrupt, and indicate sw error in case the
value is fail.
Additionally, the cause for sw error in 22560 devices
have been changed, so update the cause list.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
In 22560 devices we can start debug using context info gen3. Configure
the fw to start collecting logs to the dram before init.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
For devices which use the image loader image, the length of the frame
must be updated in the byte count in bytes, and not dwords as today.
Avoid dividing the input length by 4.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Context information structure was added to 22000 devices for
firmware self init.
In the next generation of devices the context information
changes significantly, and the original context information
is divided roughly to three data structures: context information gen3,
prph information and prph scratch.
In addition, the init flow changes so the firmware is loaded
by the IML, and so we must allocate the IML on the DRAM and
give the ROM the IML's address before kicking the firmware's
self init.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
The hw now refers to two new blocks:
* rx tr tail - The Tail index on the free buffers queue TR,
which is update by the device after reading the free buffer
from the tr.
* rx cr tail - Updated by the driver when completing
processing a new completion descriptor in the cr.
Add these two new struct to the rxq, allocate and free them
when needed.
In addition, the register for rx write pointer had been changed
to HBUS_TARG_WRPTR. The way to differentiate tx from rx is the
queue number. TX range is 0-511, and RX's is 512-527.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Device 22560 have many different hw and sw features than 22000 family,
so introduce a new family of devices - 22560.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Different device families may have different flag values
for passing a message to the fw (i.e. SW_RESET).
In order to keep the code readable, and avoid conditioning
upon the family, store a value for each flag, which indicates
the bit that needs to be enabled.
Additionally, support 22560 device csr flags and addresses.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Add support for the new 22560 family of devices and, while at it,
reorganize the 22000 family so it fits better with the new one.
Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Our current HE devices don't support BlockAck with the large bitmap,
so can't do TX aggregation with 256 frames. Restrict to the lower HT
size.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Add a module parameter to disable 802.11ax features in supported
devices. This is useful for testing or if there are interoperability
issues with some APs.
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Since the clocksource framework has introduced one suspend clocksource to
compensate the suspend time, this patch registers one always-on timer as
the suspend clocksource.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch adds a new "System Timer" on the Mediatek SoCs.
The System Timer is introduced as an always-on timer being
clockevent device for tick-broadcasting.
For clock, it is driven by 13 MHz system clock.
The implementation uses the system clock with no clock
source divider.
For interrupt, the clock event timer can be used by all cores.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Convert the driver to use the timer_of helpers.
This allows to remove custom proprietary structure,
factors out and simplifies the code.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Use specific prefix to specify the name of supported
timer hardware: "General Purpose Timer (GPT)".
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Rename mtk_timer to timer-mediatek to apply new naming convention
in clocksource folder.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This patch adds bindings of new "System Timer" on Mediatek SoCs.
Remove RTC clock in the same time because it is not used by
both "General Purpose Timer" and "System Timer" now.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Currently, quite a few clockevent devices have cpumask set to
cpu_all_mask which should be fine. However, cpu_possible_mask is more
accurate and if there are any other clockevent devices in the system
which have cpumask set to cpu_possible_mask, then having cpu_all_mask
may result in issues (mostly boot hang with forever loops in
clockevents_notify_released).
So, lets replace all the clockevent device cpu_all_mask to
cpu_possible_mask in order to prevent above mentioned possible issue.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
With lockdep turned on, the following circular lock dependency problem
was reported:
[ 57.470040] ======================================================
[ 57.502900] WARNING: possible circular locking dependency detected
[ 57.535208] 4.18.0-0.rc3.1.el8+7.x86_64+debug #1 Tainted: G
[ 57.577761] ------------------------------------------------------
[ 57.609714] tuned/1505 is trying to acquire lock:
[ 57.633808] 00000000559deec5 (cpu_hotplug_lock.rw_sem){++++}, at: store+0x27/0x120
[ 57.672880]
[ 57.672880] but task is already holding lock:
[ 57.702184] 000000002136ca64 (kn->count#118){++++}, at: kernfs_fop_write+0x1d0/0x410
[ 57.742176]
[ 57.742176] which lock already depends on the new lock.
[ 57.742176]
[ 57.785220]
[ 57.785220] the existing dependency chain (in reverse order) is:
:
[ 58.932512] other info that might help us debug this:
[ 58.932512]
[ 58.973344] Chain exists of:
[ 58.973344] cpu_hotplug_lock.rw_sem --> subsys mutex#5 --> kn->count#118
[ 58.973344]
[ 59.030795] Possible unsafe locking scenario:
[ 59.030795]
[ 59.061248] CPU0 CPU1
[ 59.085377] ---- ----
[ 59.108160] lock(kn->count#118);
[ 59.124935] lock(subsys mutex#5);
[ 59.156330] lock(kn->count#118);
[ 59.186088] lock(cpu_hotplug_lock.rw_sem);
[ 59.208541]
[ 59.208541] *** DEADLOCK ***
In the cpufreq_register_driver() function, the lock sequence is:
cpus_read_lock --> kn->count
For the cpufreq sysfs store method, the lock sequence is:
kn->count --> cpus_read_lock
These sequences are actually safe as they are taking a share lock on
cpu_hotplug_lock. However, the current lockdep code doesn't check for
share locking when detecting circular lock dependency. Fixing that
could be a substantial effort.
Instead, we can work around this problem by using cpus_read_trylock()
in the store method which is much simpler. The chance of not getting
the read lock is very small. If that happens, the userspace application
that writes the sysfs file will get an error.
Signed-off-by: Waiman Long <longman@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
There are use cases where it can be useful to have a cpus_read_trylock()
function to work around circular lock dependency problem involving
the cpu_hotplug_lock.
Signed-off-by: Waiman Long <longman@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
In the quest to remove all stack VLA usage from the kernel [1], this
removes the discouraged use of AHASH_REQUEST_ON_STACK by switching to
shash directly and allocating the descriptor in heap memory (which should
be fine: the tfm has already been allocated there too).
Link: https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qPXydAacU1RqZWA@mail.gmail.com # [1]
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
systrace used for tracing for Android systems has carried a patch for
many years in the Android tree that traces when the cpufreq limits
change. With the help of this information, systrace can know when the
policy limits change and can visually display the data. Lets add
upstream support for the same.
Signed-off-by: Ruchi Kandoi <kandoiruchi@google.com>
Signed-off-by: Joel Fernandes (Google) <joel@joelfernandes.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The Intel SoC DTS uses a hardcoded GSI number, before this commit
it was passing it to request_irq as if it were a linux irq number,
but there is no 1:1 mapping so in essence it was requesting a
random interrupt.
Besides this causing the DTS driver to not actually get an interrupt
if the thermal thresholds are exceeded this also is causing an
interrupt conflict on some devices since the linux irq 86 which is
being requested is already in use, leading to oopses like this:
genirq: Flags mismatch irq 86. 00002001 (soc_dts) vs. 00000083 (volume_down)
CPU: 0 PID: 601 Comm: systemd-udevd Tainted: G C OE 4.17.0-rc6+ #45
Hardware name: Insyde i86/Type2 - Board Product Name, BIOS CHUWI.D86JLBNR03 01/14/2015
Call Trace:
dump_stack+0x5c/0x80
__setup_irq.cold.50+0x4e/0xac
? request_threaded_irq+0xad/0x160
request_threaded_irq+0xf5/0x160
? 0xffffffffc0a93000
intel_soc_thermal_init+0x74/0x1000 [intel_soc_dts_thermal]
This commit makes the intel_soc_dts_thermal.c code call
acpi_register_gsi() to translate the hardcoded IO-APIC GSI number (86)
to a linux irq, so that the dts code uses the right interrupt and we
no longer get an oops about an irq conflict.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning:
drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning:
'mout_user_aclk400_mcuisp_p4x12' defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Minor cleanups and fixes.
-----BEGIN PGP SIGNATURE-----
iQItBAABCAAXBQJbWJ83EBxrcnprQGtlcm5lbC5vcmcACgkQwTdm5oaLg9d+7xAA
j2yiTMIXwDRuT61odTKE7TDoIkJUYmWGfnEWfDmeNyYEQmSaZNSbOP97LQI1u8mv
/xCMS1RjO+G54HLpKBet3Xk/ZR+aGp/mkDN9hrGwCgfVvo9eiaSAWTw160lLumhB
DbP3jgsmmsCId0nmXMh3hn23/kV17g/JHGrHI0Mug02ZT8giyfZesXSue2sHHkGk
erl/gQ5Lj0W/sMFwaI1bu5ai/ALWzq0huzaCMEGVV+2SOPtrCHKtoiBu01DmMf6u
ug+uBsJeFS/NL4+S3Iw6//6l8o3sihtCR+HmqNpIv+N5zqCri1dc6GyhRH4hFcdG
Per8qo//V/6vQtle+HYeJBLwTkWdAcad9WfBwMncdIvKimC3nOk89T3DYQ3cDk8E
nIiqz9i8c2TYSIGwv05YcBzlY+kpBwQ/mbdW7G11kvwGteddJwVVTbAscwGWXQ1R
Yrc426I2w/tB/2EdUB28Pn4gp1C9Jco0dMRJnml1BOl4kfZkmI/0APllbGKSsUl8
O8T4ERsZUGZEgMGFKTJfdwAYnqM3RIoxBExfe0/0CyO+QNC0USKqBG2JgUQkEq9J
CzTFplxZMW5cRfBWK6uPsH1d2waGg73ifEeGwznche+cGwxHbTUFdzHWQbldLWS0
1cJnSVSTkvyFj8SFM/zSmt6SmGQvIDcy8DPiRm9ix6Y=
=1puh
-----END PGP SIGNATURE-----
Merge tag 'samsung-soc-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc
Samsung mach/soc changes for v4.19
Minor cleanups and fixes.
* tag 'samsung-soc-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: exynos: Clear global variable on init error path
ARM: exynos: Remove outdated maintainer information
ARM: s3c24xx: Fix typo in guard macro of s3c2412.h
Signed-off-by: Olof Johansson <olof@lixom.net>
The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting
server platforms but it did not make it to the market really. There are
no development boards with it and probably there are no real products
neither. The development for Exynos5440 ended in 2013 and since then
the platform is in maintenance mode.
Removing Exynos5440 makes our life slightly easier: less maintenance,
smaller code, reduced number of quirks, no need to preserve DTB
backward-compatibility.
The Device Tree sources and some of the drivers for Exynos5440 were
already removed. This removes remaining drivers.
-----BEGIN PGP SIGNATURE-----
iQItBAABCAAXBQJbWKG7EBxrcnprQGtlcm5lbC5vcmcACgkQwTdm5oaLg9fNiA//
U/dI+ihiIXHOxtrVRZXNGsmI5545pUqLI5uTE9utvD2j10Ef+T45wOzcJEtVN5ro
+Mnqt32+LC0UfAo721Vfziu91t9HCYdeq6gFfgKS3mm5GPqqmsD7havl/UpT4jvL
JZZLTPoInT2zJ0oZanzIRoM5I7KCOrUikkoVYEq9Z2/DupZ/S1GJLYXq1kY00eXS
xrtNxTyhi6Hmg80h1u93jUfilWPuYvXAuTfK+nyHNXLDkVRAprEXEc0HCdKp0gKT
hCEVd/k2+FsREQSCq5+dCTvYwa/FATqvwU/pKZmhSuN4GOM6b/0kFFvTt0sUswY3
ZFGnEhnXQ9JGHf3/1cXdRn3e/1/5vOyjchKzCdF5Pyo40HIvI1qSK4mhCSO355PO
sIgI2OEEBCqVuu4HUeWDu13M7Q4haSHRCtqVyulT2LsNGRrm3Ko13lCz+knanMqH
4Cs7dLSz4ZqCSC4XYs8lnUvOFu2e/71vYs39QMi9yGro9Wn5T7H4qPNLVUuMER3K
Hwrj5CpGKqBnMt3qFAfsxB0CnHU+yIRb55qp9nTZSUzZ9B++qnDhoDd1ikYtc/yh
EHAnszKGPox2JbBzJRRQtpUq+qegnFaAkjssZf2eY89KKkjw/sHtssMA60dpV1tY
txpP7KiTiM3Cq0/Jdqi5D2kiiiFtpABo1Jb3CLzxlTk=
=3x4x
-----END PGP SIGNATURE-----
Merge tag 'samsung-drivers-exynos5440-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers
Exynos5440 drivers removal
The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting
server platforms but it did not make it to the market really. There are
no development boards with it and probably there are no real products
neither. The development for Exynos5440 ended in 2013 and since then
the platform is in maintenance mode.
Removing Exynos5440 makes our life slightly easier: less maintenance,
smaller code, reduced number of quirks, no need to preserve DTB
backward-compatibility.
The Device Tree sources and some of the drivers for Exynos5440 were
already removed. This removes remaining drivers.
* tag 'samsung-drivers-exynos5440-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
usb: host: exynos: Remove support for Exynos5440
clk: samsung: Remove support for Exynos5440
cpufreq: exynos: Remove support for Exynos5440
ata: ahci-platform: Remove support for Exynos5440
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit 7f9545aa1a ("arm64: smp: remove cpu and numa topology
information when hotplugging out CPU") updates the cpu topology when
the CPU is hotplugged out. However the PSCI checker code uses the
topology_core_cpumask pointers for some of the cpu hotplug testing.
Since the pointer to the core_cpumask of the first CPU in the group
is used, which when that CPU itself is hotpugged out is just set to
itself, the testing terminates after that particular CPU is tested out.
But the intention of this tests is to cover all the CPU in the group.
In order to support that, we need to stash the topology_core_cpumask
before the start of the test and use that value instead of pointer to
a cpumask which will be updated on CPU hotplug.
Fixes: 7f9545aa1a ("arm64: smp: remove cpu and numa topology
information when hotplugging out CPU")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Moves DPAA2 DPIO driver from staging to fsl/soc
Adds multiple-pin support to QE gpio driver
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbV51GAAoJEIbcUA77rBVUzB0P/1l1XZ14jlyIc4PI8eiEKx2i
Emet7qvEaeeoRYI06Dqtm+VkNYjO2Ev4n+XQYPTZGP3/b+cPh7CEI1N/L+ULFGop
HtD0FsOikvfql7BMHvGCCRLzFYHYjDNpg8JCB/3q+aOhI3/8HQyVIAEyggh1Ztam
NSmMQXHwdB8d1qAGcSYGttiJCIxLcDUtVEGcF6ZN6Lg3orpDHEbCceeQ10f1yayQ
PZuM+F1YFM4Lp17gt92caMSKENsN0Kyk/7lEVPHq0ANGMvVsHIVtZGJML+/ulaeI
v7FZrEicYJVu8LDkFAPeg3qK+O6WirOa9bQEctH7jia43QWZAZ9EROCkFOzlEwx6
+AmOB5BsqMTQsz7HppNOqB6v3zgK898UIYavGeud0c/SaIqAW3uVkKvHLKxXd/uY
K2eyvxcBs9ttK+qLopLWO1QzwWAvedIZFjSDCYpGcWDlhZR1lOqoC1u6wSApX/ZC
h7SGOOhjmzZBLtS89hHn7LnzN7RI6teNmC9uhdFtY+55IVfcRAzX3m2ym/TWPRc8
dQNA/vNMuXK2Hv8rtElqIEVUvWil3p86+640m1fnbkljmSqgzp8vAIAopUbhq2Qj
QytaQBwWPcIoAgKQjLMOypjyCTyNs1oFhKycGlwL4Jq5BwxWq27714fl+dSk4JMz
itj5Fz0+82WeDts7CBjM
=9CHI
-----END PGP SIGNATURE-----
Merge tag 'soc-fsl-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into next/drivers
Various updates to soc/fsl for 4.19
Moves DPAA2 DPIO driver from staging to fsl/soc
Adds multiple-pin support to QE gpio driver
* tag 'soc-fsl-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: cleanup Kconfig menu
soc: fsl: dpio: Convert DPIO documentation to .rst
staging: fsl-mc: Remove remaining files
staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
staging: fsl-dpaa2: eth: move generic FD defines to DPIO
soc: fsl: qe: gpio: Add qe_gpio_set_multiple
Signed-off-by: Olof Johansson <olof@lixom.net>
There's been work for this release cycles in both the SRAM controller
driver in order to support more SoCs, as part of our VPU work, but also to
enable the EMAC on the A64 (that needs to poke at registers within the same
register space).
Some work has been needed too to represent the bus to the display engine
controllers that all need an SRAM to be mapped to the CPU to be able to
access those controllers' registers.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAltXJkEACgkQ0rTAlCFN
r3R00g/8CkjHrlXejLLTxjMGdVQYnmgVL3wPBbXaqi6wtg/ATLpXN5b5m+CbRZEJ
cMyY4LVYMbmQ1aLwAUNlDzNbv5vxR5tYJ9X3x63wf1AlFPEwwOO0sy17yZp2J8Rx
FFHx/dciQPbXkbOyIF+P+b49rO7gQ1dsbl5UyEA6nfeVmbPyeamwUdYy2559fkb1
3yWyTTUbXoEsDrKjuRf+tVdDr2ssTDqmT3qFTgl2jHZ5Bbyzq2aBH0NLBlk3G1te
v4ceHRue/guEkjYnVEtIezhJMUwaDZcL5zuuRDINbT609mAMkO9he1Dz5BcvYe00
Rt5h304Nt6JSOM5iEDYnh1mzvdflm3ZR12/TTyxtmGVNB9PxVEj8z/0lT4rLOC7I
H5uNxbM5eM6GQKQou+W8OXRPyuKJ8PXWWk58ajf0knMuIBcYOU0tdrFrWcPxaFXK
VScPibv7NEs7np3mKc32L0WmsgHrfMK9mmgvFZFfhAgYM6oHM356bo+Jawrn3aJY
aL/MQ3+rxjQBwUeNbZDnt4ROoM0hYUYt2s5dNiYY8sfhy37fwZz1Vrg810MLQLTA
q/5VB7dEHGVQNZaYToo7RVegre3bMsYzG0DdZCKyZKaknJjH4hC67yOd5vD8wpMH
WMCHx+s/3A0S/BRNjstV2UNFZfsJN8BHUDC/aYda1TJc9cbvSAo=
=NuX/
-----END PGP SIGNATURE-----
Merge tag 'sunxi-drivers-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/drivers
Allwinner drivers changes for 4.19
There's been work for this release cycles in both the SRAM controller
driver in order to support more SoCs, as part of our VPU work, but also to
enable the EMAC on the A64 (that needs to poke at registers within the same
register space).
Some work has been needed too to represent the bus to the display engine
controllers that all need an SRAM to be mapped to the CPU to be able to
access those controllers' registers.
* tag 'sunxi-drivers-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
soc: sunxi: Add the A13, A23 and H3 system control compatibles
drivers: soc: sunxi: Add support for the C1 SRAM region
dt-bindings: sram: sunxi: Populate valid sections compatibles
dt-bindings: sram: sunxi: Add A13, A20, A23 and H3 dedicated bindings
soc: sunxi: sram: Add dt match for the A10 system-control compatible
dt-bindings: sram: sunxi: Introduce new A10 binding for system-control
bus: add bus driver for accessing Allwinner A64 DE2
dt-bindings: add binding for the Allwinner A64 DE2 bus
soc: sunxi: sram: Add updated compatible string for A64 system control
dt-bindings: sram: Rename A64 SRAM controller compatible
soc: sunxi: export a regmap for EMAC clock reg on A64
Signed-off-by: Olof Johansson <olof@lixom.net>
Our usual bunch of changes shared between arm and arm64.
This time, we have:
- eMMC support for the ALL-H3-CC boards
- EMAC support for the Beelink X2
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAltXJHsACgkQ0rTAlCFN
r3TrXQ//ai4SQCdkx9sWvbmVll3qhoFWT4cRE5S8bWI/9nJmoYGmlIW94PgLXi3f
ck5lMgkL1yNLDD66ym+YW57fcXjAVkySsqySMOwFkhKCFKVeZnT69om3jl7dWXou
8ieJblWO7MZUhQ7IFZdq/+KAzmQKw9H0He27Pe1x0KEEbOHgkjsWBZPnSvRMbnyC
wBt3ItecbtK/5wNmgvGrQr6yLooXnsfLS8tq/je/mP+/260FfZcvt5J73mvi/JVX
k4WISVHB+QL3tIS+/8jijYG+PD3Is9OxXcQdmGVACGyPxKQQpgmUqakn2IGwpXWv
gTc5CPOAigDKhICgbGaeiHNM/9+UEA9kqQQmweUpM0dd5p2O+mIbdOAstvQCD41y
iK5NmBrr9Q/XaobeogtQNVxDmcyFtjEp4vftHIRSt9kijIN1yhCKlC/SiRIP6hlr
t/lsXiIDyfh1eo5ZZdIltcCxKD6LpWwUqs9tRRGCXQOEz6tLivF/VFIgpvDsthLO
N/tPHeqA9VMBybyEavJsq7hs+Ckt5YbriOW+nWZRqgek0r9BHcZ2nFBg5nMhqIWw
jCZ62PXmIdJJNtaDcO/ZidWAZMIeoiTmm4VJzyhIwMMQG8DT4ONWsxxsT1aHCGk8
k7MT1/RLDHFBuj2dJKbwPIsyF8ivZAodtWdNu67zeXs+8l7vd04=
=Blyi
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3/H5 changes for 4.19
Our usual bunch of changes shared between arm and arm64.
This time, we have:
- eMMC support for the ALL-H3-CC boards
- EMAC support for the Beelink X2
* tag 'sunxi-h3-h5-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi-h3-h5: Remove unused address-cells/size-cells of dwmac-sun8i
ARM: dts: sunxi: libretech-all-h3-cc: Enable eMMC module
ARM: sun8i: h3: add SY8113B regulator on Banana Pi M2 Zero board
ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2
ARM: dts: sun8i-h3: Add missing cooling device properties for CPUs
Signed-off-by: Olof Johansson <olof@lixom.net>
multi_v7_defconfig and shmobile_defconfig Enhancement:
* Enable support for recently upstreamed RZN1D-DB board
in multi_v7_defconfig and shmobile_defconfig. This is
to give better test coverage.
shmobile_defconfig Clean-Up:
* Drop NET_VENDOR_<FOO>=n
This reduces the size of the defconfig without any change in the
resulting kernel config.
shmobile_defconfig Enhancements:
* Disable long deprecated /sbin/hotplug helper
* Enable reset controller support
This is to give better test coverage.
This may be used by reset controller support in the Renesas CPG/MSSR
driver when used by R-Car Gen2 and RZ/G1 SoCs.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAltVwNgACgkQ189kaWo3
T77n0A//RJDW4z+u4NqA9iQb9TXxFMQ+VTVtqGU0KkkNU5WMAIH8IeDTzm23aS0U
A7R7AQwqyT231UlLseRlYIzU/wZeHzyZmqZFueGXiTUdp2Nr1dlTeRy4we1ZIbBj
POOb9G68qygZXceb93BAZ13oS1BwIpD4dM4KM05eeVztOQVYzZDXUisZyThP5YkJ
ytN68X5y32mjUtnPKj4s3daKxNanlkDrzsNWRLuy+5nxE8Fxhau/ua1/GI6YLc8p
jomTUaYOuLIiNasKDlkYZCi6+LyTpXO98yvPJh5q0ULyr9nJhUyj4uWowJTAdAFl
5pFW7av6znH+zwtz/g5jIHodvLHI4i2N40L9JHCe1NCpE4yNkFnfCKrr1Xi35g8z
DQ4Vk8wvXW0aaIvJa/fXUNvMqRdex4lKTII/R5d3p7ktck+7hA7JTUqY3lCjiIH3
MjEnjx5tKZYQ+9eGFBNMYgZvgdV08vth3NUEX+n1I4HT/w5wtOLaWNcZqcSp1YaN
rxopQBIgu2sjJ4mEzzg3iJMyCDqKouHJqYVT4Vr+VO+AMpQUmT8XOu8Jpl//U/kc
cdbB7LVS5sNCvQc9hKAue88AviNDJBuBcUeL8/TtmS3S07RaoPMhxft9+bE7yOdp
U88far+cSxix0DJCC49HcbBSj00MJGbcQVxxyebtukVl104Rh84=
=tQ3T
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/defconfig
Renesas ARM Based SoC Defconfig Updates for v4.19
- Enable new RZN1D-DB board in multi_v7_defconfig and shmobile_defconfig
- shmobile_defconfig:
+ Drop NET_VENDOR_<FOO>=n
+ Disable long deprecated /sbin/hotplug helper
+ Enable reset controller support
* tag 'renesas-arm-defconfig-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: multi_v7_defconfig: Enable support for RZN1D-DB
ARM: shmobile: defconfig: Disable /sbin/hotplug fork-bomb
ARM: shmobile: defconfig: Enable support for RZN1D-DB
ARM: shmobile: defconfig: Enable reset controller support
ARM: shmobile: defconfig: Drop NET_VENDOR_<FOO>=n
Signed-off-by: Olof Johansson <olof@lixom.net>
