IOMMU Updates for Linux v6.1:
Including: - Removal of the bus_set_iommu() interface which became unnecesary because of IOMMU per-device probing - Make the dma-iommu.h header private - Intel VT-d changes from Lu Baolu: - Decouple PASID and PRI from SVA - Add ESRTPS & ESIRTPS capability check - Cleanups - Apple DART support for the M1 Pro/MAX SOCs - Support for AMD IOMMUv2 page-tables for the DMA-API layer. The v2 page-tables are compatible with the x86 CPU page-tables. Using them for DMA-API prepares support for hardware-assisted IOMMU virtualization - Support for MT6795 Helio X10 M4Us in the Mediatek IOMMU driver - Some smaller fixes and cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmNEC5oACgkQK/BELZcB GuNcOQ/6A5SXmcvDRLYZW1ENM5Z6xsZ1LabSZkjhYSpmbJyu8Uny/Z2aRWqxPMLJ hJeHTsWSLhrTq1VfjFhELHB3kgT2DRr7H3LXXaMNC6qz690EcavX1wKX2AxH0m22 8YrktkyAmFQ3BG6rsQLdlMMasLph/x06ix/xO9opQZVFdj/fV0Jx7ekX1JK+U3hx MI96i5W3G5PBVHBypAvjxSlmA4saj9Fhk7l3IZL7py9AOKz7NypuwWRs+86PMBiO EzLt5aF4g8pmKChF/c9BsoIbjBYvTG/s3NbycIng0ACc2SOvf+EvtoVZQclWifbT lwti9PLdsoVUnPOZHLYOTx4xSf/UyoLVzaLxJ52aoXnNYe2qaX5DANXhT2mWIY/Y z1mzOkShmK7WF7a8arRyqJeLJ4SvDx8GrbvLiom3DAzmqVHzzFGadHtt5fvGYN4F Jet/JIN3HjECQbamqtPBpWquBFhLmgusPksIiyMFscRvYdZqkaVkTkElcF3WqAMm QkeecfoTQ9Vdtdz44ZVLRjKpS77yRZmHshp1r/rfSI+9Ok8uRI+xmmcyrAI6ElqH DH14tLHPzw694rTHF+bTCd+pPMGOoFLi0xAfUXAeGWm1uzC1JIRrVu5JeQNOUOSD 5SQDXB7dPrhXngaws5Fx2u3amCO3688mslcGgM7q54kC+LyVo0E= =h0sT -----END PGP SIGNATURE----- Merge tag 'iommu-updates-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - remove the bus_set_iommu() interface which became unnecesary because of IOMMU per-device probing - make the dma-iommu.h header private - Intel VT-d changes from Lu Baolu: - Decouple PASID and PRI from SVA - Add ESRTPS & ESIRTPS capability check - Cleanups - Apple DART support for the M1 Pro/MAX SOCs - support for AMD IOMMUv2 page-tables for the DMA-API layer. The v2 page-tables are compatible with the x86 CPU page-tables. Using them for DMA-API prepares support for hardware-assisted IOMMU virtualization - support for MT6795 Helio X10 M4Us in the Mediatek IOMMU driver - some smaller fixes and cleanups * tag 'iommu-updates-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (59 commits) iommu/vt-d: Avoid unnecessary global DMA cache invalidation iommu/vt-d: Avoid unnecessary global IRTE cache invalidation iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support iommu/vt-d: Remove pasid_set_eafe() iommu/vt-d: Decouple PASID & PRI enabling from SVA iommu/vt-d: Remove unnecessary SVA data accesses in page fault path dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names iommu: dart: Support t6000 variant iommu/io-pgtable-dart: Add DART PTE support for t6000 iommu/io-pgtable: Add DART subpage protection support iommu/io-pgtable: Move Apple DART support to its own file iommu/mediatek: Add support for MT6795 Helio X10 M4Us iommu/mediatek: Introduce new flag TF_PORT_TO_ADDR_MT8173 dt-bindings: mediatek: Add bindings for MT6795 M4U iommu/iova: Fix module config properly iommu/amd: Fix sparse warning iommu/amd: Remove outdated comment iommu/amd: Free domain ID after domain_flush_pages iommu/amd: Free domain id in error path iommu/virtio: Fix compile error with viommu_capable() ...
This commit is contained in:
Linus Torvalds
commit
f23cdfcd04
60 changed files with 1501 additions and 902 deletions
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@ -1,93 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-2015 ARM Ltd.
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*/
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#ifndef __DMA_IOMMU_H
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#define __DMA_IOMMU_H
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#include <linux/errno.h>
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#include <linux/types.h>
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#ifdef CONFIG_IOMMU_DMA
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#include <linux/dma-mapping.h>
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#include <linux/iommu.h>
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#include <linux/msi.h>
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/* Domain management interface for IOMMU drivers */
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int iommu_get_dma_cookie(struct iommu_domain *domain);
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int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
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void iommu_put_dma_cookie(struct iommu_domain *domain);
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/* Setup call for arch DMA mapping code */
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void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit);
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int iommu_dma_init_fq(struct iommu_domain *domain);
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/* The DMA API isn't _quite_ the whole story, though... */
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/*
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* iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device
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*
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* The MSI page will be stored in @desc.
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*
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* Return: 0 on success otherwise an error describing the failure.
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*/
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int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
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/* Update the MSI message if required. */
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void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg);
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void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
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void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,
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struct iommu_domain *domain);
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extern bool iommu_dma_forcedac;
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#else /* CONFIG_IOMMU_DMA */
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struct iommu_domain;
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struct msi_desc;
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struct msi_msg;
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struct device;
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static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base,
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u64 dma_limit)
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{
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}
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static inline int iommu_dma_init_fq(struct iommu_domain *domain)
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{
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return -EINVAL;
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}
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static inline int iommu_get_dma_cookie(struct iommu_domain *domain)
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{
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return -ENODEV;
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}
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static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
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{
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return -ENODEV;
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}
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static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
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{
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}
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static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
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phys_addr_t msi_addr)
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{
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return 0;
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}
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static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg)
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{
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}
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static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
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{
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}
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#endif /* CONFIG_IOMMU_DMA */
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#endif /* __DMA_IOMMU_H */
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@ -16,7 +16,9 @@ enum io_pgtable_fmt {
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ARM_V7S,
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ARM_MALI_LPAE,
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AMD_IOMMU_V1,
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AMD_IOMMU_V2,
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APPLE_DART,
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APPLE_DART2,
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IO_PGTABLE_NUM_FMTS,
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};
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@ -260,6 +262,7 @@ extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns;
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#endif /* __IO_PGTABLE_H */
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@ -212,7 +212,7 @@ struct iommu_iotlb_gather {
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* @of_xlate: add OF master IDs to iommu grouping
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* @is_attach_deferred: Check if domain attach should be deferred from iommu
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* driver init to device driver init (default no)
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* @dev_has/enable/disable_feat: per device entries to check/enable/disable
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* @dev_enable/disable_feat: per device entries to enable/disable
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* iommu specific features.
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* @sva_bind: Bind process address space to device
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* @sva_unbind: Unbind process address space from device
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@ -227,7 +227,7 @@ struct iommu_iotlb_gather {
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* @owner: Driver module providing these ops
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*/
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struct iommu_ops {
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bool (*capable)(enum iommu_cap);
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bool (*capable)(struct device *dev, enum iommu_cap);
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/* Domain allocation and freeing by the iommu driver */
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struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type);
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@ -416,11 +416,9 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev)
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return dev->iommu->iommu_dev->ops;
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}
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extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops);
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extern int bus_iommu_probe(struct bus_type *bus);
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extern bool iommu_present(struct bus_type *bus);
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extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap);
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extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap);
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extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);
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extern struct iommu_group *iommu_group_get_by_id(int id);
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extern void iommu_domain_free(struct iommu_domain *domain);
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@ -697,11 +695,6 @@ static inline bool device_iommu_capable(struct device *dev, enum iommu_cap cap)
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return false;
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}
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static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)
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{
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return false;
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}
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static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus)
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{
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return NULL;
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@ -1070,4 +1063,40 @@ void iommu_debugfs_setup(void);
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static inline void iommu_debugfs_setup(void) {}
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#endif
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#ifdef CONFIG_IOMMU_DMA
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#include <linux/msi.h>
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/* Setup call for arch DMA mapping code */
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void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit);
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int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
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int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
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void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg);
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#else /* CONFIG_IOMMU_DMA */
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struct msi_desc;
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struct msi_msg;
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static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit)
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{
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}
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static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
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{
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return -ENODEV;
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}
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static inline int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
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{
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return 0;
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}
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static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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}
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#endif /* CONFIG_IOMMU_DMA */
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#endif /* __LINUX_IOMMU_H */
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@ -75,7 +75,7 @@ static inline unsigned long iova_pfn(struct iova_domain *iovad, dma_addr_t iova)
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return iova >> iova_shift(iovad);
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}
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#if IS_ENABLED(CONFIG_IOMMU_IOVA)
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#if IS_REACHABLE(CONFIG_IOMMU_IOVA)
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int iova_cache_get(void);
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void iova_cache_put(void);
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