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arm64: dts: renesas: r8a779f0: Add CPU core clocks

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Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.

For now no operating points are defined.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-06-08 17:40:22 +02:00
parent 9bc7cd07aa
commit e5fba0bc82
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
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@ -64,6 +64,7 @@
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_1: cpu@100 {
@ -74,6 +75,7 @@
next-level-cache = <&L3_CA55_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_2: cpu@10000 {
@ -84,6 +86,7 @@
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_3: cpu@10100 {
@ -94,6 +97,7 @@
next-level-cache = <&L3_CA55_1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
};
a55_4: cpu@20000 {
@ -104,6 +108,7 @@
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_5: cpu@20100 {
@ -114,6 +119,7 @@
next-level-cache = <&L3_CA55_2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_6: cpu@30000 {
@ -124,6 +130,7 @@
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
a55_7: cpu@30100 {
@ -134,6 +141,7 @@
next-level-cache = <&L3_CA55_3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
};
L3_CA55_0: cache-controller-0 {