IOMMU Updates for Linux v5.19
Including:
- Intel VT-d driver updates
- Domain force snooping improvement.
- Cleanups, no intentional functional changes.
- ARM SMMU driver updates
- Add new Qualcomm device-tree compatible strings
- Add new Nvidia device-tree compatible string for Tegra234
- Fix UAF in SMMUv3 shared virtual addressing code
- Force identity-mapped domains for users of ye olde SMMU
legacy binding
- Minor cleanups
- Patches to fix a BUG_ON in the vfio_iommu_group_notifier
- Groundwork for upcoming iommufd framework
- Introduction of DMA ownership so that an entire IOMMU group
is either controlled by the kernel or by user-space
- MT8195 and MT8186 support in the Mediatek IOMMU driver
- Patches to make forcing of cache-coherent DMA more coherent
between IOMMU drivers
- Fixes for thunderbolt device DMA protection
- Various smaller fixes and cleanups
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Merge tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
- Intel VT-d driver updates:
- Domain force snooping improvement.
- Cleanups, no intentional functional changes.
- ARM SMMU driver updates:
- Add new Qualcomm device-tree compatible strings
- Add new Nvidia device-tree compatible string for Tegra234
- Fix UAF in SMMUv3 shared virtual addressing code
- Force identity-mapped domains for users of ye olde SMMU legacy
binding
- Minor cleanups
- Fix a BUG_ON in the vfio_iommu_group_notifier:
- Groundwork for upcoming iommufd framework
- Introduction of DMA ownership so that an entire IOMMU group is
either controlled by the kernel or by user-space
- MT8195 and MT8186 support in the Mediatek IOMMU driver
- Make forcing of cache-coherent DMA more coherent between IOMMU
drivers
- Fixes for thunderbolt device DMA protection
- Various smaller fixes and cleanups
* tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (88 commits)
iommu/amd: Increase timeout waiting for GA log enablement
iommu/s390: Tolerate repeat attach_dev calls
iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
iommu/vt-d: Remove domain_update_iommu_snooping()
iommu/vt-d: Check domain force_snooping against attached devices
iommu/vt-d: Block force-snoop domain attaching if no SC support
iommu/vt-d: Size Page Request Queue to avoid overflow condition
iommu/vt-d: Fold dmar_insert_one_dev_info() into its caller
iommu/vt-d: Change return type of dmar_insert_one_dev_info()
iommu/vt-d: Remove unneeded validity check on dev
iommu/dma: Explicitly sort PCI DMA windows
iommu/dma: Fix iova map result check bug
iommu/mediatek: Fix NULL pointer dereference when printing dev_name
iommu: iommu_group_claim_dma_owner() must always assign a domain
iommu/arm-smmu: Force identity domains for legacy binding
iommu/arm-smmu: Support Tegra234 SMMU
dt-bindings: arm-smmu: Add compatible for Tegra234 SOC
dt-bindings: arm-smmu: Document nvidia,memory-controller property
iommu/arm-smmu-qcom: Add SC8280XP support
dt-bindings: arm-smmu: Add compatible for Qualcomm SC8280XP
...
This commit is contained in:
Linus Torvalds
commit
e1cbc3b96a
53 changed files with 2316 additions and 1035 deletions
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@ -79,6 +79,14 @@ struct amba_driver {
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void (*remove)(struct amba_device *);
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void (*shutdown)(struct amba_device *);
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const struct amba_id *id_table;
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/*
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* For most device drivers, no need to care about this flag as long as
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* all DMAs are handled through the kernel DMA API. For some special
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* ones, for example VFIO drivers, they know how to manage the DMA
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* themselves and set this flag so that the IOMMU layer will allow them
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* to setup and manage their own I/O address space.
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*/
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bool driver_managed_dma;
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};
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/*
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@ -59,6 +59,8 @@ struct fwnode_handle;
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* bus supports.
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* @dma_configure: Called to setup DMA configuration on a device on
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* this bus.
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* @dma_cleanup: Called to cleanup DMA configuration on a device on
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* this bus.
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* @pm: Power management operations of this bus, callback the specific
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* device driver's pm-ops.
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* @iommu_ops: IOMMU specific operations for this bus, used to attach IOMMU
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@ -103,6 +105,7 @@ struct bus_type {
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int (*num_vf)(struct device *dev);
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int (*dma_configure)(struct device *dev);
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void (*dma_cleanup)(struct device *dev);
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const struct dev_pm_ops *pm;
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@ -32,6 +32,13 @@ struct fsl_mc_io;
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* @shutdown: Function called at shutdown time to quiesce the device
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* @suspend: Function called when a device is stopped
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* @resume: Function called when a device is resumed
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* @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
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* For most device drivers, no need to care about this flag
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* as long as all DMAs are handled through the kernel DMA API.
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* For some special ones, for example VFIO drivers, they know
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* how to manage the DMA themselves and set this flag so that
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* the IOMMU layer will allow them to setup and manage their
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* own I/O address space.
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*
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* Generic DPAA device driver object for device drivers that are registered
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* with a DPRC bus. This structure is to be embedded in each device-specific
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@ -45,6 +52,7 @@ struct fsl_mc_driver {
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void (*shutdown)(struct fsl_mc_device *dev);
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int (*suspend)(struct fsl_mc_device *dev, pm_message_t state);
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int (*resume)(struct fsl_mc_device *dev);
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bool driver_managed_dma;
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};
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#define to_fsl_mc_driver(_drv) \
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@ -539,7 +539,8 @@ struct dmar_domain {
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u8 has_iotlb_device: 1;
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u8 iommu_coherency: 1; /* indicate coherency of iommu access */
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u8 iommu_snooping: 1; /* indicate snooping control feature */
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u8 force_snooping : 1; /* Create IOPTEs with snoop control */
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u8 set_pte_snp:1;
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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@ -9,7 +9,7 @@
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#define __INTEL_SVM_H__
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/* Page Request Queue depth */
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#define PRQ_ORDER 2
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#define PRQ_ORDER 4
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#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
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#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)
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@ -103,10 +103,11 @@ static inline bool iommu_is_dma_domain(struct iommu_domain *domain)
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}
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enum iommu_cap {
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IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA
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transactions */
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IOMMU_CAP_CACHE_COHERENCY, /* IOMMU_CACHE is supported */
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IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */
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IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */
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IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for
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DMA protection and we should too */
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};
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/* These are the possible reserved region types */
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@ -272,6 +273,9 @@ struct iommu_ops {
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* @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
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* queue
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* @iova_to_phys: translate iova to physical address
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* @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE,
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* including no-snoop TLPs on PCIe or other platform
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* specific mechanisms.
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* @enable_nesting: Enable nesting
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* @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*)
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* @free: Release the domain after use.
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@ -300,6 +304,7 @@ struct iommu_domain_ops {
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phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
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dma_addr_t iova);
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bool (*enforce_cache_coherency)(struct iommu_domain *domain);
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int (*enable_nesting)(struct iommu_domain *domain);
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int (*set_pgtable_quirks)(struct iommu_domain *domain,
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unsigned long quirks);
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@ -407,16 +412,10 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev)
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return dev->iommu->iommu_dev->ops;
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}
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#define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */
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#define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */
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#define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */
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#define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */
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#define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */
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#define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */
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extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops);
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extern int bus_iommu_probe(struct bus_type *bus);
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extern bool iommu_present(struct bus_type *bus);
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extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap);
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extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap);
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extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);
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extern struct iommu_group *iommu_group_get_by_id(int id);
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@ -478,10 +477,6 @@ extern int iommu_group_for_each_dev(struct iommu_group *group, void *data,
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extern struct iommu_group *iommu_group_get(struct device *dev);
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extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);
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extern void iommu_group_put(struct iommu_group *group);
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extern int iommu_group_register_notifier(struct iommu_group *group,
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struct notifier_block *nb);
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extern int iommu_group_unregister_notifier(struct iommu_group *group,
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struct notifier_block *nb);
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extern int iommu_register_device_fault_handler(struct device *dev,
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iommu_dev_fault_handler_t handler,
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void *data);
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@ -675,6 +670,13 @@ struct iommu_sva *iommu_sva_bind_device(struct device *dev,
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void iommu_sva_unbind_device(struct iommu_sva *handle);
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u32 iommu_sva_get_pasid(struct iommu_sva *handle);
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int iommu_device_use_default_domain(struct device *dev);
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void iommu_device_unuse_default_domain(struct device *dev);
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int iommu_group_claim_dma_owner(struct iommu_group *group, void *owner);
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void iommu_group_release_dma_owner(struct iommu_group *group);
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bool iommu_group_dma_owner_claimed(struct iommu_group *group);
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#else /* CONFIG_IOMMU_API */
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struct iommu_ops {};
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@ -689,6 +691,11 @@ static inline bool iommu_present(struct bus_type *bus)
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return false;
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}
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static inline bool device_iommu_capable(struct device *dev, enum iommu_cap cap)
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{
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return false;
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}
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static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap)
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{
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return false;
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@ -871,18 +878,6 @@ static inline void iommu_group_put(struct iommu_group *group)
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{
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}
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static inline int iommu_group_register_notifier(struct iommu_group *group,
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struct notifier_block *nb)
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{
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return -ENODEV;
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}
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static inline int iommu_group_unregister_notifier(struct iommu_group *group,
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struct notifier_block *nb)
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{
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return 0;
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}
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static inline
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int iommu_register_device_fault_handler(struct device *dev,
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iommu_dev_fault_handler_t handler,
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@ -1031,6 +1026,30 @@ static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev)
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{
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return NULL;
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}
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static inline int iommu_device_use_default_domain(struct device *dev)
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{
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return 0;
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}
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static inline void iommu_device_unuse_default_domain(struct device *dev)
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{
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}
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static inline int
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iommu_group_claim_dma_owner(struct iommu_group *group, void *owner)
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{
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return -ENODEV;
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}
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static inline void iommu_group_release_dma_owner(struct iommu_group *group)
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{
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}
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static inline bool iommu_group_dma_owner_claimed(struct iommu_group *group)
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{
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return false;
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}
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#endif /* CONFIG_IOMMU_API */
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/**
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@ -891,6 +891,13 @@ struct module;
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* created once it is bound to the driver.
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* @driver: Driver model structure.
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* @dynids: List of dynamically added device IDs.
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* @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
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* For most device drivers, no need to care about this flag
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* as long as all DMAs are handled through the kernel DMA API.
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* For some special ones, for example VFIO drivers, they know
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* how to manage the DMA themselves and set this flag so that
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* the IOMMU layer will allow them to setup and manage their
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* own I/O address space.
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*/
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struct pci_driver {
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struct list_head node;
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@ -909,6 +916,7 @@ struct pci_driver {
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const struct attribute_group **dev_groups;
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struct device_driver driver;
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struct pci_dynids dynids;
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bool driver_managed_dma;
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};
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static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
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@ -210,6 +210,14 @@ struct platform_driver {
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struct device_driver driver;
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const struct platform_device_id *id_table;
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bool prevent_deferred_probe;
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/*
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* For most device drivers, no need to care about this flag as long as
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* all DMAs are handled through the kernel DMA API. For some special
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* ones, for example VFIO drivers, they know how to manage the DMA
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* themselves and set this flag so that the IOMMU layer will allow them
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* to setup and manage their own I/O address space.
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*/
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bool driver_managed_dma;
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};
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#define to_platform_driver(drv) (container_of((drv), struct platform_driver, \
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@ -328,8 +336,6 @@ extern int platform_pm_restore(struct device *dev);
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#define platform_pm_restore NULL
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#endif
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extern int platform_dma_configure(struct device *dev);
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#ifdef CONFIG_PM_SLEEP
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#define USE_PLATFORM_PM_SLEEP_OPS \
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.suspend = platform_pm_suspend, \
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@ -465,6 +465,7 @@ static inline struct tb_xdomain *tb_service_parent(struct tb_service *svc)
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* @msix_ida: Used to allocate MSI-X vectors for rings
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* @going_away: The host controller device is about to disappear so when
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* this flag is set, avoid touching the hardware anymore.
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* @iommu_dma_protection: An IOMMU will isolate external-facing ports.
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* @interrupt_work: Work scheduled to handle ring interrupt when no
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* MSI-X is used.
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* @hop_count: Number of rings (end point hops) supported by NHI.
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@ -479,6 +480,7 @@ struct tb_nhi {
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struct tb_ring **rx_rings;
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struct ida msix_ida;
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bool going_away;
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bool iommu_dma_protection;
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struct work_struct interrupt_work;
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u32 hop_count;
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unsigned long quirks;
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Reference in a new issue