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net: hns3: refine function hclge_tm_pri_q_qs_cfg()

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This patch encapsulates the process code for queue to qset config of two
mode(tc based and vnet based) into two function, for making code more
concise.

Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Guangbin Huang 2021-11-29 22:00:24 +08:00 • committed by David S. Miller
parent 7ca561be11
commit e06dac5290
1 changed files with 50 additions and 25 deletions
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75
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View file

@ -916,37 +916,62 @@ static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
return 0;
}
static int hclge_tm_pri_q_qs_cfg_tc_base(struct hclge_dev *hdev)
{
struct hclge_vport *vport = hdev->vport;
u16 i, k;
int ret;
/* Cfg qs -> pri mapping, one by one mapping */
for (k = 0; k < hdev->num_alloc_vport; k++) {
struct hnae3_knic_private_info *kinfo = &vport[k].nic.kinfo;
for (i = 0; i < kinfo->tc_info.num_tc; i++) {
ret = hclge_tm_qs_to_pri_map_cfg(hdev,
vport[k].qs_offset + i,
i);
if (ret)
return ret;
}
}
return 0;
}
static int hclge_tm_pri_q_qs_cfg_vnet_base(struct hclge_dev *hdev)
{
struct hclge_vport *vport = hdev->vport;
u16 i, k;
int ret;
/* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
for (k = 0; k < hdev->num_alloc_vport; k++)
for (i = 0; i < HNAE3_MAX_TC; i++) {
ret = hclge_tm_qs_to_pri_map_cfg(hdev,
vport[k].qs_offset + i,
k);
if (ret)
return ret;
}
return 0;
}
static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
{
struct hclge_vport *vport = hdev->vport;
int ret;
u32 i, k;
u32 i;
if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
/* Cfg qs -> pri mapping, one by one mapping */
for (k = 0; k < hdev->num_alloc_vport; k++) {
struct hnae3_knic_private_info *kinfo =
&vport[k].nic.kinfo;
for (i = 0; i < kinfo->tc_info.num_tc; i++) {
ret = hclge_tm_qs_to_pri_map_cfg(
hdev, vport[k].qs_offset + i, i);
if (ret)
return ret;
}
}
} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
/* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
for (k = 0; k < hdev->num_alloc_vport; k++)
for (i = 0; i < HNAE3_MAX_TC; i++) {
ret = hclge_tm_qs_to_pri_map_cfg(
hdev, vport[k].qs_offset + i, k);
if (ret)
return ret;
}
} else {
if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE)
ret = hclge_tm_pri_q_qs_cfg_tc_base(hdev);
else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
ret = hclge_tm_pri_q_qs_cfg_vnet_base(hdev);
else
return -EINVAL;
}
if (ret)
return ret;
/* Cfg q -> qs mapping */
for (i = 0; i < hdev->num_alloc_vport; i++) {