MTD core changes:
* Spelling
* http to https updates
NAND core changes:
* Drop useless 'depends on' in Kconfig
* Add an extra level in the Kconfig hierarchy
* Trivial spellings
* Dynamic allocation of the interface configurations
* Dropping the default ONFI timing mode
* Various cleanup (types, structures, naming, comments)
* Hide the chip->data_interface indirection
* Add the generic rb-gpios property
* Add the ->choose_interface_config() hook
* Introduce nand_choose_best_sdr_timings()
* Use default values for tPROG_max and tBERS_max
* Avoid redefining tR_max and tCCS_min
* Add a helper to find the closest ONFI mode
* bcm63xx MTD parsers: simplify CFE detection
Raw NAND controller drivers changes:
* fsl-upm: Deprecation of specific DT properties
* fsl_upm: Driver rework and cleanup in favor of ->exec_op()
* Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use
* brcmnand: ECC error handling on EDU transfers
* brcmnand: Don't default to EDU transfers
* qcom: Set BAM mode only if not set already
* qcom: Avoid write to unavailable register
* gpio: Driver rework in favor of ->exec_op()
* tango: ->exec_op() conversion
* mtk: ->exec_op() conversion
Raw NAND chip drivers changes:
* toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4
* toshiba: Implement ->choose_interface_config() for TC58NVG0S3E
* toshiba: Implement ->choose_interface_config() for TC58TEG5DCLTA00
* hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC
SPI NOR core changes:
* Disable Quad Mode in spi_nor_restore().
* Don't abort BFPT parsing when QER reserved value is used.
* Add support/update capabilities for few flashes.
* Drop s70fl01gs flash: it does not support RDSR(05h) which
is critical for erase/write.
* Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts
during the release cycle.
SPI NOR controller drivers changes:
* Move the cadence-quadspi driver to spi-mem. The series was
taken through the SPI tree. Merge it also in spi-nor/next
to avoid conflicts during the release cycle.
* intel-spi:
- Add new PCI IDs.
- Ignore the Write Disable command, the controller doesn't
support it.
- Fix performance regression.
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Merge tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd updates from Miquel Raynal:
"MTD core changes:
- Spelling
- http to https updates
NAND core changes:
- Drop useless 'depends on' in Kconfig
- Add an extra level in the Kconfig hierarchy
- Trivial spellings
- Dynamic allocation of the interface configurations
- Dropping the default ONFI timing mode
- Various cleanup (types, structures, naming, comments)
- Hide the chip->data_interface indirection
- Add the generic rb-gpios property
- Add the ->choose_interface_config() hook
- Introduce nand_choose_best_sdr_timings()
- Use default values for tPROG_max and tBERS_max
- Avoid redefining tR_max and tCCS_min
- Add a helper to find the closest ONFI mode
- bcm63xx MTD parsers: simplify CFE detection
Raw NAND controller drivers changes:
- fsl-upm: Deprecation of specific DT properties
- fsl_upm: Driver rework and cleanup in favor of ->exec_op()
- Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use
- brcmnand: ECC error handling on EDU transfers
- brcmnand: Don't default to EDU transfers
- qcom: Set BAM mode only if not set already
- qcom: Avoid write to unavailable register
- gpio: Driver rework in favor of ->exec_op()
- tango: ->exec_op() conversion
- mtk: ->exec_op() conversion
Raw NAND chip drivers changes:
- toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4,
TC58NVG0S3E, and TC58TEG5DCLTA00
- hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC
SPI NOR core changes:
- Disable Quad Mode in spi_nor_restore().
- Don't abort BFPT parsing when QER reserved value is used.
- Add support/update capabilities for few flashes.
- Drop s70fl01gs flash: it does not support RDSR(05h) which is
critical for erase/write.
- Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts during
the release cycle.
SPI NOR controller drivers changes:
- Move the cadence-quadspi driver to spi-mem. The series was taken
through the SPI tree. Merge it also in spi-nor/next to avoid
conflicts during the release cycle.
- intel-spi:
- Add new PCI IDs.
- Ignore the Write Disable command, the controller doesn't support
it.
- Fix performance regression"
* tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (79 commits)
MTD: pfow.h: drop a duplicated word
MTD: mtd-abi.h: drop a duplicated word
mtd: rawnand: omap_elm: Replace HTTP links with HTTPS ones
mtd: Replace HTTP links with HTTPS ones
mtd: hyperbus: Replace HTTP links with HTTPS ones
mtd: revert "spi-nor: intel: provide a range for poll_timout"
mtd: spi-nor: update read capabilities for w25q64 and s25fl064k
mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g
mtd: spi-nor: macronix: Add support for mx66u2g45g
mtd: spi-nor: intel-spi: Simulate WRDI command
mtd: spi-nor: Disable the flash quad mode in spi_nor_restore()
mtd: spi-nor: Add capability to disable flash quad mode
mtd: spi-nor: spansion: Remove s70fl01gs from flash_info
mtd: spi-nor: sfdp: do not make invalid quad enable fatal
dt-bindings: mtd: fsl-upm-nand: Deprecate chip-delay and fsl, upm-wait-flags
mtd: rawnand: stm32_fmc2: get resources from parent node
mtd: rawnand: stm32_fmc2: use regmap APIs
memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver
dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation
dt-bindings: mtd: update STM32 FMC2 NAND controller documentation
...
This commit is contained in:
Linus Torvalds
commit
dec1fbbc1d
65 changed files with 2807 additions and 985 deletions
|
|
@ -1,6 +1,6 @@
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|||
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __LINUX_MTD_HYPERBUS_H__
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|
|
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@ -12,6 +12,8 @@
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#include <linux/mtd/mtd.h>
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struct nand_device;
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/**
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* struct nand_memory_organization - Memory organization structure
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* @bits_per_cell: number of bits per NAND cell
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@ -114,11 +116,11 @@ struct nand_page_io_req {
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};
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/**
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* struct nand_ecc_req - NAND ECC requirements
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* struct nand_ecc_props - NAND ECC properties
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* @strength: ECC strength
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* @step_size: ECC step/block size
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* @step_size: Number of bytes per step
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*/
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struct nand_ecc_req {
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struct nand_ecc_props {
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unsigned int strength;
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unsigned int step_size;
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};
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@ -133,8 +135,6 @@ struct nand_bbt {
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unsigned long *cache;
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};
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struct nand_device;
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/**
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* struct nand_ops - NAND operations
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* @erase: erase a specific block. No need to check if the block is bad before
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@ -179,7 +179,7 @@ struct nand_ops {
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struct nand_device {
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struct mtd_info mtd;
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struct nand_memory_organization memorg;
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struct nand_ecc_req eccreq;
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struct nand_ecc_props eccreq;
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struct nand_row_converter rowconv;
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struct nand_bbt bbt;
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const struct nand_ops *ops;
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|
|
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@ -19,7 +19,7 @@
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/* Identification info for LPDDR chip */
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#define PFOW_MANUFACTURER_ID 0x0020
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#define PFOW_DEVICE_ID 0x0022
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/* Address in PFOW where prog buffer can can be found */
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/* Address in PFOW where prog buffer can be found */
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#define PFOW_PROGRAM_BUFFER_OFFSET 0x0040
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/* Size of program buffer in words */
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#define PFOW_PROGRAM_BUFFER_SIZE 0x0042
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|
|
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|
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@ -492,22 +492,22 @@ struct nand_sdr_timings {
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};
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/**
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* enum nand_data_interface_type - NAND interface timing type
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* enum nand_interface_type - NAND interface type
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* @NAND_SDR_IFACE: Single Data Rate interface
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*/
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enum nand_data_interface_type {
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enum nand_interface_type {
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NAND_SDR_IFACE,
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};
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/**
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* struct nand_data_interface - NAND interface timing
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* struct nand_interface_config - NAND interface timing
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* @type: type of the timing
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* @timings: The timing information
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* @timings.mode: Timing mode as defined in the specification
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* @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
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*/
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struct nand_data_interface {
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enum nand_data_interface_type type;
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struct nand_interface_config {
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enum nand_interface_type type;
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struct nand_timings {
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unsigned int mode;
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union {
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@ -521,7 +521,7 @@ struct nand_data_interface {
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* @conf: The data interface
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*/
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static inline const struct nand_sdr_timings *
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nand_get_sdr_timings(const struct nand_data_interface *conf)
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nand_get_sdr_timings(const struct nand_interface_config *conf)
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{
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if (conf->type != NAND_SDR_IFACE)
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return ERR_PTR(-EINVAL);
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|
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@ -944,11 +944,10 @@ static inline void nand_op_trace(const char *prefix,
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* This method replaces chip->legacy.cmdfunc(),
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* chip->legacy.{read,write}_{buf,byte,word}(),
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* chip->legacy.dev_ready() and chip->legacy.waifunc().
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* @setup_data_interface: setup the data interface and timing. If
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* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
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* means the configuration should not be applied but
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* only checked.
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* This hook is optional.
|
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* @setup_interface: setup the data interface and timing. If chipnr is set to
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* %NAND_DATA_IFACE_CHECK_ONLY this means the configuration
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* should not be applied but only checked.
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* This hook is optional.
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*/
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struct nand_controller_ops {
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int (*attach_chip)(struct nand_chip *chip);
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|
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@ -956,8 +955,8 @@ struct nand_controller_ops {
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int (*exec_op)(struct nand_chip *chip,
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const struct nand_operation *op,
|
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bool check_only);
|
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int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
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const struct nand_data_interface *conf);
|
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int (*setup_interface)(struct nand_chip *chip, int chipnr,
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const struct nand_interface_config *conf);
|
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};
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/**
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@ -1028,140 +1027,138 @@ struct nand_legacy {
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};
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|
||||
/**
|
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* struct nand_chip - NAND Private Flash Chip Data
|
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* @base: Inherit from the generic NAND device
|
||||
* @legacy: All legacy fields/hooks. If you develop a new driver,
|
||||
* don't even try to use any of these fields/hooks, and if
|
||||
* you're modifying an existing driver that is using those
|
||||
* fields/hooks, you should consider reworking the driver
|
||||
* avoid using them.
|
||||
* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
|
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* setting the read-retry mode. Mostly needed for MLC NAND.
|
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* @ecc: [BOARDSPECIFIC] ECC control structure
|
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* @buf_align: minimum buffer alignment required by a platform
|
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* @oob_poi: "poison value buffer," used for laying out OOB data
|
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* before writing
|
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* @page_shift: [INTERN] number of address bits in a page (column
|
||||
* address bits).
|
||||
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
||||
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
||||
* @chip_shift: [INTERN] number of address bits in one chip
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly
|
||||
* be set to inform nand_scan about special functionality.
|
||||
* See the defines for further explanation.
|
||||
* @bbt_options: [INTERN] bad block specific options. All options used
|
||||
* here must come from bbm.h. By default, these options
|
||||
* will be copied to the appropriate nand_bbt_descr's.
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob
|
||||
* area.
|
||||
* @badblockbits: [INTERN] minimum number of set bits in a good block's
|
||||
* bad block marker position; i.e., BBM == 11110111b is
|
||||
* not bad when badblockbits == 7
|
||||
* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
|
||||
* set to the actually used ONFI mode if the chip is
|
||||
* ONFI compliant or deduced from the datasheet if
|
||||
* the NAND chip is not ONFI compliant.
|
||||
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
||||
* @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
|
||||
* @pagecache: Structure containing page cache related fields
|
||||
* @pagecache.bitflips: Number of bitflips of the cached page
|
||||
* @pagecache.page: Page number currently in the cache. -1 means no page is
|
||||
* currently cached
|
||||
* @subpagesize: [INTERN] holds the subpagesize
|
||||
* @id: [INTERN] holds NAND ID
|
||||
* @parameters: [INTERN] holds generic parameters under an easily
|
||||
* readable form.
|
||||
* @data_interface: [INTERN] NAND interface timing information
|
||||
* @cur_cs: currently selected target. -1 means no target selected,
|
||||
* otherwise we should always have cur_cs >= 0 &&
|
||||
* cur_cs < nanddev_ntargets(). NAND Controller drivers
|
||||
* should not modify this value, but they're allowed to
|
||||
* read it.
|
||||
* @read_retries: [INTERN] the number of read retry modes supported
|
||||
* @lock: lock protecting the suspended field. Also used to
|
||||
* serialize accesses to the NAND device.
|
||||
* @suspended: set to 1 when the device is suspended, 0 when it's not.
|
||||
* @suspend: [REPLACEABLE] specific NAND device suspend operation
|
||||
* @resume: [REPLACEABLE] specific NAND device resume operation
|
||||
* @bbt: [INTERN] bad block table pointer
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
|
||||
* lookup.
|
||||
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
|
||||
* bad block scan.
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller
|
||||
* structure which is shared among multiple independent
|
||||
* devices.
|
||||
* @priv: [OPTIONAL] pointer to private chip data
|
||||
* @manufacturer: [INTERN] Contains manufacturer information
|
||||
* @manufacturer.desc: [INTERN] Contains manufacturer's description
|
||||
* @manufacturer.priv: [INTERN] Contains manufacturer private information
|
||||
* @lock_area: [REPLACEABLE] specific NAND chip lock operation
|
||||
* @unlock_area: [REPLACEABLE] specific NAND chip unlock operation
|
||||
* struct nand_chip_ops - NAND chip operations
|
||||
* @suspend: Suspend operation
|
||||
* @resume: Resume operation
|
||||
* @lock_area: Lock operation
|
||||
* @unlock_area: Unlock operation
|
||||
* @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
|
||||
* @choose_interface_config: Choose the best interface configuration
|
||||
*/
|
||||
struct nand_chip_ops {
|
||||
int (*suspend)(struct nand_chip *chip);
|
||||
void (*resume)(struct nand_chip *chip);
|
||||
int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
|
||||
int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
|
||||
int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
|
||||
int (*choose_interface_config)(struct nand_chip *chip,
|
||||
struct nand_interface_config *iface);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nand_manufacturer - NAND manufacturer structure
|
||||
* @desc: The manufacturer description
|
||||
* @priv: Private information for the manufacturer driver
|
||||
*/
|
||||
struct nand_manufacturer {
|
||||
const struct nand_manufacturer_desc *desc;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nand_chip - NAND Private Flash Chip Data
|
||||
* @base: Inherit from the generic NAND device
|
||||
* @id: Holds NAND ID
|
||||
* @parameters: Holds generic parameters under an easily readable form
|
||||
* @manufacturer: Manufacturer information
|
||||
* @ops: NAND chip operations
|
||||
* @legacy: All legacy fields/hooks. If you develop a new driver, don't even try
|
||||
* to use any of these fields/hooks, and if you're modifying an
|
||||
* existing driver that is using those fields/hooks, you should
|
||||
* consider reworking the driver and avoid using them.
|
||||
* @options: Various chip options. They can partly be set to inform nand_scan
|
||||
* about special functionality. See the defines for further
|
||||
* explanation.
|
||||
* @current_interface_config: The currently used NAND interface configuration
|
||||
* @best_interface_config: The best NAND interface configuration which fits both
|
||||
* the NAND chip and NAND controller constraints. If
|
||||
* unset, the default reset interface configuration must
|
||||
* be used.
|
||||
* @bbt_erase_shift: Number of address bits in a bbt entry
|
||||
* @bbt_options: Bad block table specific options. All options used here must
|
||||
* come from bbm.h. By default, these options will be copied to
|
||||
* the appropriate nand_bbt_descr's.
|
||||
* @badblockpos: Bad block marker position in the oob area
|
||||
* @badblockbits: Minimum number of set bits in a good block's bad block marker
|
||||
* position; i.e., BBM = 11110111b is good when badblockbits = 7
|
||||
* @bbt_td: Bad block table descriptor for flash lookup
|
||||
* @bbt_md: Bad block table mirror descriptor
|
||||
* @badblock_pattern: Bad block scan pattern used for initial bad block scan
|
||||
* @bbt: Bad block table pointer
|
||||
* @page_shift: Number of address bits in a page (column address bits)
|
||||
* @phys_erase_shift: Number of address bits in a physical eraseblock
|
||||
* @chip_shift: Number of address bits in one chip
|
||||
* @pagemask: Page number mask = number of (pages / chip) - 1
|
||||
* @subpagesize: Holds the subpagesize
|
||||
* @data_buf: Buffer for data, size is (page size + oobsize)
|
||||
* @oob_poi: pointer on the OOB area covered by data_buf
|
||||
* @pagecache: Structure containing page cache related fields
|
||||
* @pagecache.bitflips: Number of bitflips of the cached page
|
||||
* @pagecache.page: Page number currently in the cache. -1 means no page is
|
||||
* currently cached
|
||||
* @buf_align: Minimum buffer alignment required by a platform
|
||||
* @lock: Lock protecting the suspended field. Also used to serialize accesses
|
||||
* to the NAND device
|
||||
* @suspended: Set to 1 when the device is suspended, 0 when it's not
|
||||
* @cur_cs: Currently selected target. -1 means no target selected, otherwise we
|
||||
* should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
|
||||
* NAND Controller drivers should not modify this value, but they're
|
||||
* allowed to read it.
|
||||
* @read_retries: The number of read retry modes supported
|
||||
* @controller: The hardware controller structure which is shared among multiple
|
||||
* independent devices
|
||||
* @ecc: The ECC controller structure
|
||||
* @priv: Chip private data
|
||||
*/
|
||||
struct nand_chip {
|
||||
struct nand_device base;
|
||||
|
||||
struct nand_id id;
|
||||
struct nand_parameters parameters;
|
||||
struct nand_manufacturer manufacturer;
|
||||
struct nand_chip_ops ops;
|
||||
struct nand_legacy legacy;
|
||||
|
||||
int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
|
||||
|
||||
unsigned int options;
|
||||
|
||||
/* Data interface */
|
||||
const struct nand_interface_config *current_interface_config;
|
||||
struct nand_interface_config *best_interface_config;
|
||||
|
||||
/* Bad block information */
|
||||
unsigned int bbt_erase_shift;
|
||||
unsigned int bbt_options;
|
||||
unsigned int badblockpos;
|
||||
unsigned int badblockbits;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
u8 *bbt;
|
||||
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int pagemask;
|
||||
/* Device internal layout */
|
||||
unsigned int page_shift;
|
||||
unsigned int phys_erase_shift;
|
||||
unsigned int chip_shift;
|
||||
unsigned int pagemask;
|
||||
unsigned int subpagesize;
|
||||
|
||||
/* Buffers */
|
||||
u8 *data_buf;
|
||||
|
||||
u8 *oob_poi;
|
||||
struct {
|
||||
unsigned int bitflips;
|
||||
int page;
|
||||
} pagecache;
|
||||
|
||||
int subpagesize;
|
||||
int onfi_timing_mode_default;
|
||||
unsigned int badblockpos;
|
||||
int badblockbits;
|
||||
|
||||
struct nand_id id;
|
||||
struct nand_parameters parameters;
|
||||
|
||||
struct nand_data_interface data_interface;
|
||||
|
||||
int cur_cs;
|
||||
|
||||
int read_retries;
|
||||
|
||||
struct mutex lock;
|
||||
unsigned int suspended : 1;
|
||||
int (*suspend)(struct nand_chip *chip);
|
||||
void (*resume)(struct nand_chip *chip);
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_controller *controller;
|
||||
|
||||
struct nand_ecc_ctrl ecc;
|
||||
unsigned long buf_align;
|
||||
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
/* Internals */
|
||||
struct mutex lock;
|
||||
unsigned int suspended : 1;
|
||||
int cur_cs;
|
||||
int read_retries;
|
||||
|
||||
/* Externals */
|
||||
struct nand_controller *controller;
|
||||
struct nand_ecc_ctrl ecc;
|
||||
void *priv;
|
||||
|
||||
struct {
|
||||
const struct nand_manufacturer *desc;
|
||||
void *priv;
|
||||
} manufacturer;
|
||||
|
||||
int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
|
||||
int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
|
||||
};
|
||||
|
||||
extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
|
||||
|
|
@ -1209,6 +1206,17 @@ static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
|
|||
return mtd_get_of_node(nand_to_mtd(chip));
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_get_interface_config - Retrieve the current interface configuration
|
||||
* of a NAND chip
|
||||
* @chip: The NAND chip
|
||||
*/
|
||||
static inline const struct nand_interface_config *
|
||||
nand_get_interface_config(struct nand_chip *chip)
|
||||
{
|
||||
return chip->current_interface_config;
|
||||
}
|
||||
|
||||
/*
|
||||
* A helper for defining older NAND chips where the second ID byte fully
|
||||
* defined the chip, including the geometry (chip size, eraseblock size, page
|
||||
|
|
@ -1261,10 +1269,6 @@ static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
|
|||
* @ecc_step_ds in nand_chip{}, also from the datasheet.
|
||||
* For example, the "4bit ECC for each 512Byte" can be set with
|
||||
* NAND_ECC_INFO(4, 512).
|
||||
* @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
|
||||
* reset. Should be deduced from timings described
|
||||
* in the datasheet.
|
||||
*
|
||||
*/
|
||||
struct nand_flash_dev {
|
||||
char *name;
|
||||
|
|
@ -1285,7 +1289,6 @@ struct nand_flash_dev {
|
|||
uint16_t strength_ds;
|
||||
uint16_t step_ds;
|
||||
} ecc;
|
||||
int onfi_timing_mode_default;
|
||||
};
|
||||
|
||||
int nand_create_bbt(struct nand_chip *chip);
|
||||
|
|
|
|||
|
|
@ -309,7 +309,7 @@ struct spinand_info {
|
|||
struct spinand_devid devid;
|
||||
u32 flags;
|
||||
struct nand_memory_organization memorg;
|
||||
struct nand_ecc_req eccreq;
|
||||
struct nand_ecc_props eccreq;
|
||||
struct spinand_ecc_info eccinfo;
|
||||
struct {
|
||||
const struct spinand_op_variants *read_cache;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue