Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull IRQ chip updates from Ingo Molnar:
"A late irqchips update:
- New TI INTR/INTA set of drivers
- Rewrite of the stm32mp1-exti driver as a platform driver
- Update the IOMMU MSI mapping API to be RT friendly
- A number of cleanups and other low impact fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits)
iommu/dma-iommu: Remove iommu_dma_map_msi_msg()
irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg()
irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg()
irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg()
irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg()
iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts
genirq/msi: Add a new field in msi_desc to store an IOMMU cookie
arm64: arch_k3: Enable interrupt controller drivers
irqchip/ti-sci-inta: Add msi domain support
soc: ti: Add MSI domain bus support for Interrupt Aggregator
irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip/ti-sci-intr: Add support for Interrupt Router driver
dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
gpio: thunderx: Use the default parent apis for {request,release}_resources
genirq: Introduce irq_chip_{request,release}_resource_parent() apis
firmware: ti_sci: Add helper apis to manage resources
firmware: ti_sci: Add RM mapping table for am654
firmware: ti_sci: Add support for IRQ management
firmware: ti_sci: Add support for RM core ops
...
This commit is contained in:
Linus Torvalds
commit
d9351ea14d
38 changed files with 2510 additions and 228 deletions
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@ -71,12 +71,25 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir, unsigned long attrs);
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/* The DMA API isn't _quite_ the whole story, though... */
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void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg);
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/*
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* iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device
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*
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* The MSI page will be stored in @desc.
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*
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* Return: 0 on success otherwise an error describing the failure.
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*/
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int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
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/* Update the MSI message if required. */
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void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg);
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void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
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#else
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struct iommu_domain;
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struct msi_desc;
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struct msi_msg;
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struct device;
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@ -99,7 +112,14 @@ static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
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{
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}
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static inline void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg)
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static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
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phys_addr_t msi_addr)
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{
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return 0;
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}
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static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg)
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{
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}
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@ -625,6 +625,8 @@ extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
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extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
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void *vcpu_info);
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extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
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extern int irq_chip_request_resources_parent(struct irq_data *data);
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extern void irq_chip_release_resources_parent(struct irq_data *data);
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#endif
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/* Handling of unhandled and spurious interrupts: */
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@ -165,7 +165,7 @@
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#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
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#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
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#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)
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#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
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#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
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#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
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@ -192,7 +192,7 @@
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#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
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#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
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#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)
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#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
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#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
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#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
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@ -251,7 +251,7 @@
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#define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
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#define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
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#define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
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#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
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#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb)
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#define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
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#define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
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#define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
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@ -277,7 +277,7 @@
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#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
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#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
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#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
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#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
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#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb)
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#define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
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#define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
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#define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
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@ -351,7 +351,7 @@
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#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
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#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
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#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb)
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#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
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#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
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#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
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@ -377,7 +377,7 @@
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#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
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#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
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#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)
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#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
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#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
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#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
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@ -82,6 +82,7 @@ enum irq_domain_bus_token {
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DOMAIN_BUS_NEXUS,
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DOMAIN_BUS_IPI,
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DOMAIN_BUS_FSL_MC_MSI,
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DOMAIN_BUS_TI_SCI_INTA_MSI,
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};
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/**
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@ -47,6 +47,14 @@ struct fsl_mc_msi_desc {
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u16 msi_index;
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};
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/**
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* ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
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* @dev_index: TISCI device index
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*/
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struct ti_sci_inta_msi_desc {
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u16 dev_index;
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};
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/**
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* struct msi_desc - Descriptor structure for MSI based interrupts
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* @list: List head for management
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@ -68,6 +76,7 @@ struct fsl_mc_msi_desc {
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* @mask_base: [PCI MSI-X] Mask register base address
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* @platform: [platform] Platform device specific msi descriptor data
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* @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
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* @inta: [INTA] TISCI based INTA specific msi descriptor data
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*/
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struct msi_desc {
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/* Shared device/bus type independent data */
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@ -77,6 +86,9 @@ struct msi_desc {
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struct device *dev;
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struct msi_msg msg;
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struct irq_affinity_desc *affinity;
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#ifdef CONFIG_IRQ_MSI_IOMMU
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const void *iommu_cookie;
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#endif
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union {
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/* PCI MSI/X specific data */
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@ -106,6 +118,7 @@ struct msi_desc {
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*/
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struct platform_msi_desc platform;
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struct fsl_mc_msi_desc fsl_mc;
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struct ti_sci_inta_msi_desc inta;
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};
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};
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@ -119,6 +132,29 @@ struct msi_desc {
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#define for_each_msi_entry_safe(desc, tmp, dev) \
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list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)
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#ifdef CONFIG_IRQ_MSI_IOMMU
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static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
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{
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return desc->iommu_cookie;
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}
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static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
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const void *iommu_cookie)
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{
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desc->iommu_cookie = iommu_cookie;
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}
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#else
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static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
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{
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return NULL;
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}
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static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
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const void *iommu_cookie)
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{
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}
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#endif
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#ifdef CONFIG_PCI_MSI
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#define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
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#define for_each_pci_msi_entry(desc, pdev) \
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23
include/linux/soc/ti/ti_sci_inta_msi.h
Normal file
23
include/linux/soc/ti/ti_sci_inta_msi.h
Normal file
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Texas Instruments' K3 TI SCI INTA MSI helper
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*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
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#define __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
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#include <linux/msi.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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struct irq_domain
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*ti_sci_inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info,
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struct irq_domain *parent);
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int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev,
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struct ti_sci_resource *res);
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unsigned int ti_sci_inta_msi_get_virq(struct device *dev, u32 index);
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void ti_sci_inta_msi_domain_free_irqs(struct device *dev);
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#endif /* __INCLUDE_LINUX_IRQCHIP_TI_SCI_INTA_H */
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@ -192,15 +192,68 @@ struct ti_sci_clk_ops {
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u64 *current_freq);
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};
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/**
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* struct ti_sci_rm_core_ops - Resource management core operations
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* @get_range: Get a range of resources belonging to ti sci host.
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* @get_rage_from_shost: Get a range of resources belonging to
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* specified host id.
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* - s_host: Host processing entity to which the
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* resources are allocated
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*
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* NOTE: for these functions, all the parameters are consolidated and defined
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* as below:
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* - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
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* - dev_id: TISCI device ID.
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* - subtype: Resource assignment subtype that is being requested
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* from the given device.
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* - range_start: Start index of the resource range
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* - range_end: Number of resources in the range
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*/
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struct ti_sci_rm_core_ops {
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int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
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u8 subtype, u16 *range_start, u16 *range_num);
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int (*get_range_from_shost)(const struct ti_sci_handle *handle,
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u32 dev_id, u8 subtype, u8 s_host,
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u16 *range_start, u16 *range_num);
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};
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/**
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* struct ti_sci_rm_irq_ops: IRQ management operations
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* @set_irq: Set an IRQ route between the requested source
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* and destination
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* @set_event_map: Set an Event based peripheral irq to Interrupt
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* Aggregator.
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* @free_irq: Free an an IRQ route between the requested source
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* destination.
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* @free_event_map: Free an event based peripheral irq to Interrupt
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* Aggregator.
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*/
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struct ti_sci_rm_irq_ops {
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int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
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u16 src_index, u16 dst_id, u16 dst_host_irq);
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int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
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u16 src_index, u16 ia_id, u16 vint,
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u16 global_event, u8 vint_status_bit);
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int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
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u16 src_index, u16 dst_id, u16 dst_host_irq);
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int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
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u16 src_index, u16 ia_id, u16 vint,
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u16 global_event, u8 vint_status_bit);
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};
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/**
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* struct ti_sci_ops - Function support for TI SCI
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* @dev_ops: Device specific operations
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* @clk_ops: Clock specific operations
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* @rm_core_ops: Resource management core operations.
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* @rm_irq_ops: IRQ management specific operations
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*/
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struct ti_sci_ops {
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struct ti_sci_core_ops core_ops;
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struct ti_sci_dev_ops dev_ops;
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struct ti_sci_clk_ops clk_ops;
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struct ti_sci_rm_core_ops rm_core_ops;
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struct ti_sci_rm_irq_ops rm_irq_ops;
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};
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/**
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@ -213,10 +266,47 @@ struct ti_sci_handle {
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struct ti_sci_ops ops;
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};
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#define TI_SCI_RESOURCE_NULL 0xffff
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/**
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* struct ti_sci_resource_desc - Description of TI SCI resource instance range.
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* @start: Start index of the resource.
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* @num: Number of resources.
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* @res_map: Bitmap to manage the allocation of these resources.
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*/
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struct ti_sci_resource_desc {
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u16 start;
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u16 num;
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unsigned long *res_map;
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};
|
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|
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/**
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* struct ti_sci_resource - Structure representing a resource assigned
|
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* to a device.
|
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* @sets: Number of sets available from this resource type
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* @lock: Lock to guard the res map in each set.
|
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* @desc: Array of resource descriptors.
|
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*/
|
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struct ti_sci_resource {
|
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u16 sets;
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raw_spinlock_t lock;
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struct ti_sci_resource_desc *desc;
|
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};
|
||||
|
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#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
|
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const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
|
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int ti_sci_put_handle(const struct ti_sci_handle *handle);
|
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const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
|
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const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
|
||||
const char *property);
|
||||
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
|
||||
const char *property);
|
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u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
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void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
|
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u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
|
||||
struct ti_sci_resource *
|
||||
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
|
||||
struct device *dev, u32 dev_id, char *of_prop);
|
||||
|
||||
#else /* CONFIG_TI_SCI_PROTOCOL */
|
||||
|
||||
|
|
@ -236,6 +326,40 @@ const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
|
|||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
|
||||
const char *property)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
|
||||
const char *property)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
|
||||
{
|
||||
return TI_SCI_RESOURCE_NULL;
|
||||
}
|
||||
|
||||
static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
|
||||
{
|
||||
}
|
||||
|
||||
static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline struct ti_sci_resource *
|
||||
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
|
||||
struct device *dev, u32 dev_id, char *of_prop)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
#endif /* CONFIG_TI_SCI_PROTOCOL */
|
||||
|
||||
#endif /* __TISCI_PROTOCOL_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue