arm64: dts: msm8998: Add SAW, CPRh and CPUFREQ to enable CPU scaling
Add the SAW (SPM), CPR-Hardened, CPUFREQ-HW nodes and relative OPP tables (and also assign them to the CPU nodes, as required) in order to enable CPU scaling on the MSM8998 SoC. The CPR-Hardened and CPUFREQ-HW nodes are disabled by default as to not change the previous default behavior. Since the drivers are not yet accounting for speed-binning, these OPPs are referred to the most common binning for this chip, which I have found on six phones from Sony and one from FxTec (silver bin0, perf bin2). At least until speed-binning gets done in the cpufreq-hw and CPR drivers, users should enable CPR-Hardened and CPUFREQ in their own board DT. This is done like that because these drivers are really big, so the idea is to keep the "base" version easier (but perfectly working), before adding speed-binning "complications", which may... or may not be necessary. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Fixed up for 5.18 & 6.0-rc2 by Jami]
This commit is contained in:
AngeloGioacchino Del Regno
Jami Kettunen
parent
d16cc12bc0
commit
d6ef98825d
1 changed files with 720 additions and 1 deletions
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@ -10,6 +10,15 @@
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/gpio/gpio.h>
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/* Macro for CPR-Hardened OPP entries - Example phandle: cprh_opp0 */
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#define CPRH_OPP_ENTRY(lvl, _fuselevel, _oadj, _cadj) \
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cprh_opp##lvl##: opp-##lvl { \
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opp-level = <lvl>; \
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qcom,opp-fuse-level = <_fuselevel>; \
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qcom,opp-oloop-vadj = <_oadj>; \
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qcom,opp-cloop-vadj = <_cadj>; \
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}
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/ {
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interrupt-parent = <&intc>;
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@ -136,8 +145,13 @@
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&xo>;
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&cpu_silver_opp_table>;
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power-domains = <&apc_cprh 0>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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@ -150,8 +164,13 @@
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reg = <0x0 0x1>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&xo>;
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&cpu_silver_opp_table>;
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power-domains = <&apc_cprh 0>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 0>;
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};
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CPU2: cpu@2 {
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@ -160,8 +179,13 @@
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reg = <0x0 0x2>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&xo>;
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&cpu_silver_opp_table>;
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power-domains = <&apc_cprh 0>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 0>;
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};
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CPU3: cpu@3 {
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@ -170,8 +194,13 @@
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reg = <0x0 0x3>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&xo>;
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&cpu_silver_opp_table>;
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power-domains = <&apc_cprh 0>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 0>;
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};
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CPU4: cpu@100 {
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@ -180,8 +209,13 @@
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1536>;
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clocks = <&xo>;
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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operating-points-v2 = <&cpu_gold_opp_table>;
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power-domains = <&apc_cprh 1>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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@ -194,8 +228,13 @@
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reg = <0x0 0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <1536>;
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clocks = <&xo>;
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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operating-points-v2 = <&cpu_gold_opp_table>;
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power-domains = <&apc_cprh 1>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 1>;
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};
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CPU6: cpu@102 {
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@ -204,8 +243,13 @@
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reg = <0x0 0x102>;
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enable-method = "psci";
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capacity-dmips-mhz = <1536>;
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clocks = <&xo>;
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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operating-points-v2 = <&cpu_gold_opp_table>;
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power-domains = <&apc_cprh 1>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 1>;
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};
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CPU7: cpu@103 {
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@ -214,8 +258,13 @@
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reg = <0x0 0x103>;
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enable-method = "psci";
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capacity-dmips-mhz = <1536>;
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clocks = <&xo>;
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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operating-points-v2 = <&cpu_gold_opp_table>;
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power-domains = <&apc_cprh 1>;
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power-domain-names = "cprh";
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qcom,freq-domain = <&cpufreq_hw 1>;
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};
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cpu-map {
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@ -303,6 +352,378 @@
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};
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};
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cpu_gold_opp_table: cpu-gold-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-2361600000 {
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opp-hz = /bits/ 64 <2361600000>;
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required-opps = <&cprh_opp30>;
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qcom,pll-override = <0x0a620062>;
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qcom,spare-data = <3>;
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};
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opp-2342400000 {
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opp-hz = /bits/ 64 <2342400000>;
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required-opps = <&cprh_opp29>;
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qcom,pll-override = <0x0a620062>;
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qcom,spare-data = <3>;
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};
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opp-2323200000 {
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opp-hz = /bits/ 64 <2323200000>;
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required-opps = <&cprh_opp28>;
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qcom,pll-override = <0x0a610061>;
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qcom,spare-data = <3>;
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};
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opp-2265600000 {
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opp-hz = /bits/ 64 <2265600000>;
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required-opps = <&cprh_opp27>;
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qcom,pll-override = <0x0a5e005e>;
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qcom,spare-data = <3>;
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};
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opp-2208000000 {
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opp-hz = /bits/ 64 <2208000000>;
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required-opps = <&cprh_opp26>;
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qcom,pll-override = <0x0a5c005c>;
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qcom,spare-data = <3>;
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};
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opp-2112000000 {
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opp-hz = /bits/ 64 <2112000000>;
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required-opps = <&cprh_opp25>;
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qcom,pll-override = <0x0a580058>;
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qcom,spare-data = <3>;
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};
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opp-2035200000 {
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opp-hz = /bits/ 64 <2035200000>;
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required-opps = <&cprh_opp24>;
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qcom,pll-override = <0x09550055>;
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qcom,spare-data = <3>;
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};
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opp-1958400000 {
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opp-hz = /bits/ 64 <1958400000>;
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required-opps = <&cprh_opp23>;
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qcom,pll-override = <0x09520052>;
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qcom,spare-data = <2>;
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};
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opp-1881600000 {
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opp-hz = /bits/ 64 <1881600000>;
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required-opps = <&cprh_opp22>;
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qcom,pll-override = <0x094e004e>;
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qcom,spare-data = <2>;
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};
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opp-1804800000 {
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opp-hz = /bits/ 64 <1804800000>;
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required-opps = <&cprh_opp21>;
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qcom,pll-override = <0x084b004b>;
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qcom,spare-data = <2>;
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};
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opp-1728000000 {
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opp-hz = /bits/ 64 <1728000000>;
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required-opps = <&cprh_opp20>;
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qcom,pll-override = <0x08480048>;
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qcom,spare-data = <2>;
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};
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opp-1651200000 {
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opp-hz = /bits/ 64 <1651200000>;
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required-opps = <&cprh_opp19>;
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qcom,pll-override = <0x07450045>;
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qcom,spare-data = <2>;
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};
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opp-1574400000 {
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opp-hz = /bits/ 64 <1574400000>;
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required-opps = <&cprh_opp18>;
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qcom,pll-override = <0x07420042>;
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qcom,spare-data = <2>;
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};
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opp-1497600000 {
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opp-hz = /bits/ 64 <1497600000>;
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required-opps = <&cprh_opp17>;
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qcom,pll-override = <0x073e003e>;
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qcom,spare-data = <2>;
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};
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opp-1420800000 {
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opp-hz = /bits/ 64 <1420800000>;
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required-opps = <&cprh_opp16>;
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qcom,pll-override = <0x063b003b>;
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qcom,spare-data = <2>;
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};
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opp-1344000000 {
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opp-hz = /bits/ 64 <1344000000>;
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required-opps = <&cprh_opp15>;
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qcom,pll-override = <0x06380038>;
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qcom,spare-data = <2>;
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};
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opp-1267200000 {
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opp-hz = /bits/ 64 <1267200000>;
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required-opps = <&cprh_opp14>;
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qcom,pll-override = <0x06350035>;
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qcom,spare-data = <2>;
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};
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opp-1190400000 {
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opp-hz = /bits/ 64 <1190400000>;
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required-opps = <&cprh_opp13>;
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qcom,pll-override = <0x05320032>;
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qcom,spare-data = <2>;
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};
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opp-1132800000 {
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opp-hz = /bits/ 64 <1132800000>;
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required-opps = <&cprh_opp12>;
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qcom,pll-override = <0x052f002f>;
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qcom,spare-data = <1>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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required-opps = <&cprh_opp11>;
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qcom,pll-override = <0x052c002c>;
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qcom,spare-data = <1>;
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};
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opp-979200000 {
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opp-hz = /bits/ 64 <979200000>;
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required-opps = <&cprh_opp10>;
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qcom,pll-override = <0x4290029>;
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qcom,spare-data = <1>;
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};
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opp-902400000 {
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opp-hz = /bits/ 64 <902400000>;
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required-opps = <&cprh_opp9>;
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qcom,pll-override = <0x4260026>;
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qcom,spare-data = <1>;
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};
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opp-806400000 {
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opp-hz = /bits/ 64 <806400000>;
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required-opps = <&cprh_opp8>;
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qcom,pll-override = <0x3200022>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-729600000 {
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opp-hz = /bits/ 64 <729600000>;
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required-opps = <&cprh_opp7>;
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qcom,pll-override = <0x3200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-652800000 {
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opp-hz = /bits/ 64 <652800000>;
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required-opps = <&cprh_opp6>;
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qcom,pll-override = <0x3200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-576000000 {
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opp-hz = /bits/ 64 <576000000>;
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required-opps = <&cprh_opp5>;
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qcom,pll-override = <0x2200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-499200000 {
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opp-hz = /bits/ 64 <499200000>;
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required-opps = <&cprh_opp4>;
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qcom,pll-override = <0x2200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-422400000 {
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opp-hz = /bits/ 64 <422400000>;
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required-opps = <&cprh_opp3>;
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qcom,pll-override = <0x2200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-345600000 {
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opp-hz = /bits/ 64 <345600000>;
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required-opps = <&cprh_opp2>;
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qcom,pll-override = <0x1200020>;
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qcom,pll-div = <1>;
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qcom,spare-data = <1>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&cprh_opp1>;
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qcom,pll-override = <0x1200020>;
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qcom,spare-data = <1>;
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};
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};
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cpu_silver_opp_table: cpu-silver-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1900800000 {
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opp-hz = /bits/ 64 <1900800000>;
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required-opps = <&cprh_opp22>;
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qcom,pll-override = <0x094f004f>;
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qcom,spare-data = <3>;
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};
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opp-1824000000 {
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opp-hz = /bits/ 64 <1824000000>;
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required-opps = <&cprh_opp21>;
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qcom,pll-override = <0x084c004c>;
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qcom,spare-data = <3>;
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};
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opp-1747200000 {
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opp-hz = /bits/ 64 <1747200000>;
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required-opps = <&cprh_opp20>;
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qcom,pll-override = <0x08490049>;
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qcom,spare-data = <2>;
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};
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opp-1670400000 {
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opp-hz = /bits/ 64 <1670400000>;
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required-opps = <&cprh_opp19>;
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qcom,pll-override = <0x08460046>;
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qcom,spare-data = <2>;
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};
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opp-1555200000 {
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opp-hz = /bits/ 64 <1555200000>;
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required-opps = <&cprh_opp18>;
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qcom,pll-override = <0x07410041>;
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qcom,spare-data = <2>;
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};
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opp-1478400000 {
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opp-hz = /bits/ 64 <1478400000>;
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required-opps = <&cprh_opp17>;
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qcom,pll-override = <0x073e003e>;
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qcom,spare-data = <2>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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required-opps = <&cprh_opp16>;
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qcom,pll-override = <0x063a003a>;
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qcom,spare-data = <2>;
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};
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opp-1324800000 {
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opp-hz = /bits/ 64 <1324800000>;
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required-opps = <&cprh_opp15>;
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qcom,pll-override = <0x06370037>;
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qcom,spare-data = <2>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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required-opps = <&cprh_opp14>;
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qcom,pll-override = <0x05340034>;
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qcom,spare-data = <2>;
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};
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opp-1171200000 {
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opp-hz = /bits/ 64 <1171200000>;
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required-opps = <&cprh_opp13>;
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qcom,pll-override = <0x05310031>;
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qcom,spare-data = <2>;
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};
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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required-opps = <&cprh_opp12>;
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qcom,pll-override = <0x052e002e>;
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qcom,spare-data = <2>;
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};
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opp-1036800000 {
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opp-hz = /bits/ 64 <1036800000>;
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required-opps = <&cprh_opp11>;
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qcom,pll-override = <0x042b002b>;
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qcom,spare-data = <1>;
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||||
};
|
||||
opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
required-opps = <&cprh_opp10>;
|
||||
qcom,pll-override = <0x4280028>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
required-opps = <&cprh_opp9>;
|
||||
qcom,pll-override = <0x4250025>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-825600000 {
|
||||
opp-hz = /bits/ 64 <825600000>;
|
||||
required-opps = <&cprh_opp8>;
|
||||
qcom,pll-override = <0x3200022>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-748800000 {
|
||||
opp-hz = /bits/ 64 <748800000>;
|
||||
required-opps = <&cprh_opp7>;
|
||||
qcom,pll-override = <0x3200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-672000000 {
|
||||
opp-hz = /bits/ 64 <672000000>;
|
||||
required-opps = <&cprh_opp6>;
|
||||
qcom,pll-override = <0x3200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-595200000 {
|
||||
opp-hz = /bits/ 64 <595200000>;
|
||||
required-opps = <&cprh_opp5>;
|
||||
qcom,pll-override = <0x2200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-518400000 {
|
||||
opp-hz = /bits/ 64 <518400000>;
|
||||
required-opps = <&cprh_opp4>;
|
||||
qcom,pll-override = <0x2200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-441600000 {
|
||||
opp-hz = /bits/ 64 <441600000>;
|
||||
required-opps = <&cprh_opp3>;
|
||||
qcom,pll-override = <0x2200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-364800000 {
|
||||
opp-hz = /bits/ 64 <364800000>;
|
||||
required-opps = <&cprh_opp2>;
|
||||
qcom,pll-override = <0x1200020>;
|
||||
qcom,pll-div = <1>;
|
||||
qcom,spare-data = <1>;
|
||||
};
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&cprh_opp1>;
|
||||
qcom,pll-override = <0x1200020>;
|
||||
};
|
||||
};
|
||||
|
||||
cprh_opp_table: cpr-opp-table {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
CPRH_OPP_ENTRY(1, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(2, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(3, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(4, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(5, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(6, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(7, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(8, 1, 0, 0);
|
||||
CPRH_OPP_ENTRY(9, 2, 0, 0);
|
||||
CPRH_OPP_ENTRY(10, 2, 0, 0);
|
||||
CPRH_OPP_ENTRY(11, 2, 0, 0);
|
||||
CPRH_OPP_ENTRY(12, 3 2, (-12000) (-8000), (-10000) (-10000));
|
||||
CPRH_OPP_ENTRY(13, 3, (-16000) (-16000), (-11000) (-10000));
|
||||
CPRH_OPP_ENTRY(14, 3, (-16000) (-12000), (-12000) (-11000));
|
||||
CPRH_OPP_ENTRY(15, 3, (-12000) (-16000), (-13000) (-12000));
|
||||
CPRH_OPP_ENTRY(16, 3, (-12000) (-16000), (-14000) (-12000));
|
||||
CPRH_OPP_ENTRY(17, 3, (-16000) (-12000), (-14000) (-13000));
|
||||
CPRH_OPP_ENTRY(18, 3, (-16000) (-16000), (-15000) (-14000));
|
||||
CPRH_OPP_ENTRY(19, 4 3, (-20000) (-16000), (-21000) (-14000));
|
||||
CPRH_OPP_ENTRY(20, 4 3, (-24000) (-16000), (-24000) (-15000));
|
||||
CPRH_OPP_ENTRY(21, 4, (-28000) (-24000), (-26000) (-16000));
|
||||
CPRH_OPP_ENTRY(22, 4, (-28000) (-16000), (-28000) (-16000));
|
||||
CPRH_OPP_ENTRY(23, 4, 0 (-20000), 0 (-17000));
|
||||
CPRH_OPP_ENTRY(24, 4, 0 (-16000), 0 (-15000));
|
||||
CPRH_OPP_ENTRY(25, 4, 0 (-12000), 0 (-14000));
|
||||
CPRH_OPP_ENTRY(26, 4, 0 (-28000), 0 (-27000));
|
||||
CPRH_OPP_ENTRY(27, 4, 0 (-28000), 0 (-27000));
|
||||
CPRH_OPP_ENTRY(28, 4, 0 (-28000), 0 (-28000));
|
||||
CPRH_OPP_ENTRY(29, 4, 0 (-28000), 0 (-28000));
|
||||
CPRH_OPP_ENTRY(30, 4, 0 (-28000), 0 (-28000));
|
||||
};
|
||||
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm-msm8998", "qcom,scm";
|
||||
|
|
@ -834,7 +1255,7 @@
|
|||
|
||||
qfprom: qfprom@784000 {
|
||||
compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
|
||||
reg = <0x00784000 0x621c>;
|
||||
reg = <0x00784000 0x221c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -842,6 +1263,186 @@
|
|||
reg = <0x23a 0x1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
|
||||
cpr_efuse_speedbin: speedbin@133 {
|
||||
reg = <0x133 0x2>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
|
||||
cpr_fuse_revision: cpr_fusing_rev@13e {
|
||||
reg = <0x13E 0x1>;
|
||||
bits = <3 3>;
|
||||
};
|
||||
|
||||
/* CPR Ring Oscillator: Power Cluster */
|
||||
cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 {
|
||||
reg = <0x219 0x2>;
|
||||
bits = <4 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 {
|
||||
reg = <0x219 0x1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 {
|
||||
reg = <0x218 0x2>;
|
||||
bits = <4 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 {
|
||||
reg = <0x218 0x1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
|
||||
/* CPR Init Voltage: Power Cluster */
|
||||
cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c {
|
||||
reg = <0x21C 0x2>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b {
|
||||
reg = <0x21B 0x2>;
|
||||
bits = <4 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a {
|
||||
reg = <0x21A 0x2>;
|
||||
bits = <6 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a {
|
||||
reg = <0x21A 0x1>;
|
||||
bits = <0 6>;
|
||||
};
|
||||
|
||||
/* CPR Target Quotients: Power Cluster */
|
||||
cpr_quot0_pwrcl: quot0_pwrcl@222 {
|
||||
reg = <0x222 0x3>;
|
||||
bits = <2 12>;
|
||||
};
|
||||
|
||||
cpr_quot1_pwrcl: quot1_pwrcl@220 {
|
||||
reg = <0x220 0x3>;
|
||||
bits = <6 12>;
|
||||
};
|
||||
|
||||
cpr_quot2_pwrcl: quot2_pwrcl@21f {
|
||||
reg = <0x21F 0x2>;
|
||||
bits = <2 11>;
|
||||
};
|
||||
|
||||
cpr_quot3_pwrcl: quot3_pwrcl@21d {
|
||||
reg = <0x21D 0x3>;
|
||||
bits = <6 12>;
|
||||
};
|
||||
|
||||
/* CPR Quotient Offsets: Power Cluster */
|
||||
cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 {
|
||||
reg = <0x227 0x2>;
|
||||
bits = <7 6>;
|
||||
};
|
||||
|
||||
cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 {
|
||||
reg = <0x227 0x1>;
|
||||
bits = <0 7>;
|
||||
};
|
||||
|
||||
cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 {
|
||||
reg = <0x226 0x2>;
|
||||
bits = <1 7>;
|
||||
};
|
||||
|
||||
/* CPR Aging Quotient Offsets: Power Cluster */
|
||||
cpr_aging_quot_off_pwrcl: qoff_aging_pwrcl@228 {
|
||||
reg = <0x228 0x2>;
|
||||
bits = <6 8>;
|
||||
};
|
||||
|
||||
/* CPR Ring Oscillator: Performance Cluster */
|
||||
cpr_ro_sel0_perfcl: rosel0_perfcl@22b {
|
||||
reg = <0x22B 0x1>;
|
||||
bits = <2 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel1_perfcl: rosel1_perfcl@22a {
|
||||
reg = <0x22A 0x2>;
|
||||
bits = <6 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel2_perfcl: rosel2_perfcl@22a {
|
||||
reg = <0x22A 0x1>;
|
||||
bits = <2 4>;
|
||||
};
|
||||
|
||||
cpr_ro_sel3_perfcl: rosel3_perfcl@229 {
|
||||
reg = <0x229 0x2>;
|
||||
bits = <6 4>;
|
||||
};
|
||||
|
||||
/* CPR Init Voltage: Performance Cluster */
|
||||
cpr_init_voltage0_perfcl: ivolt0_perfcl@22e {
|
||||
reg = <0x22E 0x1>;
|
||||
bits = <0 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage1_perfcl: ivolt1_perfcl@22d {
|
||||
reg = <0x22D 0x2>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage2_perfcl: ivolt2_perfcl@22c {
|
||||
reg = <0x22C 0x2>;
|
||||
bits = <4 6>;
|
||||
};
|
||||
|
||||
cpr_init_voltage3_perfcl: ivolt3_perfcl@22b {
|
||||
reg = <0x22B 0x2>;
|
||||
bits = <6 6>;
|
||||
};
|
||||
|
||||
/* CPR Target Quotients: Performance Cluster */
|
||||
cpr_quot0_perfcl: quot0_perfcl@234 {
|
||||
reg = <0x234 0x2>;
|
||||
bits = <0 12>;
|
||||
};
|
||||
|
||||
cpr_quot1_perfcl: quot1_perfcl@232 {
|
||||
reg = <0x232 0x2>;
|
||||
bits = <4 12>;
|
||||
};
|
||||
|
||||
cpr_quot2_perfcl: quot2_perfcl@231 {
|
||||
reg = <0x231 0x2>;
|
||||
bits = <0 12>;
|
||||
};
|
||||
|
||||
cpr_quot3_perfcl: quot3_perfcl@22f {
|
||||
reg = <0x22F 0x2>;
|
||||
bits = <4 11>;
|
||||
};
|
||||
|
||||
/* CPR Quotient Offsets: Performance Cluster */
|
||||
cpr_quot_offset1_perfcl: qoff1_perfcl@239 {
|
||||
reg = <0x239 0x2>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
|
||||
cpr_quot_offset2_perfcl: qoff2_perfcl@238 {
|
||||
reg = <0x238 0x2>;
|
||||
bits = <6 7>;
|
||||
};
|
||||
|
||||
cpr_quot_offset3_perfcl: qoff3_perfcl@237 {
|
||||
reg = <0x237 0x2>;
|
||||
bits = <7 7>;
|
||||
};
|
||||
|
||||
/* CPR Aging Quotient Offsets: Performance Cluster */
|
||||
cpr_aging_quot_off_perfcl: qoff_aging_perfcl@23b {
|
||||
reg = <0x23b 0x2>;
|
||||
bits = <1 8>;
|
||||
};
|
||||
};
|
||||
|
||||
bimc: interconnect@1008000 {
|
||||
|
|
@ -2844,6 +3445,38 @@
|
|||
clocks = <&xo>, <&xo>;
|
||||
};
|
||||
|
||||
power-controller@17812000 {
|
||||
compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
|
||||
"qcom,saw2";
|
||||
reg = <0x017812000 0x1000>;
|
||||
};
|
||||
|
||||
power-controller@17912000 {
|
||||
compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
|
||||
"qcom,saw2";
|
||||
reg = <0x017912000 0x1000>;
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq_hw@17814800 {
|
||||
compatible = "qcom,cpufreq-hw-8998";
|
||||
reg = <0x017914800 0x100>, <0x017814800 0x100>,
|
||||
<0x0179c0000 0x1000>, <0x0179c1000 0x1000>,
|
||||
<0x0179c2000 0x1000>, <0x0179c3000 0x1000>;
|
||||
reg-names = "osm-acd0", "osm-acd1",
|
||||
"osm-domain0", "freq-domain0",
|
||||
"osm-domain1", "freq-domain1";
|
||||
|
||||
assigned-clocks = <&gcc HMSS_GPLL0_CLK_SRC>;
|
||||
assigned-clock-rates = <300000000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
||||
<&gcc HMSS_GPLL0_CLK_SRC>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apcs_glb: mailbox@17911000 {
|
||||
compatible = "qcom,msm8998-apcs-hmss-global";
|
||||
reg = <0x17911000 0x1000>;
|
||||
|
|
@ -2909,6 +3542,92 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* Gold and Silver cluster */
|
||||
apc_cprh: power-controller@179c8000 {
|
||||
compatible = "qcom,msm8998-cprh";
|
||||
reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
|
||||
|
||||
assigned-clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
operating-points-v2 = <&cprh_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDCX_AO>;
|
||||
#power-domain-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
nvmem-cells = <&cpr_efuse_speedbin>,
|
||||
<&cpr_fuse_revision>,
|
||||
<&cpr_quot0_pwrcl>,
|
||||
<&cpr_quot1_pwrcl>,
|
||||
<&cpr_quot2_pwrcl>,
|
||||
<&cpr_quot3_pwrcl>,
|
||||
<&cpr_quot_offset1_pwrcl>,
|
||||
<&cpr_quot_offset2_pwrcl>,
|
||||
<&cpr_quot_offset3_pwrcl>,
|
||||
<&cpr_init_voltage0_pwrcl>,
|
||||
<&cpr_init_voltage1_pwrcl>,
|
||||
<&cpr_init_voltage2_pwrcl>,
|
||||
<&cpr_init_voltage3_pwrcl>,
|
||||
<&cpr_ro_sel0_pwrcl>,
|
||||
<&cpr_ro_sel1_pwrcl>,
|
||||
<&cpr_ro_sel2_pwrcl>,
|
||||
<&cpr_ro_sel3_pwrcl>,
|
||||
<&cpr_aging_quot_off_pwrcl>,
|
||||
<&cpr_quot0_perfcl>,
|
||||
<&cpr_quot1_perfcl>,
|
||||
<&cpr_quot2_perfcl>,
|
||||
<&cpr_quot3_perfcl>,
|
||||
<&cpr_quot_offset1_perfcl>,
|
||||
<&cpr_quot_offset2_perfcl>,
|
||||
<&cpr_quot_offset3_perfcl>,
|
||||
<&cpr_init_voltage0_perfcl>,
|
||||
<&cpr_init_voltage1_perfcl>,
|
||||
<&cpr_init_voltage2_perfcl>,
|
||||
<&cpr_init_voltage3_perfcl>,
|
||||
<&cpr_ro_sel0_perfcl>,
|
||||
<&cpr_ro_sel1_perfcl>,
|
||||
<&cpr_ro_sel2_perfcl>,
|
||||
<&cpr_ro_sel3_perfcl>,
|
||||
<&cpr_aging_quot_off_perfcl>;
|
||||
|
||||
nvmem-cell-names = "cpr_speed_bin",
|
||||
"cpr_fuse_revision",
|
||||
"cpr0_quotient1",
|
||||
"cpr0_quotient2",
|
||||
"cpr0_quotient3",
|
||||
"cpr0_quotient4",
|
||||
"cpr0_quotient_offset2",
|
||||
"cpr0_quotient_offset3",
|
||||
"cpr0_quotient_offset4",
|
||||
"cpr0_init_voltage1",
|
||||
"cpr0_init_voltage2",
|
||||
"cpr0_init_voltage3",
|
||||
"cpr0_init_voltage4",
|
||||
"cpr0_ring_osc1",
|
||||
"cpr0_ring_osc2",
|
||||
"cpr0_ring_osc3",
|
||||
"cpr0_ring_osc4",
|
||||
"cpr0_aging_quotient",
|
||||
"cpr1_quotient1",
|
||||
"cpr1_quotient2",
|
||||
"cpr1_quotient3",
|
||||
"cpr1_quotient4",
|
||||
"cpr1_quotient_offset2",
|
||||
"cpr1_quotient_offset3",
|
||||
"cpr1_quotient_offset4",
|
||||
"cpr1_init_voltage1",
|
||||
"cpr1_init_voltage2",
|
||||
"cpr1_init_voltage3",
|
||||
"cpr1_init_voltage4",
|
||||
"cpr1_ring_osc1",
|
||||
"cpr1_ring_osc2",
|
||||
"cpr1_ring_osc3",
|
||||
"cpr1_ring_osc4",
|
||||
"cpr1_aging_quotient";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x17a00000 0x10000>, /* GICD */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue