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usb: phy: msm: Correct USB PHY Reset sequence for newer platform

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On few legacy platforms, USB PHY is having dedicated reset clk.
It is used to reset USB PHY after putting USB PHY into low power
mode and for calibration of USB PHY. Putting USB PHY into low
power mode is causing ulpi read/write timeout as expected. USB PHY
reset clk is not available on newer platform.

For 28nm PHY, reset USB PHY after resetting USB LINK.
Also reset USB PHY using USB_PHY_PON bit with USB_OTG_HS_PHY_CTRL
register after programming USB PHY Override registers as suggested
with hardware programming guidelines.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Tim Bird <tim.bird@sonymobile.com>
Cc: Mayank Rana <mrana@codeaurora.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Ivan T. Ivanov 2014-04-28 16:34:18 +03:00 • committed by Felipe Balbi
parent cfa3ff5dfe
commit d69c6f5df3
2 changed files with 94 additions and 53 deletions
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5
include/linux/usb/msm_hsusb_hw.h
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@ -42,9 +42,14 @@
#define ULPI_DATA(n) ((n) & 255)
#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
/* synopsys 28nm phy registers */
#define ULPI_PWR_CLK_MNG_REG 0x88
#define OTG_COMP_DISABLE BIT(0)
#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */
#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */
#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */
#define PHY_POR_ASSERT (1 << 0) /* USB2 28nm PHY POR ASSERT */
/* OTG definitions */
#define OTGSC_INTSTS_MASK (0x7f << 16)