kybaaz/linux-xiaomi-chiron
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Merge airlied/drm-next into drm-misc-next

Browse source 
Backmerge 4.15 and hdcp topic branch

Signed-off-by: Sean Paul <seanpaul@chromium.org>
This commit is contained in:
Sean Paul 2018-02-16 15:47:43 -05:00
commit d4da404f36
10586 changed files with 442860 additions and 211688 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/acpi/acbuffer.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

6
include/acpi/acconfig.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -145,9 +145,9 @@
#define ACPI_ADDRESS_RANGE_MAX 2
/* Maximum number of While() loops before abort */
/* Maximum time (default 30s) of While() loops before abort */
#define ACPI_MAX_LOOP_COUNT 0x000FFFFF
#define ACPI_MAX_LOOP_TIMEOUT 30
/******************************************************************************
*

14
include/acpi/acexcep.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -130,8 +130,9 @@ struct acpi_exception_info {
#define AE_HEX_OVERFLOW EXCEP_ENV (0x0020)
#define AE_DECIMAL_OVERFLOW EXCEP_ENV (0x0021)
#define AE_OCTAL_OVERFLOW EXCEP_ENV (0x0022)
#define AE_END_OF_TABLE EXCEP_ENV (0x0023)
#define AE_CODE_ENV_MAX 0x0022
#define AE_CODE_ENV_MAX 0x0023
/*
* Programmer exceptions
@ -195,7 +196,7 @@ struct acpi_exception_info {
#define AE_AML_CIRCULAR_REFERENCE EXCEP_AML (0x001E)
#define AE_AML_BAD_RESOURCE_LENGTH EXCEP_AML (0x001F)
#define AE_AML_ILLEGAL_ADDRESS EXCEP_AML (0x0020)
#define AE_AML_INFINITE_LOOP EXCEP_AML (0x0021)
#define AE_AML_LOOP_TIMEOUT EXCEP_AML (0x0021)
#define AE_AML_UNINITIALIZED_NODE EXCEP_AML (0x0022)
#define AE_AML_TARGET_TYPE EXCEP_AML (0x0023)
@ -275,7 +276,8 @@ static const struct acpi_exception_info acpi_gbl_exception_names_env[] = {
EXCEP_TXT("AE_DECIMAL_OVERFLOW",
"Overflow during ASCII decimal-to-binary conversion"),
EXCEP_TXT("AE_OCTAL_OVERFLOW",
"Overflow during ASCII octal-to-binary conversion")
"Overflow during ASCII octal-to-binary conversion"),
EXCEP_TXT("AE_END_OF_TABLE", "Reached the end of table")
};
static const struct acpi_exception_info acpi_gbl_exception_names_pgm[] = {
@ -368,8 +370,8 @@ static const struct acpi_exception_info acpi_gbl_exception_names_aml[] = {
"The length of a Resource Descriptor in the AML is incorrect"),
EXCEP_TXT("AE_AML_ILLEGAL_ADDRESS",
"A memory, I/O, or PCI configuration address is invalid"),
EXCEP_TXT("AE_AML_INFINITE_LOOP",
"An apparent infinite AML While loop, method was aborted"),
EXCEP_TXT("AE_AML_LOOP_TIMEOUT",
"An AML While loop exceeded the maximum execution time"),
EXCEP_TXT("AE_AML_UNINITIALIZED_NODE",
"A namespace node is uninitialized or unresolved"),
EXCEP_TXT("AE_AML_TARGET_TYPE",

2
include/acpi/acnames.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/acoutput.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/acpi.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

3
include/acpi/acpi_bus.h
View file

@ -91,6 +91,9 @@ acpi_evaluate_dsm_typed(acpi_handle handle, const guid_t *guid, u64 rev,
bool acpi_dev_found(const char *hid);
bool acpi_dev_present(const char *hid, const char *uid, s64 hrv);
const char *
acpi_dev_get_first_match_name(const char *hid, const char *uid, s64 hrv);
#ifdef CONFIG_ACPI
#include <linux/proc_fs.h>

2
include/acpi/acpiosxf.h
View file

@ -7,7 +7,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

8
include/acpi/acpixf.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -46,7 +46,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20170831
#define ACPI_CA_VERSION 0x20180105
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
@ -260,11 +260,11 @@ ACPI_INIT_GLOBAL(u8, acpi_gbl_osi_data, 0);
ACPI_INIT_GLOBAL(u8, acpi_gbl_reduced_hardware, FALSE);
/*
* Maximum number of While() loop iterations before forced method abort.
* Maximum timeout for While() loop iterations before forced method abort.
* This mechanism is intended to prevent infinite loops during interpreter
* execution within a host kernel.
*/
ACPI_INIT_GLOBAL(u32, acpi_gbl_max_loop_iterations, ACPI_MAX_LOOP_COUNT);
ACPI_INIT_GLOBAL(u32, acpi_gbl_max_loop_iterations, ACPI_MAX_LOOP_TIMEOUT);
/*
* This mechanism is used to trace a specified AML method. The method is

2
include/acpi/acrestyp.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/actbl.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

161
include/acpi/actbl1.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -69,9 +69,10 @@
#define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */
#define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
#define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */
#define ACPI_SIG_PDTT "PDTT" /* Processor Debug Trigger Table */
#define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */
#define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */
#define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */
#define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */
#define ACPI_SIG_SLIT "SLIT" /* System Locality Distance Information Table */
#define ACPI_SIG_SRAT "SRAT" /* System Resource Affinity Table */
#define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */
@ -1149,7 +1150,8 @@ enum acpi_nfit_type {
ACPI_NFIT_TYPE_CONTROL_REGION = 4,
ACPI_NFIT_TYPE_DATA_REGION = 5,
ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6,
ACPI_NFIT_TYPE_RESERVED = 7 /* 7 and greater are reserved */
ACPI_NFIT_TYPE_CAPABILITIES = 7,
ACPI_NFIT_TYPE_RESERVED = 8 /* 8 and greater are reserved */
};
/*
@ -1162,7 +1164,7 @@ struct acpi_nfit_system_address {
struct acpi_nfit_header header;
u16 range_index;
u16 flags;
u32 reserved; /* Reseved, must be zero */
u32 reserved; /* Reserved, must be zero */
u32 proximity_domain;
u8 range_guid[16];
u64 address;
@ -1281,9 +1283,72 @@ struct acpi_nfit_flush_address {
u64 hint_address[1]; /* Variable length */
};
/* 7: Platform Capabilities Structure */
struct acpi_nfit_capabilities {
struct acpi_nfit_header header;
u8 highest_capability;
u8 reserved[3]; /* Reserved, must be zero */
u32 capabilities;
u32 reserved2;
};
/* Capabilities Flags */
#define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */
#define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */
#define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */
/*
* NFIT/DVDIMM device handle support - used as the _ADR for each NVDIMM
*/
struct nfit_device_handle {
u32 handle;
};
/* Device handle construction and extraction macros */
#define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F
#define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0
#define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00
#define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000
#define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000
#define ACPI_NFIT_DIMM_NUMBER_OFFSET 0
#define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4
#define ACPI_NFIT_MEMORY_ID_OFFSET 8
#define ACPI_NFIT_SOCKET_ID_OFFSET 12
#define ACPI_NFIT_NODE_ID_OFFSET 16
/* Macro to construct a NFIT/NVDIMM device handle */
#define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \
((dimm) | \
((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \
((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \
((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \
((node) << ACPI_NFIT_NODE_ID_OFFSET))
/* Macros to extract individual fields from a NFIT/NVDIMM device handle */
#define ACPI_NFIT_GET_DIMM_NUMBER(handle) \
((handle) & ACPI_NFIT_DIMM_NUMBER_MASK)
#define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \
(((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET)
#define ACPI_NFIT_GET_MEMORY_ID(handle) \
(((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET)
#define ACPI_NFIT_GET_SOCKET_ID(handle) \
(((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET)
#define ACPI_NFIT_GET_NODE_ID(handle) \
(((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET)
/*******************************************************************************
*
* PDTT - Processor Debug Trigger Table (ACPI 6.2)
* PDTT - Platform Debug Trigger Table (ACPI 6.2)
* Version 0
*
******************************************************************************/
@ -1301,14 +1366,14 @@ struct acpi_table_pdtt {
* starting at array_offset.
*/
struct acpi_pdtt_channel {
u16 sub_channel_id;
u8 subchannel_id;
u8 flags;
};
/* Mask and Flags for above */
/* Flags for above */
#define ACPI_PDTT_SUBCHANNEL_ID_MASK 0x00FF
#define ACPI_PDTT_RUNTIME_TRIGGER (1<<8)
#define ACPI_PPTT_WAIT_COMPLETION (1<<9)
#define ACPI_PDTT_RUNTIME_TRIGGER (1)
#define ACPI_PDTT_WAIT_COMPLETION (1<<1)
/*******************************************************************************
*
@ -1376,6 +1441,20 @@ struct acpi_pptt_cache {
#define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */
#define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */
/* Attributes describing cache */
#define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */
#define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */
#define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */
#define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */
#define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */
#define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */
#define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */
#define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */
#define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */
#define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */
/* 2: ID Structure */
struct acpi_pptt_id {
@ -1403,6 +1482,68 @@ struct acpi_table_sbst {
u32 critical_level;
};
/*******************************************************************************
*
* SDEV - Secure Devices Table (ACPI 6.2)
* Version 1
*
******************************************************************************/
struct acpi_table_sdev {
struct acpi_table_header header; /* Common ACPI table header */
};
struct acpi_sdev_header {
u8 type;
u8 flags;
u16 length;
};
/* Values for subtable type above */
enum acpi_sdev_type {
ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0,
ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1,
ACPI_SDEV_TYPE_RESERVED = 2 /* 2 and greater are reserved */
};
/* Values for flags above */
#define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1)
/*
* SDEV subtables
*/
/* 0: Namespace Device Based Secure Device Structure */
struct acpi_sdev_namespace {
struct acpi_sdev_header header;
u16 device_id_offset;
u16 device_id_length;
u16 vendor_data_offset;
u16 vendor_data_length;
};
/* 1: PCIe Endpoint Device Based Device Structure */
struct acpi_sdev_pcie {
struct acpi_sdev_header header;
u16 segment;
u16 start_bus;
u16 path_offset;
u16 path_length;
u16 vendor_data_offset;
u16 vendor_data_length;
};
/* 1a: PCIe Endpoint path entry */
struct acpi_sdev_pcie_path {
u8 device;
u8 function;
};
/*******************************************************************************
*
* SLIT - System Locality Distance Information Table

17
include/acpi/actbl2.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -810,6 +810,7 @@ struct acpi_iort_smmu_v3 {
u8 pxm;
u8 reserved1;
u16 reserved2;
u32 id_mapping_index;
};
/* Values for Model field above */
@ -1246,6 +1247,8 @@ enum acpi_spmi_interface_types {
* TCPA - Trusted Computing Platform Alliance table
* Version 2
*
* TCG Hardware Interface Table for TPM 1.2 Clients and Servers
*
* Conforms to "TCG ACPI Specification, Family 1.2 and 2.0",
* Version 1.2, Revision 8
* February 27, 2017
@ -1310,6 +1313,8 @@ struct acpi_table_tcpa_server {
* TPM2 - Trusted Platform Module (TPM) 2.0 Hardware Interface Table
* Version 4
*
* TCG Hardware Interface Table for TPM 2.0 Clients and Servers
*
* Conforms to "TCG ACPI Specification, Family 1.2 and 2.0",
* Version 1.2, Revision 8
* February 27, 2017
@ -1329,15 +1334,23 @@ struct acpi_table_tpm2 {
/* Values for start_method above */
#define ACPI_TPM2_NOT_ALLOWED 0
#define ACPI_TPM2_RESERVED1 1
#define ACPI_TPM2_START_METHOD 2
#define ACPI_TPM2_RESERVED3 3
#define ACPI_TPM2_RESERVED4 4
#define ACPI_TPM2_RESERVED5 5
#define ACPI_TPM2_MEMORY_MAPPED 6
#define ACPI_TPM2_COMMAND_BUFFER 7
#define ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD 8
#define ACPI_TPM2_RESERVED9 9
#define ACPI_TPM2_RESERVED10 10
#define ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC 11 /* V1.2 Rev 8 */
#define ACPI_TPM2_RESERVED 12
/* Trailer appears after any start_method subtables */
/* Optional trailer appears after any start_method subtables */
struct acpi_tpm2_trailer {
u8 method_parameters[12];
u32 minimum_log_length; /* Minimum length for the event log area */
u64 log_address; /* Address of the event log area */
};

2
include/acpi/actbl3.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

16
include/acpi/actypes.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -468,6 +468,8 @@ typedef void *acpi_handle; /* Actually a ptr to a NS Node */
#define ACPI_NSEC_PER_MSEC 1000000L
#define ACPI_NSEC_PER_SEC 1000000000L
#define ACPI_TIME_AFTER(a, b) ((s64)((b) - (a)) < 0)
/* Owner IDs are used to track namespace nodes for selective deletion */
typedef u8 acpi_owner_id;
@ -483,7 +485,7 @@ typedef u8 acpi_owner_id;
/*
* Constants with special meanings
*/
#define ACPI_ROOT_OBJECT ACPI_ADD_PTR (acpi_handle, NULL, ACPI_MAX_PTR)
#define ACPI_ROOT_OBJECT ((acpi_handle) ACPI_TO_POINTER (ACPI_MAX_PTR))
#define ACPI_WAIT_FOREVER 0xFFFF /* u16, as per ACPI spec */
#define ACPI_DO_NOT_WAIT 0
@ -530,13 +532,13 @@ typedef u64 acpi_integer;
#define ACPI_CAST_INDIRECT_PTR(t, p) ((t **) (acpi_uintptr_t) (p))
#define ACPI_ADD_PTR(t, a, b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8, (a)) + (acpi_size)(b)))
#define ACPI_SUB_PTR(t, a, b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8, (a)) - (acpi_size)(b)))
#define ACPI_PTR_DIFF(a, b) (acpi_size) (ACPI_CAST_PTR (u8, (a)) - ACPI_CAST_PTR (u8, (b)))
#define ACPI_PTR_DIFF(a, b) ((acpi_size) (ACPI_CAST_PTR (u8, (a)) - ACPI_CAST_PTR (u8, (b))))
/* Pointer/Integer type conversions */
#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL,(acpi_size) i)
#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p, (void *) NULL)
#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF (&(((d *) 0)->f), (void *) NULL)
#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) 0, (acpi_size) (i))
#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p, (void *) 0)
#define ACPI_OFFSET(d, f) ACPI_PTR_DIFF (&(((d *) 0)->f), (void *) 0)
#define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i)
#define ACPI_PTR_TO_PHYSADDR(i) ACPI_TO_INTEGER(i)
@ -1299,6 +1301,8 @@ typedef enum {
#define ACPI_OSI_WIN_7 0x0B
#define ACPI_OSI_WIN_8 0x0C
#define ACPI_OSI_WIN_10 0x0D
#define ACPI_OSI_WIN_10_RS1 0x0E
#define ACPI_OSI_WIN_10_RS2 0x0F
/* Definitions of getopt */

2
include/acpi/acuuid.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/platform/acenv.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/platform/acenvex.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/platform/acgcc.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/platform/acgccex.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/acpi/platform/acintel.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
include/acpi/platform/aclinux.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -206,7 +206,7 @@
#define ACPI_FLUSH_CPU_CACHE()
#define ACPI_CAST_PTHREAD_T(pthread) ((acpi_thread_id) (pthread))
#if defined(__ia64__) || defined(__x86_64__) ||\
#if defined(__ia64__) || (defined(__x86_64__) && !defined(__ILP32__)) ||\
defined(__aarch64__) || defined(__PPC64__) ||\
defined(__s390x__)
#define ACPI_MACHINE_WIDTH 64

2
include/acpi/platform/aclinuxex.h
View file

@ -5,7 +5,7 @@
*****************************************************************************/
/*
* Copyright (C) 2000 - 2017, Intel Corp.
* Copyright (C) 2000 - 2018, Intel Corp.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
include/asm-generic/audit_dir_write.h
View file

@ -27,7 +27,9 @@ __NR_mknod,
__NR_mkdirat,
__NR_mknodat,
__NR_unlinkat,
#ifdef __NR_renameat
__NR_renameat,
#endif
__NR_linkat,
__NR_symlinkat,
#endif

20
include/asm-generic/bitops/find.h
View file

@ -16,6 +16,22 @@ extern unsigned long find_next_bit(const unsigned long *addr, unsigned long
size, unsigned long offset);
#endif
#ifndef find_next_and_bit
/**
* find_next_and_bit - find the next set bit in both memory regions
* @addr1: The first address to base the search on
* @addr2: The second address to base the search on
* @offset: The bitnumber to start searching at
* @size: The bitmap size in bits
*
* Returns the bit number for the next set bit
* If no bits are set, returns @size.
*/
extern unsigned long find_next_and_bit(const unsigned long *addr1,
const unsigned long *addr2, unsigned long size,
unsigned long offset);
#endif
#ifndef find_next_zero_bit
/**
* find_next_zero_bit - find the next cleared bit in a memory region
@ -55,8 +71,12 @@ extern unsigned long find_first_zero_bit(const unsigned long *addr,
unsigned long size);
#else /* CONFIG_GENERIC_FIND_FIRST_BIT */
#ifndef find_first_bit
#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
#endif
#ifndef find_first_zero_bit
#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
#endif
#endif /* CONFIG_GENERIC_FIND_FIRST_BIT */

30
include/asm-generic/clkdev.h
View file

@ -1,30 +0,0 @@
/*
* include/asm-generic/clkdev.h
*
* Based on the ARM clkdev.h:
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __ASM_CLKDEV_H
#define __ASM_CLKDEV_H
#include <linux/slab.h>
#ifndef CONFIG_COMMON_CLK
struct clk;
static inline int __clk_get(struct clk *clk) { return 1; }
static inline void __clk_put(struct clk *clk) { }
#endif
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
return kzalloc(size, GFP_KERNEL);
}
#endif

10
include/asm-generic/dma-mapping.h Normal file
View file

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_GENERIC_DMA_MAPPING_H
#define _ASM_GENERIC_DMA_MAPPING_H
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
{
return &dma_direct_ops;
}
#endif /* _ASM_GENERIC_DMA_MAPPING_H */

35
include/asm-generic/error-injection.h Normal file
View file

@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_GENERIC_ERROR_INJECTION_H
#define _ASM_GENERIC_ERROR_INJECTION_H
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
enum {
EI_ETYPE_NONE, /* Dummy value for undefined case */
EI_ETYPE_NULL, /* Return NULL if failure */
EI_ETYPE_ERRNO, /* Return -ERRNO if failure */
EI_ETYPE_ERRNO_NULL, /* Return -ERRNO or NULL if failure */
};
struct error_injection_entry {
unsigned long addr;
int etype;
};
#ifdef CONFIG_FUNCTION_ERROR_INJECTION
/*
* Whitelist ganerating macro. Specify functions which can be
* error-injectable using this macro.
*/
#define ALLOW_ERROR_INJECTION(fname, _etype) \
static struct error_injection_entry __used \
__attribute__((__section__("_error_injection_whitelist"))) \
_eil_addr_##fname = { \
.addr = (unsigned long)fname, \
.etype = EI_ETYPE_##_etype, \
};
#else
#define ALLOW_ERROR_INJECTION(fname, _etype)
#endif
#endif
#endif /* _ASM_GENERIC_ERROR_INJECTION_H */

6
include/asm-generic/pci_iomap.h
View file

@ -1,12 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Generic I/O port emulation, based on MN10300 code
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef __ASM_GENERIC_PCI_IOMAP_H
#define __ASM_GENERIC_PCI_IOMAP_H

25
include/asm-generic/pgtable.h
View file

@ -309,17 +309,24 @@ extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
#endif
#ifndef __HAVE_ARCH_PMDP_INVALIDATE
extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
pmd_t *pmdp);
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
/*
* This is an implementation of pmdp_establish() that is only suitable for an
* architecture that doesn't have hardware dirty/accessed bits. In this case we
* can't race with CPU which sets these bits and non-atomic aproach is fine.
*/
static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
unsigned long address, pmd_t *pmdp, pmd_t pmd)
{
pmd_t old_pmd = *pmdp;
set_pmd_at(vma->vm_mm, address, pmdp, pmd);
return old_pmd;
}
#endif
#ifndef __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
unsigned long address, pmd_t *pmdp)
{
}
#ifndef __HAVE_ARCH_PMDP_INVALIDATE
extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
pmd_t *pmdp);
#endif
#ifndef __HAVE_ARCH_PTE_SAME

1
include/asm-generic/qrwlock_types.h
View file

@ -3,6 +3,7 @@
#define __ASM_GENERIC_QRWLOCK_TYPES_H
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/spinlock_types.h>
/*

8
include/asm-generic/sections.h
View file

@ -30,6 +30,7 @@
* __ctors_start, __ctors_end
* __irqentry_text_start, __irqentry_text_end
* __softirqentry_text_start, __softirqentry_text_end
* __start_opd, __end_opd
*/
extern char _text[], _stext[], _etext[];
extern char _data[], _sdata[], _edata[];
@ -49,12 +50,15 @@ extern char __start_once[], __end_once[];
/* Start and end of .ctors section - used for constructor calls. */
extern char __ctors_start[], __ctors_end[];
/* Start and end of .opd section - used for function descriptors. */
extern char __start_opd[], __end_opd[];
extern __visible const void __nosave_begin, __nosave_end;
/* function descriptor handling (if any). Override
* in asm/sections.h */
/* Function descriptor handling (if any). Override in asm/sections.h */
#ifndef dereference_function_descriptor
#define dereference_function_descriptor(p) (p)
#define dereference_kernel_function_descriptor(p) (p)
#endif
/* random extra sections (if any). Override

14
include/asm-generic/vmlinux.lds.h
View file

@ -136,6 +136,15 @@
#define KPROBE_BLACKLIST()
#endif
#ifdef CONFIG_FUNCTION_ERROR_INJECTION
#define ERROR_INJECT_WHITELIST() STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__start_error_injection_whitelist) = .;\
KEEP(*(_error_injection_whitelist)) \
VMLINUX_SYMBOL(__stop_error_injection_whitelist) = .;
#else
#define ERROR_INJECT_WHITELIST()
#endif
#ifdef CONFIG_EVENT_TRACING
#define FTRACE_EVENTS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_ftrace_events) = .; \
@ -268,7 +277,11 @@
#define INIT_TASK_DATA(align) \
. = ALIGN(align); \
VMLINUX_SYMBOL(__start_init_task) = .; \
VMLINUX_SYMBOL(init_thread_union) = .; \
VMLINUX_SYMBOL(init_stack) = .; \
*(.data..init_task) \
*(.data..init_thread_info) \
. = VMLINUX_SYMBOL(__start_init_task) + THREAD_SIZE; \
VMLINUX_SYMBOL(__end_init_task) = .;
/*
@ -564,6 +577,7 @@
FTRACE_EVENTS() \
TRACE_SYSCALLS() \
KPROBE_BLACKLIST() \
ERROR_INJECT_WHITELIST() \
MEM_DISCARD(init.rodata) \
CLK_OF_TABLES() \
RESERVEDMEM_OF_TABLES() \

10
include/crypto/aead.h
View file

@ -327,7 +327,12 @@ static inline struct crypto_aead *crypto_aead_reqtfm(struct aead_request *req)
*/
static inline int crypto_aead_encrypt(struct aead_request *req)
{
return crypto_aead_alg(crypto_aead_reqtfm(req))->encrypt(req);
struct crypto_aead *aead = crypto_aead_reqtfm(req);
if (crypto_aead_get_flags(aead) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return crypto_aead_alg(aead)->encrypt(req);
}
/**
@ -356,6 +361,9 @@ static inline int crypto_aead_decrypt(struct aead_request *req)
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
if (crypto_aead_get_flags(aead) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
if (req->cryptlen < crypto_aead_authsize(aead))
return -EINVAL;

3
include/crypto/chacha20.h
View file

@ -13,12 +13,13 @@
#define CHACHA20_IV_SIZE 16
#define CHACHA20_KEY_SIZE 32
#define CHACHA20_BLOCK_SIZE 64
#define CHACHA20_BLOCK_WORDS (CHACHA20_BLOCK_SIZE / sizeof(u32))
struct chacha20_ctx {
u32 key[8];
};
void chacha20_block(u32 *state, void *stream);
void chacha20_block(u32 *state, u32 *stream);
void crypto_chacha20_init(u32 *state, struct chacha20_ctx *ctx, u8 *iv);
int crypto_chacha20_setkey(struct crypto_skcipher *tfm, const u8 *key,
unsigned int keysize);

46
include/crypto/hash.h
View file

@ -71,12 +71,11 @@ struct ahash_request {
/**
* struct ahash_alg - asynchronous message digest definition
* @init: Initialize the transformation context. Intended only to initialize the
* @init: **[mandatory]** Initialize the transformation context. Intended only to initialize the
* state of the HASH transformation at the beginning. This shall fill in
* the internal structures used during the entire duration of the whole
* transformation. No data processing happens at this point.
* Note: mandatory.
* @update: Push a chunk of data into the driver for transformation. This
* @update: **[mandatory]** Push a chunk of data into the driver for transformation. This
* function actually pushes blocks of data from upper layers into the
* driver, which then passes those to the hardware as seen fit. This
* function must not finalize the HASH transformation by calculating the
@ -85,20 +84,17 @@ struct ahash_request {
* context, as this function may be called in parallel with the same
* transformation object. Data processing can happen synchronously
* [SHASH] or asynchronously [AHASH] at this point.
* Note: mandatory.
* @final: Retrieve result from the driver. This function finalizes the
* @final: **[mandatory]** Retrieve result from the driver. This function finalizes the
* transformation and retrieves the resulting hash from the driver and
* pushes it back to upper layers. No data processing happens at this
* point unless hardware requires it to finish the transformation
* (then the data buffered by the device driver is processed).
* Note: mandatory.
* @finup: Combination of @update and @final. This function is effectively a
* @finup: **[optional]** Combination of @update and @final. This function is effectively a
* combination of @update and @final calls issued in sequence. As some
* hardware cannot do @update and @final separately, this callback was
* added to allow such hardware to be used at least by IPsec. Data
* processing can happen synchronously [SHASH] or asynchronously [AHASH]
* at this point.
* Note: optional.
* @digest: Combination of @init and @update and @final. This function
* effectively behaves as the entire chain of operations, @init,
* @update and @final issued in sequence. Just like @finup, this was
@ -210,7 +206,6 @@ struct crypto_ahash {
unsigned int keylen);
unsigned int reqsize;
bool has_setkey;
struct crypto_tfm base;
};
@ -410,11 +405,6 @@ static inline void *ahash_request_ctx(struct ahash_request *req)
int crypto_ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
unsigned int keylen);
static inline bool crypto_ahash_has_setkey(struct crypto_ahash *tfm)
{
return tfm->has_setkey;
}
/**
* crypto_ahash_finup() - update and finalize message digest
* @req: reference to the ahash_request handle that holds all information
@ -487,7 +477,12 @@ static inline int crypto_ahash_export(struct ahash_request *req, void *out)
*/
static inline int crypto_ahash_import(struct ahash_request *req, const void *in)
{
return crypto_ahash_reqtfm(req)->import(req, in);
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
if (crypto_ahash_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->import(req, in);
}
/**
@ -503,7 +498,12 @@ static inline int crypto_ahash_import(struct ahash_request *req, const void *in)
*/
static inline int crypto_ahash_init(struct ahash_request *req)
{
return crypto_ahash_reqtfm(req)->init(req);
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
if (crypto_ahash_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->init(req);
}
/**
@ -855,7 +855,12 @@ static inline int crypto_shash_export(struct shash_desc *desc, void *out)
*/
static inline int crypto_shash_import(struct shash_desc *desc, const void *in)
{
return crypto_shash_alg(desc->tfm)->import(desc, in);
struct crypto_shash *tfm = desc->tfm;
if (crypto_shash_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return crypto_shash_alg(tfm)->import(desc, in);
}
/**
@ -871,7 +876,12 @@ static inline int crypto_shash_import(struct shash_desc *desc, const void *in)
*/
static inline int crypto_shash_init(struct shash_desc *desc)
{
return crypto_shash_alg(desc->tfm)->init(desc);
struct crypto_shash *tfm = desc->tfm;
if (crypto_shash_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return crypto_shash_alg(tfm)->init(desc);
}
/**

2
include/crypto/if_alg.h
View file

@ -245,7 +245,7 @@ ssize_t af_alg_sendpage(struct socket *sock, struct page *page,
int offset, size_t size, int flags);
void af_alg_free_resources(struct af_alg_async_req *areq);
void af_alg_async_cb(struct crypto_async_request *_req, int err);
unsigned int af_alg_poll(struct file *file, struct socket *sock,
__poll_t af_alg_poll(struct file *file, struct socket *sock,
poll_table *wait);
struct af_alg_async_req *af_alg_alloc_areq(struct sock *sk,
unsigned int areqlen);

2
include/crypto/internal/hash.h
View file

@ -90,6 +90,8 @@ static inline bool crypto_shash_alg_has_setkey(struct shash_alg *alg)
return alg->setkey != shash_no_setkey;
}
bool crypto_hash_alg_has_setkey(struct hash_alg_common *halg);
int crypto_init_ahash_spawn(struct crypto_ahash_spawn *spawn,
struct hash_alg_common *alg,
struct crypto_instance *inst);

11
include/crypto/internal/scompress.h
View file

@ -28,17 +28,6 @@ struct crypto_scomp {
* @free_ctx: Function frees context allocated with alloc_ctx
* @compress: Function performs a compress operation
* @decompress: Function performs a de-compress operation
* @init: Initialize the cryptographic transformation object.
* This function is used to initialize the cryptographic
* transformation object. This function is called only once at
* the instantiation time, right after the transformation context
* was allocated. In case the cryptographic hardware has some
* special requirements which need to be handled by software, this
* function shall check for the precise requirement of the
* transformation and put any software fallbacks in place.
* @exit: Deinitialize the cryptographic transformation object. This is a
* counterpart to @init, used to remove various changes set in
* @init.
* @base: Common crypto API algorithm data structure
*/
struct scomp_alg {

10
include/crypto/null.h
View file

@ -12,14 +12,4 @@
struct crypto_skcipher *crypto_get_default_null_skcipher(void);
void crypto_put_default_null_skcipher(void);
static inline struct crypto_skcipher *crypto_get_default_null_skcipher2(void)
{
return crypto_get_default_null_skcipher();
}
static inline void crypto_put_default_null_skcipher2(void)
{
crypto_put_default_null_skcipher();
}
#endif

2
include/crypto/poly1305.h
View file

@ -31,8 +31,6 @@ struct poly1305_desc_ctx {
};
int crypto_poly1305_init(struct shash_desc *desc);
int crypto_poly1305_setkey(struct crypto_shash *tfm,
const u8 *key, unsigned int keylen);
unsigned int crypto_poly1305_setdesckey(struct poly1305_desc_ctx *dctx,
const u8 *src, unsigned int srclen);
int crypto_poly1305_update(struct shash_desc *desc,

27
include/crypto/salsa20.h Normal file
View file

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Common values for the Salsa20 algorithm
*/
#ifndef _CRYPTO_SALSA20_H
#define _CRYPTO_SALSA20_H
#include <linux/types.h>
#define SALSA20_IV_SIZE 8
#define SALSA20_MIN_KEY_SIZE 16
#define SALSA20_MAX_KEY_SIZE 32
#define SALSA20_BLOCK_SIZE 64
struct crypto_skcipher;
struct salsa20_ctx {
u32 initial_state[16];
};
void crypto_salsa20_init(u32 *state, const struct salsa20_ctx *ctx,
const u8 *iv);
int crypto_salsa20_setkey(struct crypto_skcipher *tfm, const u8 *key,
unsigned int keysize);
#endif /* _CRYPTO_SALSA20_H */

6
include/crypto/sha3.h
View file

@ -19,7 +19,6 @@
struct sha3_state {
u64 st[25];
unsigned int md_len;
unsigned int rsiz;
unsigned int rsizw;
@ -27,4 +26,9 @@ struct sha3_state {
u8 buf[SHA3_224_BLOCK_SIZE];
};
int crypto_sha3_init(struct shash_desc *desc);
int crypto_sha3_update(struct shash_desc *desc, const u8 *data,
unsigned int len);
int crypto_sha3_final(struct shash_desc *desc, u8 *out);
#endif

11
include/crypto/skcipher.h
View file

@ -401,11 +401,6 @@ static inline int crypto_skcipher_setkey(struct crypto_skcipher *tfm,
return tfm->setkey(tfm, key, keylen);
}
static inline bool crypto_skcipher_has_setkey(struct crypto_skcipher *tfm)
{
return tfm->keysize;
}
static inline unsigned int crypto_skcipher_default_keysize(
struct crypto_skcipher *tfm)
{
@ -442,6 +437,9 @@ static inline int crypto_skcipher_encrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
if (crypto_skcipher_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->encrypt(req);
}
@ -460,6 +458,9 @@ static inline int crypto_skcipher_decrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
if (crypto_skcipher_get_flags(tfm) & CRYPTO_TFM_NEED_KEY)
return -ENOKEY;
return tfm->decrypt(req);
}

16
include/drm/drm_connector.h
View file

@ -419,6 +419,12 @@ struct drm_connector_state {
* upscaling, mostly used for built-in panels.
*/
unsigned int scaling_mode;
/**
* @content_protection: Connector property to request content
* protection. This is most commonly used for HDCP.
*/
unsigned int content_protection;
};
/**
@ -766,6 +772,7 @@ struct drm_cmdline_mode {
* @tile_h_size: horizontal size of this tile.
* @tile_v_size: vertical size of this tile.
* @scaling_mode_property: Optional atomic property to control the upscaling.
* @content_protection_property: Optional property to control content protection
*
* Each connector may be connected to one or more CRTCs, or may be clonable by
* another connector if they can share a CRTC. Each connector also has a specific
@ -856,6 +863,12 @@ struct drm_connector {
struct drm_property *scaling_mode_property;
/**
* @content_protection_property: DRM ENUM property for content
* protection
*/
struct drm_property *content_protection_property;
/**
* @path_blob_ptr:
*
@ -1065,6 +1078,7 @@ const char *drm_get_dvi_i_subconnector_name(int val);
const char *drm_get_dvi_i_select_name(int val);
const char *drm_get_tv_subconnector_name(int val);
const char *drm_get_tv_select_name(int val);
const char *drm_get_content_protection_name(int val);
int drm_mode_create_dvi_i_properties(struct drm_device *dev);
int drm_mode_create_tv_properties(struct drm_device *dev,
@ -1073,6 +1087,8 @@ int drm_mode_create_tv_properties(struct drm_device *dev,
int drm_mode_create_scaling_mode_property(struct drm_device *dev);
int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
u32 scaling_mode_mask);
int drm_connector_attach_content_protection_property(
struct drm_connector *connector);
int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
int drm_mode_create_suggested_offset_properties(struct drm_device *dev);

17
include/drm/drm_dp_helper.h
View file

@ -870,6 +870,23 @@
#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
#define DP_AUX_HDCP_BKSV 0x68000
#define DP_AUX_HDCP_RI_PRIME 0x68005
#define DP_AUX_HDCP_AKSV 0x68007
#define DP_AUX_HDCP_AN 0x6800C
#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
#define DP_AUX_HDCP_BCAPS 0x68028
# define DP_BCAPS_REPEATER_PRESENT BIT(1)
# define DP_BCAPS_HDCP_CAPABLE BIT(0)
#define DP_AUX_HDCP_BSTATUS 0x68029
# define DP_BSTATUS_REAUTH_REQ BIT(3)
# define DP_BSTATUS_LINK_FAILURE BIT(2)
# define DP_BSTATUS_R0_PRIME_READY BIT(1)
# define DP_BSTATUS_READY BIT(0)
#define DP_AUX_HDCP_BINFO 0x6802A
#define DP_AUX_HDCP_KSV_FIFO 0x6802C
#define DP_AUX_HDCP_AINFO 0x6803B
/* DP 1.2 Sideband message defines */
/* peer device type - DP 1.2a Table 2-92 */
#define DP_PEER_DEVICE_NONE 0x0

2
include/drm/drm_file.h
View file

@ -364,7 +364,7 @@ int drm_open(struct inode *inode, struct file *filp);
ssize_t drm_read(struct file *filp, char __user *buffer,
size_t count, loff_t *offset);
int drm_release(struct inode *inode, struct file *filp);
unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
__poll_t drm_poll(struct file *filp, struct poll_table_struct *wait);
int drm_event_reserve_init_locked(struct drm_device *dev,
struct drm_file *file_priv,
struct drm_pending_event *p,

41
include/drm/drm_hdcp.h Normal file
View file

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 Google, Inc.
*
* Authors:
* Sean Paul <seanpaul@chromium.org>
*/
#ifndef _DRM_HDCP_H_INCLUDED_
#define _DRM_HDCP_H_INCLUDED_
/* Period of hdcp checks (to ensure we're still authenticated) */
#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
/* Shared lengths/masks between HDMI/DVI/DisplayPort */
#define DRM_HDCP_AN_LEN 8
#define DRM_HDCP_BSTATUS_LEN 2
#define DRM_HDCP_KSV_LEN 5
#define DRM_HDCP_RI_LEN 2
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
/* Slave address for the HDCP registers in the receiver */
#define DRM_HDCP_DDC_ADDR 0x3A
/* HDCP register offsets for HDMI/DVI devices */
#define DRM_HDCP_DDC_BKSV 0x00
#define DRM_HDCP_DDC_RI_PRIME 0x08
#define DRM_HDCP_DDC_AKSV 0x10
#define DRM_HDCP_DDC_AN 0x18
#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
#define DRM_HDCP_DDC_BCAPS 0x40
#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
#define DRM_HDCP_DDC_BSTATUS 0x41
#define DRM_HDCP_DDC_KSV_FIFO 0x43
#endif

3
include/drm/i915_component.h
View file

@ -26,9 +26,8 @@
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
* 5 should be enough as only HSW, BDW, SKL need such fix.
*/
#define MAX_PORTS 5
#define MAX_PORTS 6
/**
* struct i915_audio_component_ops - Ops implemented by i915 driver, called by hda driver

18
include/drm/i915_pciids.h
View file

@ -414,24 +414,20 @@
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info)
/* CNL U 2+2 */
#define INTEL_CNL_U_GT2_IDS(info) \
/* CNL */
#define INTEL_CNL_IDS(info) \
INTEL_VGA_DEVICE(0x5A52, info), \
INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
INTEL_VGA_DEVICE(0x5A4A, info)
/* CNL Y 2+2 */
#define INTEL_CNL_Y_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A51, info), \
INTEL_VGA_DEVICE(0x5A59, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A71, info), \
INTEL_VGA_DEVICE(0x5A79, info)
#define INTEL_CNL_IDS(info) \
INTEL_CNL_U_GT2_IDS(info), \
INTEL_CNL_Y_GT2_IDS(info)
INTEL_VGA_DEVICE(0x5A79, info), \
INTEL_VGA_DEVICE(0x5A54, info), \
INTEL_VGA_DEVICE(0x5A5C, info), \
INTEL_VGA_DEVICE(0x5A44, info)
#endif /* _I915_PCIIDS_H */

22
include/dt-bindings/bus/ti-sysc.h Normal file
View file

@ -0,0 +1,22 @@
/* TI sysc interconnect target module defines */
/* Generic sysc found on omap2 and later, also known as type1 */
#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
#define SYSC_OMAP2_EMUFREE (1 << 5)
#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
#define SYSC_OMAP2_SOFTRESET (1 << 1)
#define SYSC_OMAP2_AUTOIDLE (1 << 0)
/* Generic sysc found on omap4 and later, also known as type2 */
#define SYSC_OMAP4_DMADISABLE (1 << 16)
#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
#define SYSC_OMAP4_SOFTRESET (1 << 0)
/* SmartReflex sysc found on 36xx and later */
#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
#define SYSC_IDLE_FORCE 0
#define SYSC_IDLE_NO 1
#define SYSC_IDLE_SMART 2
#define SYSC_IDLE_SMART_WKUP 3

108
include/dt-bindings/clock/am3.h Normal file
View file

@ -0,0 +1,108 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_AM3_H
#define __DT_BINDINGS_CLK_AM3_H
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
/* mpu clocks */
#define AM3_MPU_CLKCTRL_OFFSET 0x4
#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
#endif

113
include/dt-bindings/clock/am4.h Normal file
View file

@ -0,0 +1,113 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_AM4_H
#define __DT_BINDINGS_CLK_AM4_H
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
/* l4_wkup clocks */
#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
/* mpu clocks */
#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* gfx_l3 clocks */
#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_rtc clocks */
#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
/* l4_per clocks */
#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
#endif

52
include/dt-bindings/clock/aspeed-clock.h Normal file
View file

@ -0,0 +1,52 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
#ifndef DT_BINDINGS_ASPEED_CLOCK_H
#define DT_BINDINGS_ASPEED_CLOCK_H
#define ASPEED_CLK_GATE_ECLK 0
#define ASPEED_CLK_GATE_GCLK 1
#define ASPEED_CLK_GATE_MCLK 2
#define ASPEED_CLK_GATE_VCLK 3
#define ASPEED_CLK_GATE_BCLK 4
#define ASPEED_CLK_GATE_DCLK 5
#define ASPEED_CLK_GATE_REFCLK 6
#define ASPEED_CLK_GATE_USBPORT2CLK 7
#define ASPEED_CLK_GATE_LCLK 8
#define ASPEED_CLK_GATE_USBUHCICLK 9
#define ASPEED_CLK_GATE_D1CLK 10
#define ASPEED_CLK_GATE_YCLK 11
#define ASPEED_CLK_GATE_USBPORT1CLK 12
#define ASPEED_CLK_GATE_UART1CLK 13
#define ASPEED_CLK_GATE_UART2CLK 14
#define ASPEED_CLK_GATE_UART5CLK 15
#define ASPEED_CLK_GATE_ESPICLK 16
#define ASPEED_CLK_GATE_MAC1CLK 17
#define ASPEED_CLK_GATE_MAC2CLK 18
#define ASPEED_CLK_GATE_RSACLK 19
#define ASPEED_CLK_GATE_UART3CLK 20
#define ASPEED_CLK_GATE_UART4CLK 21
#define ASPEED_CLK_GATE_SDCLKCLK 22
#define ASPEED_CLK_GATE_LHCCLK 23
#define ASPEED_CLK_HPLL 24
#define ASPEED_CLK_AHB 25
#define ASPEED_CLK_APB 26
#define ASPEED_CLK_UART 27
#define ASPEED_CLK_SDIO 28
#define ASPEED_CLK_ECLK 29
#define ASPEED_CLK_ECLK_MUX 30
#define ASPEED_CLK_LHCLK 31
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
#define ASPEED_RESET_ADC 2
#define ASPEED_RESET_JTAG_MASTER 3
#define ASPEED_RESET_MIC 4
#define ASPEED_RESET_PWM 5
#define ASPEED_RESET_PCIVGA 6
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
#endif

71
include/dt-bindings/clock/axg-clkc.h Normal file
View file

@ -0,0 +1,71 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Meson-AXG clock tree IDs
*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#ifndef __AXG_CLKC_H
#define __AXG_CLKC_H
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_AUDIO_LOCKER 16
#define CLKID_MIPI_DSI_HOST 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
#define CLKID_SPICC0 21
#define CLKID_I2C 22
#define CLKID_RNG0 23
#define CLKID_UART0 24
#define CLKID_MIPI_DSI_PHY 25
#define CLKID_SPICC1 26
#define CLKID_PCIE_A 27
#define CLKID_PCIE_B 28
#define CLKID_HIU_IFACE 29
#define CLKID_ASSIST_MISC 30
#define CLKID_SD_EMMC_B 31
#define CLKID_SD_EMMC_C 32
#define CLKID_DMA 33
#define CLKID_SPI 34
#define CLKID_AUDIO 35
#define CLKID_ETH 36
#define CLKID_UART1 37
#define CLKID_G2D 38
#define CLKID_USB0 39
#define CLKID_USB1 40
#define CLKID_RESET 41
#define CLKID_USB 42
#define CLKID_AHB_ARB0 43
#define CLKID_EFUSE 44
#define CLKID_BOOT_ROM 45
#define CLKID_AHB_DATA_BUS 46
#define CLKID_AHB_CTRL_BUS 47
#define CLKID_USB1_DDR_BRIDGE 48
#define CLKID_USB0_DDR_BRIDGE 49
#define CLKID_MMC_PCLK 50
#define CLKID_VPU_INTR 51
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
#define CLKID_GIC 53
#define CLKID_AO_MEDIA_CPU 54
#define CLKID_AO_AHB_SRAM 55
#define CLKID_AO_AHB_BUS 56
#define CLKID_AO_IFACE 57
#define CLKID_AO_I2C 58
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
#endif /* __AXG_CLKC_H */

45
include/dt-bindings/clock/dm814.h Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_DM814_H
#define __DT_BINDINGS_CLK_DM814_H
#define DM814_CLKCTRL_OFFSET 0x0
#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)
/* default clocks */
#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
/* alwon clocks */
#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
#endif

53
include/dt-bindings/clock/dm816.h Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_DM816_H
#define __DT_BINDINGS_CLK_DM816_H
#define DM816_CLKCTRL_OFFSET 0x0
#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET)
/* default clocks */
#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
/* alwon clocks */
#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c)
#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188)
#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c)
#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194)
#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198)
#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0)
#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0)
#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4)
#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8)
#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc)
#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0)
#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4)
#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8)
#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc)
#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200)
#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204)
#endif

172
include/dt-bindings/clock/dra7.h Normal file
View file

@ -0,0 +1,172 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_DRA7_H
#define __DT_BINDINGS_CLK_DRA7_H
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
/* l3main1 clocks */
#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
/* dma clocks */
#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
/* l4cfg clocks */
#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
/* l3instr clocks */
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#endif

7
include/dt-bindings/clock/hi3660-clock.h
View file

@ -208,4 +208,11 @@
#define HI3660_CLK_I2C6_IOMCU 3
#define HI3660_CLK_IOMCU_PERI0 4
/* clk in stub clock */
#define HI3660_CLK_STUB_CLUSTER0 0
#define HI3660_CLK_STUB_CLUSTER1 1
#define HI3660_CLK_STUB_GPU 2
#define HI3660_CLK_STUB_DDR 3
#define HI3660_CLK_STUB_NUM 4
#endif /* __DTS_HI3660_CLOCK_H */

58
include/dt-bindings/clock/jz4770-cgu.h Normal file
View file

@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
*/
#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
#define JZ4770_CLK_EXT 0
#define JZ4770_CLK_OSC32K 1
#define JZ4770_CLK_PLL0 2
#define JZ4770_CLK_PLL1 3
#define JZ4770_CLK_CCLK 4
#define JZ4770_CLK_H0CLK 5
#define JZ4770_CLK_H1CLK 6
#define JZ4770_CLK_H2CLK 7
#define JZ4770_CLK_C1CLK 8
#define JZ4770_CLK_PCLK 9
#define JZ4770_CLK_MMC0_MUX 10
#define JZ4770_CLK_MMC0 11
#define JZ4770_CLK_MMC1_MUX 12
#define JZ4770_CLK_MMC1 13
#define JZ4770_CLK_MMC2_MUX 14
#define JZ4770_CLK_MMC2 15
#define JZ4770_CLK_CIM 16
#define JZ4770_CLK_UHC 17
#define JZ4770_CLK_GPU 18
#define JZ4770_CLK_BCH 19
#define JZ4770_CLK_LPCLK_MUX 20
#define JZ4770_CLK_GPS 21
#define JZ4770_CLK_SSI_MUX 22
#define JZ4770_CLK_PCM_MUX 23
#define JZ4770_CLK_I2S 24
#define JZ4770_CLK_OTG 25
#define JZ4770_CLK_SSI0 26
#define JZ4770_CLK_SSI1 27
#define JZ4770_CLK_SSI2 28
#define JZ4770_CLK_PCM0 29
#define JZ4770_CLK_PCM1 30
#define JZ4770_CLK_DMA 31
#define JZ4770_CLK_I2C0 32
#define JZ4770_CLK_I2C1 33
#define JZ4770_CLK_I2C2 34
#define JZ4770_CLK_UART0 35
#define JZ4770_CLK_UART1 36
#define JZ4770_CLK_UART2 37
#define JZ4770_CLK_UART3 38
#define JZ4770_CLK_IPU 39
#define JZ4770_CLK_ADC 40
#define JZ4770_CLK_AIC 41
#define JZ4770_CLK_AUX 42
#define JZ4770_CLK_VPU 43
#define JZ4770_CLK_UHC_PHY 44
#define JZ4770_CLK_OTG_PHY 45
#define JZ4770_CLK_EXT512 46
#define JZ4770_CLK_RTC 47
#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */

118
include/dt-bindings/clock/omap5.h Normal file
View file

@ -0,0 +1,118 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_OMAP5_H
#define __DT_BINDINGS_CLK_OMAP5_H
#define OMAP5_CLKCTRL_OFFSET 0x20
#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
/* mpu clocks */
#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* dsp clocks */
#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* abe clocks */
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
/* l3main1 clocks */
#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* l3main2 clocks */
#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* ipu clocks */
#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* dma clocks */
#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* emif clocks */
#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
/* l4cfg clocks */
#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
/* l3instr clocks */
#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
/* l4per clocks */
#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
/* dss clocks */
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
/* l3init clocks */
#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
/* wkupaon clocks */
#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
#endif

222
include/dt-bindings/clock/qcom,gcc-ipq8074.h
View file

@ -58,6 +58,186 @@
#define GCC_QPIC_AHB_CLK 41
#define GCC_QPIC_CLK 42
#define PCNOC_BFDCD_CLK_SRC 43
#define GPLL2_MAIN 44
#define GPLL2 45
#define GPLL4_MAIN 46
#define GPLL4 47
#define GPLL6_MAIN 48
#define GPLL6 49
#define UBI32_PLL_MAIN 50
#define UBI32_PLL 51
#define NSS_CRYPTO_PLL_MAIN 52
#define NSS_CRYPTO_PLL 53
#define PCIE0_AXI_CLK_SRC 54
#define PCIE0_AUX_CLK_SRC 55
#define PCIE0_PIPE_CLK_SRC 56
#define PCIE1_AXI_CLK_SRC 57
#define PCIE1_AUX_CLK_SRC 58
#define PCIE1_PIPE_CLK_SRC 59
#define SDCC1_APPS_CLK_SRC 60
#define SDCC1_ICE_CORE_CLK_SRC 61
#define SDCC2_APPS_CLK_SRC 62
#define USB0_MASTER_CLK_SRC 63
#define USB0_AUX_CLK_SRC 64
#define USB0_MOCK_UTMI_CLK_SRC 65
#define USB0_PIPE_CLK_SRC 66
#define USB1_MASTER_CLK_SRC 67
#define USB1_AUX_CLK_SRC 68
#define USB1_MOCK_UTMI_CLK_SRC 69
#define USB1_PIPE_CLK_SRC 70
#define GCC_XO_CLK_SRC 71
#define SYSTEM_NOC_BFDCD_CLK_SRC 72
#define NSS_CE_CLK_SRC 73
#define NSS_NOC_BFDCD_CLK_SRC 74
#define NSS_CRYPTO_CLK_SRC 75
#define NSS_UBI0_CLK_SRC 76
#define NSS_UBI0_DIV_CLK_SRC 77
#define NSS_UBI1_CLK_SRC 78
#define NSS_UBI1_DIV_CLK_SRC 79
#define UBI_MPT_CLK_SRC 80
#define NSS_IMEM_CLK_SRC 81
#define NSS_PPE_CLK_SRC 82
#define NSS_PORT1_RX_CLK_SRC 83
#define NSS_PORT1_RX_DIV_CLK_SRC 84
#define NSS_PORT1_TX_CLK_SRC 85
#define NSS_PORT1_TX_DIV_CLK_SRC 86
#define NSS_PORT2_RX_CLK_SRC 87
#define NSS_PORT2_RX_DIV_CLK_SRC 88
#define NSS_PORT2_TX_CLK_SRC 89
#define NSS_PORT2_TX_DIV_CLK_SRC 90
#define NSS_PORT3_RX_CLK_SRC 91
#define NSS_PORT3_RX_DIV_CLK_SRC 92
#define NSS_PORT3_TX_CLK_SRC 93
#define NSS_PORT3_TX_DIV_CLK_SRC 94
#define NSS_PORT4_RX_CLK_SRC 95
#define NSS_PORT4_RX_DIV_CLK_SRC 96
#define NSS_PORT4_TX_CLK_SRC 97
#define NSS_PORT4_TX_DIV_CLK_SRC 98
#define NSS_PORT5_RX_CLK_SRC 99
#define NSS_PORT5_RX_DIV_CLK_SRC 100
#define NSS_PORT5_TX_CLK_SRC 101
#define NSS_PORT5_TX_DIV_CLK_SRC 102
#define NSS_PORT6_RX_CLK_SRC 103
#define NSS_PORT6_RX_DIV_CLK_SRC 104
#define NSS_PORT6_TX_CLK_SRC 105
#define NSS_PORT6_TX_DIV_CLK_SRC 106
#define CRYPTO_CLK_SRC 107
#define GP1_CLK_SRC 108
#define GP2_CLK_SRC 109
#define GP3_CLK_SRC 110
#define GCC_PCIE0_AHB_CLK 111
#define GCC_PCIE0_AUX_CLK 112
#define GCC_PCIE0_AXI_M_CLK 113
#define GCC_PCIE0_AXI_S_CLK 114
#define GCC_PCIE0_PIPE_CLK 115
#define GCC_SYS_NOC_PCIE0_AXI_CLK 116
#define GCC_PCIE1_AHB_CLK 117
#define GCC_PCIE1_AUX_CLK 118
#define GCC_PCIE1_AXI_M_CLK 119
#define GCC_PCIE1_AXI_S_CLK 120
#define GCC_PCIE1_PIPE_CLK 121
#define GCC_SYS_NOC_PCIE1_AXI_CLK 122
#define GCC_USB0_AUX_CLK 123
#define GCC_SYS_NOC_USB0_AXI_CLK 124
#define GCC_USB0_MASTER_CLK 125
#define GCC_USB0_MOCK_UTMI_CLK 126
#define GCC_USB0_PHY_CFG_AHB_CLK 127
#define GCC_USB0_PIPE_CLK 128
#define GCC_USB0_SLEEP_CLK 129
#define GCC_USB1_AUX_CLK 130
#define GCC_SYS_NOC_USB1_AXI_CLK 131
#define GCC_USB1_MASTER_CLK 132
#define GCC_USB1_MOCK_UTMI_CLK 133
#define GCC_USB1_PHY_CFG_AHB_CLK 134
#define GCC_USB1_PIPE_CLK 135
#define GCC_USB1_SLEEP_CLK 136
#define GCC_SDCC1_AHB_CLK 137
#define GCC_SDCC1_APPS_CLK 138
#define GCC_SDCC1_ICE_CORE_CLK 139
#define GCC_SDCC2_AHB_CLK 140
#define GCC_SDCC2_APPS_CLK 141
#define GCC_MEM_NOC_NSS_AXI_CLK 142
#define GCC_NSS_CE_APB_CLK 143
#define GCC_NSS_CE_AXI_CLK 144
#define GCC_NSS_CFG_CLK 145
#define GCC_NSS_CRYPTO_CLK 146
#define GCC_NSS_CSR_CLK 147
#define GCC_NSS_EDMA_CFG_CLK 148
#define GCC_NSS_EDMA_CLK 149
#define GCC_NSS_IMEM_CLK 150
#define GCC_NSS_NOC_CLK 151
#define GCC_NSS_PPE_BTQ_CLK 152
#define GCC_NSS_PPE_CFG_CLK 153
#define GCC_NSS_PPE_CLK 154
#define GCC_NSS_PPE_IPE_CLK 155
#define GCC_NSS_PTP_REF_CLK 156
#define GCC_NSSNOC_CE_APB_CLK 157
#define GCC_NSSNOC_CE_AXI_CLK 158
#define GCC_NSSNOC_CRYPTO_CLK 159
#define GCC_NSSNOC_PPE_CFG_CLK 160
#define GCC_NSSNOC_PPE_CLK 161
#define GCC_NSSNOC_QOSGEN_REF_CLK 162
#define GCC_NSSNOC_SNOC_CLK 163
#define GCC_NSSNOC_TIMEOUT_REF_CLK 164
#define GCC_NSSNOC_UBI0_AHB_CLK 165
#define GCC_NSSNOC_UBI1_AHB_CLK 166
#define GCC_UBI0_AHB_CLK 167
#define GCC_UBI0_AXI_CLK 168
#define GCC_UBI0_NC_AXI_CLK 169
#define GCC_UBI0_CORE_CLK 170
#define GCC_UBI0_MPT_CLK 171
#define GCC_UBI1_AHB_CLK 172
#define GCC_UBI1_AXI_CLK 173
#define GCC_UBI1_NC_AXI_CLK 174
#define GCC_UBI1_CORE_CLK 175
#define GCC_UBI1_MPT_CLK 176
#define GCC_CMN_12GPLL_AHB_CLK 177
#define GCC_CMN_12GPLL_SYS_CLK 178
#define GCC_MDIO_AHB_CLK 179
#define GCC_UNIPHY0_AHB_CLK 180
#define GCC_UNIPHY0_SYS_CLK 181
#define GCC_UNIPHY1_AHB_CLK 182
#define GCC_UNIPHY1_SYS_CLK 183
#define GCC_UNIPHY2_AHB_CLK 184
#define GCC_UNIPHY2_SYS_CLK 185
#define GCC_NSS_PORT1_RX_CLK 186
#define GCC_NSS_PORT1_TX_CLK 187
#define GCC_NSS_PORT2_RX_CLK 188
#define GCC_NSS_PORT2_TX_CLK 189
#define GCC_NSS_PORT3_RX_CLK 190
#define GCC_NSS_PORT3_TX_CLK 191
#define GCC_NSS_PORT4_RX_CLK 192
#define GCC_NSS_PORT4_TX_CLK 193
#define GCC_NSS_PORT5_RX_CLK 194
#define GCC_NSS_PORT5_TX_CLK 195
#define GCC_NSS_PORT6_RX_CLK 196
#define GCC_NSS_PORT6_TX_CLK 197
#define GCC_PORT1_MAC_CLK 198
#define GCC_PORT2_MAC_CLK 199
#define GCC_PORT3_MAC_CLK 200
#define GCC_PORT4_MAC_CLK 201
#define GCC_PORT5_MAC_CLK 202
#define GCC_PORT6_MAC_CLK 203
#define GCC_UNIPHY0_PORT1_RX_CLK 204
#define GCC_UNIPHY0_PORT1_TX_CLK 205
#define GCC_UNIPHY0_PORT2_RX_CLK 206
#define GCC_UNIPHY0_PORT2_TX_CLK 207
#define GCC_UNIPHY0_PORT3_RX_CLK 208
#define GCC_UNIPHY0_PORT3_TX_CLK 209
#define GCC_UNIPHY0_PORT4_RX_CLK 210
#define GCC_UNIPHY0_PORT4_TX_CLK 211
#define GCC_UNIPHY0_PORT5_RX_CLK 212
#define GCC_UNIPHY0_PORT5_TX_CLK 213
#define GCC_UNIPHY1_PORT5_RX_CLK 214
#define GCC_UNIPHY1_PORT5_TX_CLK 215
#define GCC_UNIPHY2_PORT6_RX_CLK 216
#define GCC_UNIPHY2_PORT6_TX_CLK 217
#define GCC_CRYPTO_AHB_CLK 218
#define GCC_CRYPTO_AXI_CLK 219
#define GCC_CRYPTO_CLK 220
#define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@ -148,5 +328,47 @@
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
#define GCC_SMMU_CATS_BCR 88
#define GCC_UBI0_AXI_ARES 89
#define GCC_UBI0_AHB_ARES 90
#define GCC_UBI0_NC_AXI_ARES 91
#define GCC_UBI0_DBG_ARES 92
#define GCC_UBI0_CORE_CLAMP_ENABLE 93
#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94
#define GCC_UBI1_AXI_ARES 95
#define GCC_UBI1_AHB_ARES 96
#define GCC_UBI1_NC_AXI_ARES 97
#define GCC_UBI1_DBG_ARES 98
#define GCC_UBI1_CORE_CLAMP_ENABLE 99
#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100
#define GCC_NSS_CFG_ARES 101
#define GCC_NSS_IMEM_ARES 102
#define GCC_NSS_NOC_ARES 103
#define GCC_NSS_CRYPTO_ARES 104
#define GCC_NSS_CSR_ARES 105
#define GCC_NSS_CE_APB_ARES 106
#define GCC_NSS_CE_AXI_ARES 107
#define GCC_NSSNOC_CE_APB_ARES 108
#define GCC_NSSNOC_CE_AXI_ARES 109
#define GCC_NSSNOC_UBI0_AHB_ARES 110
#define GCC_NSSNOC_UBI1_AHB_ARES 111
#define GCC_NSSNOC_SNOC_ARES 112
#define GCC_NSSNOC_CRYPTO_ARES 113
#define GCC_NSSNOC_ATB_ARES 114
#define GCC_NSSNOC_QOSGEN_REF_ARES 115
#define GCC_NSSNOC_TIMEOUT_REF_ARES 116
#define GCC_PCIE0_PIPE_ARES 117
#define GCC_PCIE0_SLEEP_ARES 118
#define GCC_PCIE0_CORE_STICKY_ARES 119
#define GCC_PCIE0_AXI_MASTER_ARES 120
#define GCC_PCIE0_AXI_SLAVE_ARES 121
#define GCC_PCIE0_AHB_ARES 122
#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123
#define GCC_PCIE1_PIPE_ARES 124
#define GCC_PCIE1_SLEEP_ARES 125
#define GCC_PCIE1_CORE_STICKY_ARES 126
#define GCC_PCIE1_AXI_MASTER_ARES 127
#define GCC_PCIE1_AXI_SLAVE_ARES 128
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#endif

404
include/dt-bindings/clock/sprd,sc9860-clk.h Normal file
View file

@ -0,0 +1,404 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Spreadtrum SC9860 platform clocks
//
// Copyright (C) 2017, Spreadtrum Communications Inc.
#ifndef _DT_BINDINGS_CLK_SC9860_H_
#define _DT_BINDINGS_CLK_SC9860_H_
#define CLK_FAC_4M 0
#define CLK_FAC_2M 1
#define CLK_FAC_1M 2
#define CLK_FAC_250K 3
#define CLK_FAC_RPLL0_26M 4
#define CLK_FAC_RPLL1_26M 5
#define CLK_FAC_RCO25M 6
#define CLK_FAC_RCO4M 7
#define CLK_FAC_RCO2M 8
#define CLK_FAC_3K2 9
#define CLK_FAC_1K 10
#define CLK_MPLL0_GATE 11
#define CLK_MPLL1_GATE 12
#define CLK_DPLL0_GATE 13
#define CLK_DPLL1_GATE 14
#define CLK_LTEPLL0_GATE 15
#define CLK_TWPLL_GATE 16
#define CLK_LTEPLL1_GATE 17
#define CLK_RPLL0_GATE 18
#define CLK_RPLL1_GATE 19
#define CLK_CPPLL_GATE 20
#define CLK_GPLL_GATE 21
#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1)
#define CLK_MPLL0 0
#define CLK_MPLL1 1
#define CLK_DPLL0 2
#define CLK_DPLL1 3
#define CLK_RPLL0 4
#define CLK_RPLL1 5
#define CLK_TWPLL 6
#define CLK_LTEPLL0 7
#define CLK_LTEPLL1 8
#define CLK_GPLL 9
#define CLK_CPPLL 10
#define CLK_GPLL_42M5 11
#define CLK_TWPLL_768M 12
#define CLK_TWPLL_384M 13
#define CLK_TWPLL_192M 14
#define CLK_TWPLL_96M 15
#define CLK_TWPLL_48M 16
#define CLK_TWPLL_24M 17
#define CLK_TWPLL_12M 18
#define CLK_TWPLL_512M 19
#define CLK_TWPLL_256M 20
#define CLK_TWPLL_128M 21
#define CLK_TWPLL_64M 22
#define CLK_TWPLL_307M2 23
#define CLK_TWPLL_153M6 24
#define CLK_TWPLL_76M8 25
#define CLK_TWPLL_51M2 26
#define CLK_TWPLL_38M4 27
#define CLK_TWPLL_19M2 28
#define CLK_L0_614M4 29
#define CLK_L0_409M6 30
#define CLK_L0_38M 31
#define CLK_L1_38M 32
#define CLK_RPLL0_192M 33
#define CLK_RPLL0_96M 34
#define CLK_RPLL0_48M 35
#define CLK_RPLL1_468M 36
#define CLK_RPLL1_192M 37
#define CLK_RPLL1_96M 38
#define CLK_RPLL1_64M 39
#define CLK_RPLL1_48M 40
#define CLK_DPLL0_50M 41
#define CLK_DPLL1_50M 42
#define CLK_CPPLL_50M 43
#define CLK_M0_39M 44
#define CLK_M1_63M 45
#define CLK_PLL_NUM (CLK_M1_63M + 1)
#define CLK_AP_APB 0
#define CLK_AP_USB3 1
#define CLK_UART0 2
#define CLK_UART1 3
#define CLK_UART2 4
#define CLK_UART3 5
#define CLK_UART4 6
#define CLK_I2C0 7
#define CLK_I2C1 8
#define CLK_I2C2 9
#define CLK_I2C3 10
#define CLK_I2C4 11
#define CLK_I2C5 12
#define CLK_SPI0 13
#define CLK_SPI1 14
#define CLK_SPI2 15
#define CLK_SPI3 16
#define CLK_IIS0 17
#define CLK_IIS1 18
#define CLK_IIS2 19
#define CLK_IIS3 20
#define CLK_AP_CLK_NUM (CLK_IIS3 + 1)
#define CLK_AON_APB 0
#define CLK_AUX0 1
#define CLK_AUX1 2
#define CLK_AUX2 3
#define CLK_PROBE 4
#define CLK_SP_AHB 5
#define CLK_CCI 6
#define CLK_GIC 7
#define CLK_CSSYS 8
#define CLK_SDIO0_2X 9
#define CLK_SDIO1_2X 10
#define CLK_SDIO2_2X 11
#define CLK_EMMC_2X 12
#define CLK_SDIO0_1X 13
#define CLK_SDIO1_1X 14
#define CLK_SDIO2_1X 15
#define CLK_EMMC_1X 16
#define CLK_ADI 17
#define CLK_PWM0 18
#define CLK_PWM1 19
#define CLK_PWM2 20
#define CLK_PWM3 21
#define CLK_EFUSE 22
#define CLK_CM3_UART0 23
#define CLK_CM3_UART1 24
#define CLK_THM 25
#define CLK_CM3_I2C0 26
#define CLK_CM3_I2C1 27
#define CLK_CM4_SPI 28
#define CLK_AON_I2C 29
#define CLK_AVS 30
#define CLK_CA53_DAP 31
#define CLK_CA53_TS 32
#define CLK_DJTAG_TCK 33
#define CLK_PMU 34
#define CLK_PMU_26M 35
#define CLK_DEBOUNCE 36
#define CLK_OTG2_REF 37
#define CLK_USB3_REF 38
#define CLK_AP_AXI 39
#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1)
#define CLK_USB3_EB 0
#define CLK_USB3_SUSPEND_EB 1
#define CLK_USB3_REF_EB 2
#define CLK_DMA_EB 3
#define CLK_SDIO0_EB 4
#define CLK_SDIO1_EB 5
#define CLK_SDIO2_EB 6
#define CLK_EMMC_EB 7
#define CLK_ROM_EB 8
#define CLK_BUSMON_EB 9
#define CLK_CC63S_EB 10
#define CLK_CC63P_EB 11
#define CLK_CE0_EB 12
#define CLK_CE1_EB 13
#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1)
#define CLK_AVS_LIT_EB 0
#define CLK_AVS_BIG_EB 1
#define CLK_AP_INTC5_EB 2
#define CLK_GPIO_EB 3
#define CLK_PWM0_EB 4
#define CLK_PWM1_EB 5
#define CLK_PWM2_EB 6
#define CLK_PWM3_EB 7
#define CLK_KPD_EB 8
#define CLK_AON_SYS_EB 9
#define CLK_AP_SYS_EB 10
#define CLK_AON_TMR_EB 11
#define CLK_AP_TMR0_EB 12
#define CLK_EFUSE_EB 13
#define CLK_EIC_EB 14
#define CLK_PUB1_REG_EB 15
#define CLK_ADI_EB 16
#define CLK_AP_INTC0_EB 17
#define CLK_AP_INTC1_EB 18
#define CLK_AP_INTC2_EB 19
#define CLK_AP_INTC3_EB 20
#define CLK_AP_INTC4_EB 21
#define CLK_SPLK_EB 22
#define CLK_MSPI_EB 23
#define CLK_PUB0_REG_EB 24
#define CLK_PIN_EB 25
#define CLK_AON_CKG_EB 26
#define CLK_GPU_EB 27
#define CLK_APCPU_TS0_EB 28
#define CLK_APCPU_TS1_EB 29
#define CLK_DAP_EB 30
#define CLK_I2C_EB 31
#define CLK_PMU_EB 32
#define CLK_THM_EB 33
#define CLK_AUX0_EB 34
#define CLK_AUX1_EB 35
#define CLK_AUX2_EB 36
#define CLK_PROBE_EB 37
#define CLK_GPU0_AVS_EB 38
#define CLK_GPU1_AVS_EB 39
#define CLK_APCPU_WDG_EB 40
#define CLK_AP_TMR1_EB 41
#define CLK_AP_TMR2_EB 42
#define CLK_DISP_EMC_EB 43
#define CLK_ZIP_EMC_EB 44
#define CLK_GSP_EMC_EB 45
#define CLK_OSC_AON_EB 46
#define CLK_LVDS_TRX_EB 47
#define CLK_LVDS_TCXO_EB 48
#define CLK_MDAR_EB 49
#define CLK_RTC4M0_CAL_EB 50
#define CLK_RCT100M_CAL_EB 51
#define CLK_DJTAG_EB 52
#define CLK_MBOX_EB 53
#define CLK_AON_DMA_EB 54
#define CLK_DBG_EMC_EB 55
#define CLK_LVDS_PLL_DIV_EN 56
#define CLK_DEF_EB 57
#define CLK_AON_APB_RSV0 58
#define CLK_ORP_JTAG_EB 59
#define CLK_VSP_EB 60
#define CLK_CAM_EB 61
#define CLK_DISP_EB 62
#define CLK_DBG_AXI_IF_EB 63
#define CLK_SDIO0_2X_EN 64
#define CLK_SDIO1_2X_EN 65
#define CLK_SDIO2_2X_EN 66
#define CLK_EMMC_2X_EN 67
#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1)
#define CLK_LIT_MCU 0
#define CLK_BIG_MCU 1
#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1)
#define CLK_AGCP_IIS0_EB 0
#define CLK_AGCP_IIS1_EB 1
#define CLK_AGCP_IIS2_EB 2
#define CLK_AGCP_IIS3_EB 3
#define CLK_AGCP_UART_EB 4
#define CLK_AGCP_DMACP_EB 5
#define CLK_AGCP_DMAAP_EB 6
#define CLK_AGCP_ARC48K_EB 7
#define CLK_AGCP_SRC44P1K_EB 8
#define CLK_AGCP_MCDT_EB 9
#define CLK_AGCP_VBCIFD_EB 10
#define CLK_AGCP_VBC_EB 11
#define CLK_AGCP_SPINLOCK_EB 12
#define CLK_AGCP_ICU_EB 13
#define CLK_AGCP_AP_ASHB_EB 14
#define CLK_AGCP_CP_ASHB_EB 15
#define CLK_AGCP_AUD_EB 16
#define CLK_AGCP_AUDIF_EB 17
#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1)
#define CLK_GPU 0
#define CLK_GPU_NUM (CLK_GPU + 1)
#define CLK_AHB_VSP 0
#define CLK_VSP 1
#define CLK_VSP_ENC 2
#define CLK_VPP 3
#define CLK_VSP_26M 4
#define CLK_VSP_NUM (CLK_VSP_26M + 1)
#define CLK_VSP_DEC_EB 0
#define CLK_VSP_CKG_EB 1
#define CLK_VSP_MMU_EB 2
#define CLK_VSP_ENC_EB 3
#define CLK_VPP_EB 4
#define CLK_VSP_26M_EB 5
#define CLK_VSP_AXI_GATE 6
#define CLK_VSP_ENC_GATE 7
#define CLK_VPP_AXI_GATE 8
#define CLK_VSP_BM_GATE 9
#define CLK_VSP_ENC_BM_GATE 10
#define CLK_VPP_BM_GATE 11
#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1)
#define CLK_AHB_CAM 0
#define CLK_SENSOR0 1
#define CLK_SENSOR1 2
#define CLK_SENSOR2 3
#define CLK_MIPI_CSI0_EB 4
#define CLK_MIPI_CSI1_EB 5
#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1)
#define CLK_DCAM0_EB 0
#define CLK_DCAM1_EB 1
#define CLK_ISP0_EB 2
#define CLK_CSI0_EB 3
#define CLK_CSI1_EB 4
#define CLK_JPG0_EB 5
#define CLK_JPG1_EB 6
#define CLK_CAM_CKG_EB 7
#define CLK_CAM_MMU_EB 8
#define CLK_ISP1_EB 9
#define CLK_CPP_EB 10
#define CLK_MMU_PF_EB 11
#define CLK_ISP2_EB 12
#define CLK_DCAM2ISP_IF_EB 13
#define CLK_ISP2DCAM_IF_EB 14
#define CLK_ISP_LCLK_EB 15
#define CLK_ISP_ICLK_EB 16
#define CLK_ISP_MCLK_EB 17
#define CLK_ISP_PCLK_EB 18
#define CLK_ISP_ISP2DCAM_EB 19
#define CLK_DCAM0_IF_EB 20
#define CLK_CLK26M_IF_EB 21
#define CLK_CPHY0_GATE 22
#define CLK_MIPI_CSI0_GATE 23
#define CLK_CPHY1_GATE 24
#define CLK_MIPI_CSI1 25
#define CLK_DCAM0_AXI_GATE 26
#define CLK_DCAM1_AXI_GATE 27
#define CLK_SENSOR0_GATE 28
#define CLK_SENSOR1_GATE 29
#define CLK_JPG0_AXI_GATE 30
#define CLK_GPG1_AXI_GATE 31
#define CLK_ISP0_AXI_GATE 32
#define CLK_ISP1_AXI_GATE 33
#define CLK_ISP2_AXI_GATE 34
#define CLK_CPP_AXI_GATE 35
#define CLK_D0_IF_AXI_GATE 36
#define CLK_D2I_IF_AXI_GATE 37
#define CLK_I2D_IF_AXI_GATE 38
#define CLK_SPARE_AXI_GATE 39
#define CLK_SENSOR2_GATE 40
#define CLK_D0IF_IN_D_EN 41
#define CLK_D1IF_IN_D_EN 42
#define CLK_D0IF_IN_D2I_EN 43
#define CLK_D1IF_IN_D2I_EN 44
#define CLK_IA_IN_D2I_EN 45
#define CLK_IB_IN_D2I_EN 46
#define CLK_IC_IN_D2I_EN 47
#define CLK_IA_IN_I_EN 48
#define CLK_IB_IN_I_EN 49
#define CLK_IC_IN_I_EN 50
#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1)
#define CLK_AHB_DISP 0
#define CLK_DISPC0_DPI 1
#define CLK_DISPC1_DPI 2
#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1)
#define CLK_DISPC0_EB 0
#define CLK_DISPC1_EB 1
#define CLK_DISPC_MMU_EB 2
#define CLK_GSP0_EB 3
#define CLK_GSP1_EB 4
#define CLK_GSP0_MMU_EB 5
#define CLK_GSP1_MMU_EB 6
#define CLK_DSI0_EB 7
#define CLK_DSI1_EB 8
#define CLK_DISP_CKG_EB 9
#define CLK_DISP_GPU_EB 10
#define CLK_GPU_MTX_EB 11
#define CLK_GSP_MTX_EB 12
#define CLK_TMC_MTX_EB 13
#define CLK_DISPC_MTX_EB 14
#define CLK_DPHY0_GATE 15
#define CLK_DPHY1_GATE 16
#define CLK_GSP0_A_GATE 17
#define CLK_GSP1_A_GATE 18
#define CLK_GSP0_F_GATE 19
#define CLK_GSP1_F_GATE 20
#define CLK_D_MTX_F_GATE 21
#define CLK_D_MTX_A_GATE 22
#define CLK_D_NOC_F_GATE 23
#define CLK_D_NOC_A_GATE 24
#define CLK_GSP_MTX_F_GATE 25
#define CLK_GSP_MTX_A_GATE 26
#define CLK_GSP_NOC_F_GATE 27
#define CLK_GSP_NOC_A_GATE 28
#define CLK_DISPM0IDLE_GATE 29
#define CLK_GSPM0IDLE_GATE 30
#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1)
#define CLK_SIM0_EB 0
#define CLK_IIS0_EB 1
#define CLK_IIS1_EB 2
#define CLK_IIS2_EB 3
#define CLK_IIS3_EB 4
#define CLK_SPI0_EB 5
#define CLK_SPI1_EB 6
#define CLK_SPI2_EB 7
#define CLK_I2C0_EB 8
#define CLK_I2C1_EB 9
#define CLK_I2C2_EB 10
#define CLK_I2C3_EB 11
#define CLK_I2C4_EB 12
#define CLK_I2C5_EB 13
#define CLK_UART0_EB 14
#define CLK_UART1_EB 15
#define CLK_UART2_EB 16
#define CLK_UART3_EB 17
#define CLK_UART4_EB 18
#define CLK_AP_CKG_EB 19
#define CLK_SPI3_EB 20
#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1)
#endif /* _DT_BINDINGS_CLK_SC9860_H_ */

49
include/dt-bindings/gpio/aspeed-gpio.h Normal file
View file

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* This header provides constants for binding aspeed,*-gpio.
*
* The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define ASPEED_GPIO_PORT_A 0
#define ASPEED_GPIO_PORT_B 1
#define ASPEED_GPIO_PORT_C 2
#define ASPEED_GPIO_PORT_D 3
#define ASPEED_GPIO_PORT_E 4
#define ASPEED_GPIO_PORT_F 5
#define ASPEED_GPIO_PORT_G 6
#define ASPEED_GPIO_PORT_H 7
#define ASPEED_GPIO_PORT_I 8
#define ASPEED_GPIO_PORT_J 9
#define ASPEED_GPIO_PORT_K 10
#define ASPEED_GPIO_PORT_L 11
#define ASPEED_GPIO_PORT_M 12
#define ASPEED_GPIO_PORT_N 13
#define ASPEED_GPIO_PORT_O 14
#define ASPEED_GPIO_PORT_P 15
#define ASPEED_GPIO_PORT_Q 16
#define ASPEED_GPIO_PORT_R 17
#define ASPEED_GPIO_PORT_S 18
#define ASPEED_GPIO_PORT_T 19
#define ASPEED_GPIO_PORT_U 20
#define ASPEED_GPIO_PORT_V 21
#define ASPEED_GPIO_PORT_W 22
#define ASPEED_GPIO_PORT_X 23
#define ASPEED_GPIO_PORT_Y 24
#define ASPEED_GPIO_PORT_Z 25
#define ASPEED_GPIO_PORT_AA 26
#define ASPEED_GPIO_PORT_AB 27
#define ASPEED_GPIO_PORT_AC 28
#define ASPEED_GPIO(port, offset) \
((ASPEED_GPIO_PORT_##port * 8) + offset)
#endif

6
include/dt-bindings/gpio/gpio.h
View file

@ -29,8 +29,8 @@
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/* Bit 3 express GPIO suspend/resume persistence */
#define GPIO_SLEEP_MAINTAIN_VALUE 0
#define GPIO_SLEEP_MAY_LOSE_VALUE 8
/* Bit 3 express GPIO suspend/resume and reset persistence */
#define GPIO_PERSISTENT 0
#define GPIO_TRANSITORY 8
#endif

116
include/dt-bindings/gpio/meson-axg-gpio.h Normal file
View file

@ -0,0 +1,116 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
#define _DT_BINDINGS_MESON_AXG_GPIO_H
/* First GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_TEST_N 14
/* Second GPIO chip */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define BOOT_0 11
#define BOOT_1 12
#define BOOT_2 13
#define BOOT_3 14
#define BOOT_4 15
#define BOOT_5 16
#define BOOT_6 17
#define BOOT_7 18
#define BOOT_8 19
#define BOOT_9 20
#define BOOT_10 21
#define BOOT_11 22
#define BOOT_12 23
#define BOOT_13 24
#define BOOT_14 25
#define GPIOA_0 26
#define GPIOA_1 27
#define GPIOA_2 28
#define GPIOA_3 29
#define GPIOA_4 30
#define GPIOA_5 31
#define GPIOA_6 32
#define GPIOA_7 33
#define GPIOA_8 34
#define GPIOA_9 35
#define GPIOA_10 36
#define GPIOA_11 37
#define GPIOA_12 38
#define GPIOA_13 39
#define GPIOA_14 40
#define GPIOA_15 41
#define GPIOA_16 42
#define GPIOA_17 43
#define GPIOA_18 44
#define GPIOA_19 45
#define GPIOA_20 46
#define GPIOX_0 47
#define GPIOX_1 48
#define GPIOX_2 49
#define GPIOX_3 50
#define GPIOX_4 51
#define GPIOX_5 52
#define GPIOX_6 53
#define GPIOX_7 54
#define GPIOX_8 55
#define GPIOX_9 56
#define GPIOX_10 57
#define GPIOX_11 58
#define GPIOX_12 59
#define GPIOX_13 60
#define GPIOX_14 61
#define GPIOX_15 62
#define GPIOX_16 63
#define GPIOX_17 64
#define GPIOX_18 65
#define GPIOX_19 66
#define GPIOX_20 67
#define GPIOX_21 68
#define GPIOX_22 69
#define GPIOY_0 70
#define GPIOY_1 71
#define GPIOY_2 72
#define GPIOY_3 73
#define GPIOY_4 74
#define GPIOY_5 75
#define GPIOY_6 76
#define GPIOY_7 77
#define GPIOY_8 78
#define GPIOY_9 79
#define GPIOY_10 80
#define GPIOY_11 81
#define GPIOY_12 82
#define GPIOY_13 83
#define GPIOY_14 84
#define GPIOY_15 85
#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */

111
include/dt-bindings/memory/tegra186-mc.h Normal file
View file

@ -0,0 +1,111 @@
#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
/* special clients */
#define TEGRA186_SID_INVALID 0x00
#define TEGRA186_SID_PASSTHROUGH 0x7f
/* host1x clients */
#define TEGRA186_SID_HOST1X 0x01
#define TEGRA186_SID_CSI 0x02
#define TEGRA186_SID_VIC 0x03
#define TEGRA186_SID_VI 0x04
#define TEGRA186_SID_ISP 0x05
#define TEGRA186_SID_NVDEC 0x06
#define TEGRA186_SID_NVENC 0x07
#define TEGRA186_SID_NVJPG 0x08
#define TEGRA186_SID_NVDISPLAY 0x09
#define TEGRA186_SID_TSEC 0x0a
#define TEGRA186_SID_TSECB 0x0b
#define TEGRA186_SID_SE 0x0c
#define TEGRA186_SID_SE1 0x0d
#define TEGRA186_SID_SE2 0x0e
#define TEGRA186_SID_SE3 0x0f
/* GPU clients */
#define TEGRA186_SID_GPU 0x10
/* other SoC clients */
#define TEGRA186_SID_AFI 0x11
#define TEGRA186_SID_HDA 0x12
#define TEGRA186_SID_ETR 0x13
#define TEGRA186_SID_EQOS 0x14
#define TEGRA186_SID_UFSHC 0x15
#define TEGRA186_SID_AON 0x16
#define TEGRA186_SID_SDMMC4 0x17
#define TEGRA186_SID_SDMMC3 0x18
#define TEGRA186_SID_SDMMC2 0x19
#define TEGRA186_SID_SDMMC1 0x1a
#define TEGRA186_SID_XUSB_HOST 0x1b
#define TEGRA186_SID_XUSB_DEV 0x1c
#define TEGRA186_SID_SATA 0x1d
#define TEGRA186_SID_APE 0x1e
#define TEGRA186_SID_SCE 0x1f
/* GPC DMA clients */
#define TEGRA186_SID_GPCDMA_0 0x20
#define TEGRA186_SID_GPCDMA_1 0x21
#define TEGRA186_SID_GPCDMA_2 0x22
#define TEGRA186_SID_GPCDMA_3 0x23
#define TEGRA186_SID_GPCDMA_4 0x24
#define TEGRA186_SID_GPCDMA_5 0x25
#define TEGRA186_SID_GPCDMA_6 0x26
#define TEGRA186_SID_GPCDMA_7 0x27
/* APE DMA clients */
#define TEGRA186_SID_APE_1 0x28
#define TEGRA186_SID_APE_2 0x29
/* camera RTCPU */
#define TEGRA186_SID_RCE 0x2a
/* camera RTCPU on host1x address space */
#define TEGRA186_SID_RCE_1X 0x2b
/* APE DMA clients */
#define TEGRA186_SID_APE_3 0x2c
/* camera RTCPU running on APE */
#define TEGRA186_SID_APE_CAM 0x2d
#define TEGRA186_SID_APE_CAM_1X 0x2e
/*
* The BPMP has its SID value hardcoded in the firmware. Changing it requires
* considerable effort.
*/
#define TEGRA186_SID_BPMP 0x32
/* for SMMU tests */
#define TEGRA186_SID_SMMU_TEST 0x33
/* host1x virtualization channels */
#define TEGRA186_SID_HOST1X_CTX0 0x38
#define TEGRA186_SID_HOST1X_CTX1 0x39
#define TEGRA186_SID_HOST1X_CTX2 0x3a
#define TEGRA186_SID_HOST1X_CTX3 0x3b
#define TEGRA186_SID_HOST1X_CTX4 0x3c
#define TEGRA186_SID_HOST1X_CTX5 0x3d
#define TEGRA186_SID_HOST1X_CTX6 0x3e
#define TEGRA186_SID_HOST1X_CTX7 0x3f
/* host1x command buffers */
#define TEGRA186_SID_HOST1X_VM0 0x40
#define TEGRA186_SID_HOST1X_VM1 0x41
#define TEGRA186_SID_HOST1X_VM2 0x42
#define TEGRA186_SID_HOST1X_VM3 0x43
#define TEGRA186_SID_HOST1X_VM4 0x44
#define TEGRA186_SID_HOST1X_VM5 0x45
#define TEGRA186_SID_HOST1X_VM6 0x46
#define TEGRA186_SID_HOST1X_VM7 0x47
/* SE data buffers */
#define TEGRA186_SID_SE_VM0 0x48
#define TEGRA186_SID_SE_VM1 0x49
#define TEGRA186_SID_SE_VM2 0x4a
#define TEGRA186_SID_SE_VM3 0x4b
#define TEGRA186_SID_SE_VM4 0x4c
#define TEGRA186_SID_SE_VM5 0x4d
#define TEGRA186_SID_SE_VM6 0x4e
#define TEGRA186_SID_SE_VM7 0x4f
#endif

3
include/dt-bindings/pinctrl/am43xx.h
View file

@ -25,7 +25,8 @@
#define DS0_FORCE_OFF_MODE (1 << 24)
#define DS0_INPUT (1 << 25)
#define DS0_FORCE_OUT_HIGH (1 << 26)
#define DS0_PULL_UP_DOWN_EN (1 << 27)
#define DS0_PULL_UP_DOWN_EN (0 << 27)
#define DS0_PULL_UP_DOWN_DIS (1 << 27)
#define DS0_PULL_UP_SEL (1 << 28)
#define WAKEUP_ENABLE (1 << 29)

6
include/dt-bindings/pinctrl/stm32-pinfunc.h
View file

@ -1,3 +1,9 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
#define _DT_BINDINGS_STM32_PINFUNC_H

26
include/dt-bindings/power/mt2712-power.h Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (C) 2017 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H
#define _DT_BINDINGS_POWER_MT2712_POWER_H
#define MT2712_POWER_DOMAIN_MM 0
#define MT2712_POWER_DOMAIN_VDEC 1
#define MT2712_POWER_DOMAIN_VENC 2
#define MT2712_POWER_DOMAIN_ISP 3
#define MT2712_POWER_DOMAIN_AUDIO 4
#define MT2712_POWER_DOMAIN_USB 5
#define MT2712_POWER_DOMAIN_USB2 6
#define MT2712_POWER_DOMAIN_MFG 7
#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */

19
include/dt-bindings/power/owl-s700-powergate.h Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Actions Semi S700 SPS
*
* Copyright (c) 2017 Andreas Färber
*/
#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
#define S700_PD_VDE 0
#define S700_PD_VCE_SI 1
#define S700_PD_USB2_1 2
#define S700_PD_HDE 3
#define S700_PD_DMA 4
#define S700_PD_DS 5
#define S700_PD_USB3 6
#define S700_PD_USB2_0 7
#endif

124
include/dt-bindings/reset/amlogic,meson-axg-reset.h Normal file
View file

@ -0,0 +1,124 @@
/*
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2017 Amlogic, inc.
* Author: Yixun Lan <yixun.lan@amlogic.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD)
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
/* RESET0 */
#define RESET_HIU 0
#define RESET_PCIE_A 1
#define RESET_PCIE_B 2
#define RESET_DDR_TOP 3
/* 4 */
#define RESET_VIU 5
#define RESET_PCIE_PHY 6
#define RESET_PCIE_APB 7
/* 8 */
/* 9 */
#define RESET_VENC 10
#define RESET_ASSIST 11
/* 12 */
#define RESET_VCBUS 13
/* 14 */
/* 15 */
#define RESET_GIC 16
#define RESET_CAPB3_DECODE 17
/* 18-21 */
#define RESET_SYS_CPU_CAPB3 22
#define RESET_CBUS_CAPB3 23
#define RESET_AHB_CNTL 24
#define RESET_AHB_DATA 25
#define RESET_VCBUS_CLK81 26
#define RESET_MMC 27
/* 28-31 */
/* RESET1 */
/* 32 */
/* 33 */
#define RESET_USB_OTG 34
#define RESET_DDR 35
#define RESET_AO_RESET 36
/* 37 */
#define RESET_AHB_SRAM 38
/* 39 */
/* 40 */
#define RESET_DMA 41
#define RESET_ISA 42
#define RESET_ETHERNET 43
/* 44 */
#define RESET_SD_EMMC_B 45
#define RESET_SD_EMMC_C 46
#define RESET_ROM_BOOT 47
#define RESET_SYS_CPU_0 48
#define RESET_SYS_CPU_1 49
#define RESET_SYS_CPU_2 50
#define RESET_SYS_CPU_3 51
#define RESET_SYS_CPU_CORE_0 52
#define RESET_SYS_CPU_CORE_1 53
#define RESET_SYS_CPU_CORE_2 54
#define RESET_SYS_CPU_CORE_3 55
#define RESET_SYS_PLL_DIV 56
#define RESET_SYS_CPU_AXI 57
#define RESET_SYS_CPU_L2 58
#define RESET_SYS_CPU_P 59
#define RESET_SYS_CPU_MBIST 60
/* 61-63 */
/* RESET2 */
/* 64 */
/* 65 */
#define RESET_AUDIO 66
/* 67 */
#define RESET_MIPI_HOST 68
#define RESET_AUDIO_LOCKER 69
#define RESET_GE2D 70
/* 71-76 */
#define RESET_AO_CPU_RESET 77
/* 78-95 */
/* RESET3 */
#define RESET_RING_OSCILLATOR 96
/* 97-127 */
/* RESET4 */
/* 128 */
/* 129 */
#define RESET_MIPI_PHY 130
/* 131-140 */
#define RESET_VENCL 141
#define RESET_I2C_MASTER_2 142
#define RESET_I2C_MASTER_1 143
/* 144-159 */
/* RESET5 */
/* 160-191 */
/* RESET6 */
#define RESET_PERIPHS_GENERAL 192
#define RESET_PERIPHS_SPICC 193
/* 194 */
/* 195 */
#define RESET_PERIPHS_I2C_MASTER_0 196
/* 197-200 */
#define RESET_PERIPHS_UART_0 201
#define RESET_PERIPHS_UART_1 202
/* 203-204 */
#define RESET_PERIPHS_SPI_0 205
#define RESET_PERIPHS_I2C_MASTER_3 206
/* 207-223 */
/* RESET7 */
#define RESET_USB_DDR_0 224
#define RESET_USB_DDR_1 225
#define RESET_USB_DDR_2 226
#define RESET_USB_DDR_3 227
/* 228 */
#define RESET_DEVICE_MMC_ARB 229
/* 230 */
#define RESET_VID_LOCK 231
#define RESET_A9_DMC_PIPEL 232
#define RESET_DMC_VPU_PIPEL 233
/* 234-255 */
#endif

2
include/kvm/arm_arch_timer.h
View file

@ -90,6 +90,8 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
void kvm_timer_init_vhe(void);
bool kvm_arch_timer_get_input_level(int vintid);
#define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer)
#define vcpu_ptimer(v) (&(v)->arch.timer_cpu.ptimer)

51
include/kvm/arm_psci.h Normal file
View file

@ -0,0 +1,51 @@
/*
* Copyright (C) 2012,2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __KVM_ARM_PSCI_H__
#define __KVM_ARM_PSCI_H__
#include <linux/kvm_host.h>
#include <uapi/linux/psci.h>
#define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1)
#define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2)
#define KVM_ARM_PSCI_1_0 PSCI_VERSION(1, 0)
#define KVM_ARM_PSCI_LATEST KVM_ARM_PSCI_1_0
/*
* We need the KVM pointer independently from the vcpu as we can call
* this from HYP, and need to apply kern_hyp_va on it...
*/
static inline int kvm_psci_version(struct kvm_vcpu *vcpu, struct kvm *kvm)
{
/*
* Our PSCI implementation stays the same across versions from
* v0.2 onward, only adding the few mandatory functions (such
* as FEATURES with 1.0) that are required by newer
* revisions. It is thus safe to return the latest.
*/
if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
return KVM_ARM_PSCI_LATEST;
return KVM_ARM_PSCI_0_1;
}
int kvm_hvc_call_handler(struct kvm_vcpu *vcpu);
#endif /* __KVM_ARM_PSCI_H__ */

13
include/kvm/arm_vgic.h
View file

@ -130,6 +130,17 @@ struct vgic_irq {
u8 priority;
enum vgic_irq_config config; /* Level or edge */
/*
* Callback function pointer to in-kernel devices that can tell us the
* state of the input level of mapped level-triggered IRQ faster than
* peaking into the physical GIC.
*
* Always called in non-preemptible section and the functions can use
* kvm_arm_get_running_vcpu() to get the vcpu pointer for private
* IRQs.
*/
bool (*get_input_level)(int vintid);
void *owner; /* Opaque pointer to reserve an interrupt
for in-kernel devices. */
};
@ -331,7 +342,7 @@ void kvm_vgic_init_cpu_hardware(void);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
bool level, void *owner);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
u32 vintid);
u32 vintid, bool (*get_input_level)(int vindid));
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);

28
include/linux/acpi.h
View file

@ -56,6 +56,8 @@ static inline acpi_handle acpi_device_handle(struct acpi_device *adev)
#define ACPI_COMPANION_SET(dev, adev) set_primary_fwnode(dev, (adev) ? \
acpi_fwnode_handle(adev) : NULL)
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
#define ACPI_HANDLE_FWNODE(fwnode) \
acpi_device_handle(to_acpi_device_node(fwnode))
static inline struct fwnode_handle *acpi_alloc_fwnode_static(void)
{
@ -451,6 +453,7 @@ void __init acpi_no_s4_hw_signature(void);
void __init acpi_old_suspend_ordering(void);
void __init acpi_nvs_nosave(void);
void __init acpi_nvs_nosave_s3(void);
void __init acpi_sleep_no_blacklist(void);
#endif /* CONFIG_PM_SLEEP */
struct acpi_osc_context {
@ -584,6 +587,7 @@ extern int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
const struct device *dev);
void *acpi_get_match_data(const struct device *dev);
extern bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv);
int acpi_device_uevent_modalias(struct device *, struct kobj_uevent_env *);
@ -626,6 +630,7 @@ int acpi_arch_timer_mem_init(struct arch_timer_mem *timer_mem, int *timer_count)
#define ACPI_COMPANION(dev) (NULL)
#define ACPI_COMPANION_SET(dev, adev) do { } while (0)
#define ACPI_HANDLE(dev) (NULL)
#define ACPI_HANDLE_FWNODE(fwnode) (NULL)
#define ACPI_DEVICE_CLASS(_cls, _msk) .cls = (0), .cls_msk = (0),
struct fwnode_handle;
@ -640,6 +645,12 @@ static inline bool acpi_dev_present(const char *hid, const char *uid, s64 hrv)
return false;
}
static inline const char *
acpi_dev_get_first_match_name(const char *hid, const char *uid, s64 hrv)
{
return NULL;
}
static inline bool is_acpi_node(struct fwnode_handle *fwnode)
{
return false;
@ -755,6 +766,11 @@ static inline const struct acpi_device_id *acpi_match_device(
return NULL;
}
static inline void *acpi_get_match_data(const struct device *dev)
{
return NULL;
}
static inline bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv)
{
@ -978,6 +994,11 @@ struct acpi_gpio_mapping {
const char *name;
const struct acpi_gpio_params *data;
unsigned int size;
/* Ignore IoRestriction field */
#define ACPI_GPIO_QUIRK_NO_IO_RESTRICTION BIT(0)
unsigned int quirks;
};
#if defined(CONFIG_ACPI) && defined(CONFIG_GPIOLIB)
@ -1242,9 +1263,12 @@ static inline bool acpi_has_watchdog(void) { return false; }
#ifdef CONFIG_ACPI_SPCR_TABLE
extern bool qdf2400_e44_present;
int parse_spcr(bool earlycon);
int acpi_parse_spcr(bool enable_earlycon, bool enable_console);
#else
static inline int parse_spcr(bool earlycon) { return 0; }
static inline int acpi_parse_spcr(bool enable_earlycon, bool enable_console)
{
return 0;
}
#endif
#if IS_ENABLED(CONFIG_ACPI_GENERIC_GSI)

2
include/linux/arch_topology.h
View file

@ -27,7 +27,7 @@ void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity);
DECLARE_PER_CPU(unsigned long, freq_scale);
static inline
unsigned long topology_get_freq_scale(struct sched_domain *sd, int cpu)
unsigned long topology_get_freq_scale(int cpu)
{
return per_cpu(freq_scale, cpu);
}

165
include/linux/arm-smccc.h
View file

@ -14,14 +14,16 @@
#ifndef __LINUX_ARM_SMCCC_H
#define __LINUX_ARM_SMCCC_H
#include <uapi/linux/const.h>
/*
* This file provides common defines for ARM SMC Calling Convention as
* specified in
* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
*/
#define ARM_SMCCC_STD_CALL 0
#define ARM_SMCCC_FAST_CALL 1
#define ARM_SMCCC_STD_CALL _AC(0,U)
#define ARM_SMCCC_FAST_CALL _AC(1,U)
#define ARM_SMCCC_TYPE_SHIFT 31
#define ARM_SMCCC_SMC_32 0
@ -60,6 +62,24 @@
#define ARM_SMCCC_QUIRK_NONE 0
#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
#define ARM_SMCCC_VERSION_1_0 0x10000
#define ARM_SMCCC_VERSION_1_1 0x10001
#define ARM_SMCCC_VERSION_FUNC_ID \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
ARM_SMCCC_SMC_32, \
0, 0)
#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
ARM_SMCCC_SMC_32, \
0, 1)
#define ARM_SMCCC_ARCH_WORKAROUND_1 \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
ARM_SMCCC_SMC_32, \
0, 0x8000)
#ifndef __ASSEMBLY__
#include <linux/linkage.h>
@ -130,5 +150,146 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
/* SMCCC v1.1 implementation madness follows */
#ifdef CONFIG_ARM64
#define SMCCC_SMC_INST "smc #0"
#define SMCCC_HVC_INST "hvc #0"
#elif defined(CONFIG_ARM)
#include <asm/opcodes-sec.h>
#include <asm/opcodes-virt.h>
#define SMCCC_SMC_INST __SMC(0)
#define SMCCC_HVC_INST __HVC(0)
#endif
#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x
#define __count_args(...) \
___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
#define __constraint_write_0 \
"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3)
#define __constraint_write_1 \
"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3)
#define __constraint_write_2 \
"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3)
#define __constraint_write_3 \
"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3)
#define __constraint_write_4 __constraint_write_3
#define __constraint_write_5 __constraint_write_4
#define __constraint_write_6 __constraint_write_5
#define __constraint_write_7 __constraint_write_6
#define __constraint_read_0
#define __constraint_read_1
#define __constraint_read_2
#define __constraint_read_3
#define __constraint_read_4 "r" (r4)
#define __constraint_read_5 __constraint_read_4, "r" (r5)
#define __constraint_read_6 __constraint_read_5, "r" (r6)
#define __constraint_read_7 __constraint_read_6, "r" (r7)
#define __declare_arg_0(a0, res) \
struct arm_smccc_res *___res = res; \
register u32 r0 asm("r0") = a0; \
register unsigned long r1 asm("r1"); \
register unsigned long r2 asm("r2"); \
register unsigned long r3 asm("r3")
#define __declare_arg_1(a0, a1, res) \
struct arm_smccc_res *___res = res; \
register u32 r0 asm("r0") = a0; \
register typeof(a1) r1 asm("r1") = a1; \
register unsigned long r2 asm("r2"); \
register unsigned long r3 asm("r3")
#define __declare_arg_2(a0, a1, a2, res) \
struct arm_smccc_res *___res = res; \
register u32 r0 asm("r0") = a0; \
register typeof(a1) r1 asm("r1") = a1; \
register typeof(a2) r2 asm("r2") = a2; \
register unsigned long r3 asm("r3")
#define __declare_arg_3(a0, a1, a2, a3, res) \
struct arm_smccc_res *___res = res; \
register u32 r0 asm("r0") = a0; \
register typeof(a1) r1 asm("r1") = a1; \
register typeof(a2) r2 asm("r2") = a2; \
register typeof(a3) r3 asm("r3") = a3
#define __declare_arg_4(a0, a1, a2, a3, a4, res) \
__declare_arg_3(a0, a1, a2, a3, res); \
register typeof(a4) r4 asm("r4") = a4
#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \
__declare_arg_4(a0, a1, a2, a3, a4, res); \
register typeof(a5) r5 asm("r5") = a5
#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \
__declare_arg_5(a0, a1, a2, a3, a4, a5, res); \
register typeof(a6) r6 asm("r6") = a6
#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \
__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \
register typeof(a7) r7 asm("r7") = a7
#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)
#define ___constraints(count) \
: __constraint_write_ ## count \
: __constraint_read_ ## count \
: "memory"
#define __constraints(count) ___constraints(count)
/*
* We have an output list that is not necessarily used, and GCC feels
* entitled to optimise the whole sequence away. "volatile" is what
* makes it stick.
*/
#define __arm_smccc_1_1(inst, ...) \
do { \
__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
asm volatile(inst "\n" \
__constraints(__count_args(__VA_ARGS__))); \
if (___res) \
*___res = (typeof(*___res)){r0, r1, r2, r3}; \
} while (0)
/*
* arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call
*
* This is a variadic macro taking one to eight source arguments, and
* an optional return structure.
*
* @a0-a7: arguments passed in registers 0 to 7
* @res: result values from registers 0 to 3
*
* This macro is used to make SMC calls following SMC Calling Convention v1.1.
* The content of the supplied param are copied to registers 0 to 7 prior
* to the SMC instruction. The return values are updated with the content
* from register 0 to 3 on return from the SMC instruction if not NULL.
*/
#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__)
/*
* arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call
*
* This is a variadic macro taking one to eight source arguments, and
* an optional return structure.
*
* @a0-a7: arguments passed in registers 0 to 7
* @res: result values from registers 0 to 3
*
* This macro is used to make HVC calls following SMC Calling Convention v1.1.
* The content of the supplied param are copied to registers 0 to 7 prior
* to the HVC instruction. The return values are updated with the content
* from register 0 to 3 on return from the HVC instruction if not NULL.
*/
#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__)
#endif /*__ASSEMBLY__*/
#endif /*__LINUX_ARM_SMCCC_H*/

79
include/linux/arm_sdei.h Normal file
View file

@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2017 Arm Ltd.
#ifndef __LINUX_ARM_SDEI_H
#define __LINUX_ARM_SDEI_H
#include <uapi/linux/arm_sdei.h>
enum sdei_conduit_types {
CONDUIT_INVALID = 0,
CONDUIT_SMC,
CONDUIT_HVC,
};
#include <asm/sdei.h>
/* Arch code should override this to set the entry point from firmware... */
#ifndef sdei_arch_get_entry_point
#define sdei_arch_get_entry_point(conduit) (0)
#endif
/*
* When an event occurs sdei_event_handler() will call a user-provided callback
* like this in NMI context on the CPU that received the event.
*/
typedef int (sdei_event_callback)(u32 event, struct pt_regs *regs, void *arg);
/*
* Register your callback to claim an event. The event must be described
* by firmware.
*/
int sdei_event_register(u32 event_num, sdei_event_callback *cb, void *arg);
/*
* Calls to sdei_event_unregister() may return EINPROGRESS. Keep calling
* it until it succeeds.
*/
int sdei_event_unregister(u32 event_num);
int sdei_event_enable(u32 event_num);
int sdei_event_disable(u32 event_num);
#ifdef CONFIG_ARM_SDE_INTERFACE
/* For use by arch code when CPU hotplug notifiers are not appropriate. */
int sdei_mask_local_cpu(void);
int sdei_unmask_local_cpu(void);
#else
static inline int sdei_mask_local_cpu(void) { return 0; }
static inline int sdei_unmask_local_cpu(void) { return 0; }
#endif /* CONFIG_ARM_SDE_INTERFACE */
/*
* This struct represents an event that has been registered. The driver
* maintains a list of all events, and which ones are registered. (Private
* events have one entry in the list, but are registered on each CPU).
* A pointer to this struct is passed to firmware, and back to the event
* handler. The event handler can then use this to invoke the registered
* callback, without having to walk the list.
*
* For CPU private events, this structure is per-cpu.
*/
struct sdei_registered_event {
/* For use by arch code: */
struct pt_regs interrupted_regs;
sdei_event_callback *callback;
void *callback_arg;
u32 event_num;
u8 priority;
};
/* The arch code entry point should then call this when an event arrives. */
int notrace sdei_event_handler(struct pt_regs *regs,
struct sdei_registered_event *arg);
/* arch code may use this to retrieve the extra registers. */
int sdei_api_event_context(u32 query, u64 *result);
#endif /* __LINUX_ARM_SDEI_H */

2
include/linux/ata.h
View file

@ -448,6 +448,8 @@ enum {
ATA_SET_MAX_LOCK = 0x02,
ATA_SET_MAX_UNLOCK = 0x03,
ATA_SET_MAX_FREEZE_LOCK = 0x04,
ATA_SET_MAX_PASSWD_DMA = 0x05,
ATA_SET_MAX_UNLOCK_DMA = 0x06,
/* feature values for DEVICE CONFIGURATION OVERLAY */
ATA_DCO_RESTORE = 0xC0,

2
include/linux/backing-dev.h
View file

@ -332,7 +332,7 @@ static inline bool inode_to_wb_is_valid(struct inode *inode)
* holding either @inode->i_lock, @inode->i_mapping->tree_lock, or the
* associated wb's list_lock.
*/
static inline struct bdi_writeback *inode_to_wb(struct inode *inode)
static inline struct bdi_writeback *inode_to_wb(const struct inode *inode)
{
#ifdef CONFIG_LOCKDEP
WARN_ON_ONCE(debug_locks &&

24
include/linux/bio.h
View file

@ -300,6 +300,29 @@ static inline void bio_get_last_bvec(struct bio *bio, struct bio_vec *bv)
bv->bv_len = iter.bi_bvec_done;
}
static inline unsigned bio_pages_all(struct bio *bio)
{
WARN_ON_ONCE(bio_flagged(bio, BIO_CLONED));
return bio->bi_vcnt;
}
static inline struct bio_vec *bio_first_bvec_all(struct bio *bio)
{
WARN_ON_ONCE(bio_flagged(bio, BIO_CLONED));
return bio->bi_io_vec;
}
static inline struct page *bio_first_page_all(struct bio *bio)
{
return bio_first_bvec_all(bio)->bv_page;
}
static inline struct bio_vec *bio_last_bvec_all(struct bio *bio)
{
WARN_ON_ONCE(bio_flagged(bio, BIO_CLONED));
return &bio->bi_io_vec[bio->bi_vcnt - 1];
}
enum bip_flags {
BIP_BLOCK_INTEGRITY = 1 << 0, /* block layer owns integrity data */
BIP_MAPPED_INTEGRITY = 1 << 1, /* ref tag has been remapped */
@ -477,7 +500,6 @@ static inline void bio_flush_dcache_pages(struct bio *bi)
#endif
extern void bio_copy_data(struct bio *dst, struct bio *src);
extern int bio_alloc_pages(struct bio *bio, gfp_t gfp);
extern void bio_free_pages(struct bio *bio);
extern struct bio *bio_copy_user_iov(struct request_queue *,

46
include/linux/bitfield.h
View file

@ -16,6 +16,7 @@
#define _LINUX_BITFIELD_H
#include <linux/build_bug.h>
#include <asm/byteorder.h>
/*
* Bitfield access macros
@ -103,4 +104,49 @@
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
extern void __compiletime_warning("value doesn't fit into mask")
__field_overflow(void);
extern void __compiletime_error("bad bitfield mask")
__bad_mask(void);
static __always_inline u64 field_multiplier(u64 field)
{
if ((field | (field - 1)) & ((field | (field - 1)) + 1))
__bad_mask();
return field & -field;
}
static __always_inline u64 field_mask(u64 field)
{
return field / field_multiplier(field);
}
#define ____MAKE_OP(type,base,to,from) \
static __always_inline __##type type##_encode_bits(base v, base field) \
{ \
if (__builtin_constant_p(v) && (v & ~field_multiplier(field))) \
__field_overflow(); \
return to((v & field_mask(field)) * field_multiplier(field)); \
} \
static __always_inline __##type type##_replace_bits(__##type old, \
base val, base field) \
{ \
return (old & ~to(field)) | type##_encode_bits(val, field); \
} \
static __always_inline void type##p_replace_bits(__##type *p, \
base val, base field) \
{ \
*p = (*p & ~to(field)) | type##_encode_bits(val, field); \
} \
static __always_inline base type##_get_bits(__##type v, base field) \
{ \
return (from(v) & field)/field_multiplier(field); \
}
#define __MAKE_OP(size) \
____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
____MAKE_OP(u##size,u##size,,)
__MAKE_OP(16)
__MAKE_OP(32)
__MAKE_OP(64)
#undef __MAKE_OP
#undef ____MAKE_OP
#endif

63
include/linux/bitmap.h
View file

@ -64,9 +64,14 @@
* bitmap_find_free_region(bitmap, bits, order) Find and allocate bit region
* bitmap_release_region(bitmap, pos, order) Free specified bit region
* bitmap_allocate_region(bitmap, pos, order) Allocate specified bit region
* bitmap_from_u32array(dst, nbits, buf, nwords) *dst = *buf (nwords 32b words)
* bitmap_to_u32array(buf, nwords, src, nbits) *buf = *dst (nwords 32b words)
* bitmap_from_arr32(dst, buf, nbits) Copy nbits from u32[] buf to dst
* bitmap_to_arr32(buf, src, nbits) Copy nbits from buf to u32[] dst
*
* Note, bitmap_zero() and bitmap_fill() operate over the region of
* unsigned longs, that is, bits behind bitmap till the unsigned long
* boundary will be zeroed or filled as well. Consider to use
* bitmap_clear() or bitmap_set() to make explicit zeroing or filling
* respectively.
*/
/**
@ -83,8 +88,12 @@
* test_and_change_bit(bit, addr) Change bit and return old value
* find_first_zero_bit(addr, nbits) Position first zero bit in *addr
* find_first_bit(addr, nbits) Position first set bit in *addr
* find_next_zero_bit(addr, nbits, bit) Position next zero bit in *addr >= bit
* find_next_zero_bit(addr, nbits, bit)
* Position next zero bit in *addr >= bit
* find_next_bit(addr, nbits, bit) Position next set bit in *addr >= bit
* find_next_and_bit(addr1, addr2, nbits, bit)
* Same as find_next_bit, but in
* (*addr1 & *addr2)
*
*/
@ -174,14 +183,7 @@ extern void bitmap_fold(unsigned long *dst, const unsigned long *orig,
extern int bitmap_find_free_region(unsigned long *bitmap, unsigned int bits, int order);
extern void bitmap_release_region(unsigned long *bitmap, unsigned int pos, int order);
extern int bitmap_allocate_region(unsigned long *bitmap, unsigned int pos, int order);
extern unsigned int bitmap_from_u32array(unsigned long *bitmap,
unsigned int nbits,
const u32 *buf,
unsigned int nwords);
extern unsigned int bitmap_to_u32array(u32 *buf,
unsigned int nwords,
const unsigned long *bitmap,
unsigned int nbits);
#ifdef __BIG_ENDIAN
extern void bitmap_copy_le(unsigned long *dst, const unsigned long *src, unsigned int nbits);
#else
@ -209,12 +211,12 @@ static inline void bitmap_zero(unsigned long *dst, unsigned int nbits)
static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
{
unsigned int nlongs = BITS_TO_LONGS(nbits);
if (!small_const_nbits(nbits)) {
unsigned int len = (nlongs - 1) * sizeof(unsigned long);
memset(dst, 0xff, len);
if (small_const_nbits(nbits))
*dst = ~0UL;
else {
unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0xff, len);
}
dst[nlongs - 1] = BITMAP_LAST_WORD_MASK(nbits);
}
static inline void bitmap_copy(unsigned long *dst, const unsigned long *src,
@ -228,6 +230,35 @@ static inline void bitmap_copy(unsigned long *dst, const unsigned long *src,
}
}
/*
* Copy bitmap and clear tail bits in last word.
*/
static inline void bitmap_copy_clear_tail(unsigned long *dst,
const unsigned long *src, unsigned int nbits)
{
bitmap_copy(dst, src, nbits);
if (nbits % BITS_PER_LONG)
dst[nbits / BITS_PER_LONG] &= BITMAP_LAST_WORD_MASK(nbits);
}
/*
* On 32-bit systems bitmaps are represented as u32 arrays internally, and
* therefore conversion is not needed when copying data from/to arrays of u32.
*/
#if BITS_PER_LONG == 64
extern void bitmap_from_arr32(unsigned long *bitmap, const u32 *buf,
unsigned int nbits);
extern void bitmap_to_arr32(u32 *buf, const unsigned long *bitmap,
unsigned int nbits);
#else
#define bitmap_from_arr32(bitmap, buf, nbits) \
bitmap_copy_clear_tail((unsigned long *) (bitmap), \
(const unsigned long *) (buf), (nbits))
#define bitmap_to_arr32(buf, bitmap, nbits) \
bitmap_copy_clear_tail((unsigned long *) (buf), \
(const unsigned long *) (bitmap), (nbits))
#endif
static inline int bitmap_and(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, unsigned int nbits)
{

8
include/linux/blk-cgroup.h
View file

@ -660,12 +660,14 @@ static inline void blkg_rwstat_reset(struct blkg_rwstat *rwstat)
static inline void blkg_rwstat_add_aux(struct blkg_rwstat *to,
struct blkg_rwstat *from)
{
struct blkg_rwstat v = blkg_rwstat_read(from);
u64 sum[BLKG_RWSTAT_NR];
int i;
for (i = 0; i < BLKG_RWSTAT_NR; i++)
atomic64_add(atomic64_read(&v.aux_cnt[i]) +
atomic64_read(&from->aux_cnt[i]),
sum[i] = percpu_counter_sum_positive(&from->cpu_cnt[i]);
for (i = 0; i < BLKG_RWSTAT_NR; i++)
atomic64_add(sum[i] + atomic64_read(&from->aux_cnt[i]),
&to->aux_cnt[i]);
}

3
include/linux/blk-mq.h
View file

@ -51,6 +51,7 @@ struct blk_mq_hw_ctx {
unsigned int queue_num;
atomic_t nr_active;
unsigned int nr_expired;
struct hlist_node cpuhp_dead;
struct kobject kobj;
@ -65,7 +66,7 @@ struct blk_mq_hw_ctx {
#endif
/* Must be the last member - see also blk_mq_hw_ctx_size(). */
struct srcu_struct queue_rq_srcu[0];
struct srcu_struct srcu[0];
};
struct blk_mq_tag_set {

46
include/linux/blk_types.h
View file

@ -39,6 +39,52 @@ typedef u8 __bitwise blk_status_t;
#define BLK_STS_AGAIN ((__force blk_status_t)12)
/*
* BLK_STS_DEV_RESOURCE is returned from the driver to the block layer if
* device related resources are unavailable, but the driver can guarantee
* that the queue will be rerun in the future once resources become
* available again. This is typically the case for device specific
* resources that are consumed for IO. If the driver fails allocating these
* resources, we know that inflight (or pending) IO will free these
* resource upon completion.
*
* This is different from BLK_STS_RESOURCE in that it explicitly references
* a device specific resource. For resources of wider scope, allocation
* failure can happen without having pending IO. This means that we can't
* rely on request completions freeing these resources, as IO may not be in
* flight. Examples of that are kernel memory allocations, DMA mappings, or
* any other system wide resources.
*/
#define BLK_STS_DEV_RESOURCE ((__force blk_status_t)13)
/**
* blk_path_error - returns true if error may be path related
* @error: status the request was completed with
*
* Description:
* This classifies block error status into non-retryable errors and ones
* that may be successful if retried on a failover path.
*
* Return:
* %false - retrying failover path will not help
* %true - may succeed if retried
*/
static inline bool blk_path_error(blk_status_t error)
{
switch (error) {
case BLK_STS_NOTSUPP:
case BLK_STS_NOSPC:
case BLK_STS_TARGET:
case BLK_STS_NEXUS:
case BLK_STS_MEDIUM:
case BLK_STS_PROTECTION:
return false;
}
/* Anything else could be a path failure, so should be retried */
return true;
}
struct blk_issue_stat {
u64 stat;
};

172
include/linux/blkdev.h
View file

@ -27,6 +27,8 @@
#include <linux/percpu-refcount.h>
#include <linux/scatterlist.h>
#include <linux/blkzoned.h>
#include <linux/seqlock.h>
#include <linux/u64_stats_sync.h>
struct module;
struct scsi_ioctl_command;
@ -121,6 +123,12 @@ typedef __u32 __bitwise req_flags_t;
/* Look at ->special_vec for the actual data payload instead of the
bio chain. */
#define RQF_SPECIAL_PAYLOAD ((__force req_flags_t)(1 << 18))
/* The per-zone write lock is held for this request */
#define RQF_ZONE_WRITE_LOCKED ((__force req_flags_t)(1 << 19))
/* timeout is expired */
#define RQF_MQ_TIMEOUT_EXPIRED ((__force req_flags_t)(1 << 20))
/* already slept for hybrid poll */
#define RQF_MQ_POLL_SLEPT ((__force req_flags_t)(1 << 21))
/* flags that prevent us from merging requests: */
#define RQF_NOMERGE_FLAGS \
@ -133,12 +141,6 @@ typedef __u32 __bitwise req_flags_t;
* especially blk_mq_rq_ctx_init() to take care of the added fields.
*/
struct request {
struct list_head queuelist;
union {
struct __call_single_data csd;
u64 fifo_time;
};
struct request_queue *q;
struct blk_mq_ctx *mq_ctx;
@ -148,8 +150,6 @@ struct request {
int internal_tag;
unsigned long atomic_flags;
/* the following two fields are internal, NEVER access directly */
unsigned int __data_len; /* total data len */
int tag;
@ -158,6 +158,8 @@ struct request {
struct bio *bio;
struct bio *biotail;
struct list_head queuelist;
/*
* The hash is used inside the scheduler, and killed once the
* request reaches the dispatch list. The ipi_list is only used
@ -205,19 +207,16 @@ struct request {
struct hd_struct *part;
unsigned long start_time;
struct blk_issue_stat issue_stat;
#ifdef CONFIG_BLK_CGROUP
struct request_list *rl; /* rl this rq is alloced from */
unsigned long long start_time_ns;
unsigned long long io_start_time_ns; /* when passed to hardware */
#endif
/* Number of scatter-gather DMA addr+len pairs after
* physical address coalescing is performed.
*/
unsigned short nr_phys_segments;
#if defined(CONFIG_BLK_DEV_INTEGRITY)
unsigned short nr_integrity_segments;
#endif
unsigned short write_hint;
unsigned short ioprio;
unsigned int timeout;
@ -226,11 +225,37 @@ struct request {
unsigned int extra_len; /* length of alignment and padding */
unsigned short write_hint;
/*
* On blk-mq, the lower bits of ->gstate (generation number and
* state) carry the MQ_RQ_* state value and the upper bits the
* generation number which is monotonically incremented and used to
* distinguish the reuse instances.
*
* ->gstate_seq allows updates to ->gstate and other fields
* (currently ->deadline) during request start to be read
* atomically from the timeout path, so that it can operate on a
* coherent set of information.
*/
seqcount_t gstate_seq;
u64 gstate;
/*
* ->aborted_gstate is used by the timeout to claim a specific
* recycle instance of this request. See blk_mq_timeout_work().
*/
struct u64_stats_sync aborted_gstate_sync;
u64 aborted_gstate;
/* access through blk_rq_set_deadline, blk_rq_deadline */
unsigned long __deadline;
unsigned long deadline;
struct list_head timeout_list;
union {
struct __call_single_data csd;
u64 fifo_time;
};
/*
* completion callback.
*/
@ -239,6 +264,12 @@ struct request {
/* for bidi */
struct request *next_rq;
#ifdef CONFIG_BLK_CGROUP
struct request_list *rl; /* rl this rq is alloced from */
unsigned long long start_time_ns;
unsigned long long io_start_time_ns; /* when passed to hardware */
#endif
};
static inline bool blk_op_is_scsi(unsigned int op)
@ -563,6 +594,22 @@ struct request_queue {
struct queue_limits limits;
/*
* Zoned block device information for request dispatch control.
* nr_zones is the total number of zones of the device. This is always
* 0 for regular block devices. seq_zones_bitmap is a bitmap of nr_zones
* bits which indicates if a zone is conventional (bit clear) or
* sequential (bit set). seq_zones_wlock is a bitmap of nr_zones
* bits which indicates if a zone is write locked, that is, if a write
* request targeting the zone was dispatched. All three fields are
* initialized by the low level device driver (e.g. scsi/sd.c).
* Stacking drivers (device mappers) may or may not initialize
* these fields.
*/
unsigned int nr_zones;
unsigned long *seq_zones_bitmap;
unsigned long *seq_zones_wlock;
/*
* sg stuff
*/
@ -807,6 +854,27 @@ static inline unsigned int blk_queue_zone_sectors(struct request_queue *q)
return blk_queue_is_zoned(q) ? q->limits.chunk_sectors : 0;
}
static inline unsigned int blk_queue_nr_zones(struct request_queue *q)
{
return q->nr_zones;
}
static inline unsigned int blk_queue_zone_no(struct request_queue *q,
sector_t sector)
{
if (!blk_queue_is_zoned(q))
return 0;
return sector >> ilog2(q->limits.chunk_sectors);
}
static inline bool blk_queue_zone_is_seq(struct request_queue *q,
sector_t sector)
{
if (!blk_queue_is_zoned(q) || !q->seq_zones_bitmap)
return false;
return test_bit(blk_queue_zone_no(q, sector), q->seq_zones_bitmap);
}
static inline bool rq_is_sync(struct request *rq)
{
return op_is_sync(rq->cmd_flags);
@ -1046,6 +1114,16 @@ static inline unsigned int blk_rq_cur_sectors(const struct request *rq)
return blk_rq_cur_bytes(rq) >> 9;
}
static inline unsigned int blk_rq_zone_no(struct request *rq)
{
return blk_queue_zone_no(rq->q, blk_rq_pos(rq));
}
static inline unsigned int blk_rq_zone_is_seq(struct request *rq)
{
return blk_queue_zone_is_seq(rq->q, blk_rq_pos(rq));
}
/*
* Some commands like WRITE SAME have a payload or data transfer size which
* is different from the size of the request. Any driver that supports such
@ -1595,7 +1673,15 @@ static inline unsigned int bdev_zone_sectors(struct block_device *bdev)
if (q)
return blk_queue_zone_sectors(q);
return 0;
}
static inline unsigned int bdev_nr_zones(struct block_device *bdev)
{
struct request_queue *q = bdev_get_queue(bdev);
if (q)
return blk_queue_nr_zones(q);
return 0;
}
@ -1731,8 +1817,6 @@ static inline bool req_gap_front_merge(struct request *req, struct bio *bio)
int kblockd_schedule_work(struct work_struct *work);
int kblockd_schedule_work_on(int cpu, struct work_struct *work);
int kblockd_schedule_delayed_work(struct delayed_work *dwork, unsigned long delay);
int kblockd_schedule_delayed_work_on(int cpu, struct delayed_work *dwork, unsigned long delay);
int kblockd_mod_delayed_work_on(int cpu, struct delayed_work *dwork, unsigned long delay);
#ifdef CONFIG_BLK_CGROUP
@ -1971,6 +2055,60 @@ extern int __blkdev_driver_ioctl(struct block_device *, fmode_t, unsigned int,
extern int bdev_read_page(struct block_device *, sector_t, struct page *);
extern int bdev_write_page(struct block_device *, sector_t, struct page *,
struct writeback_control *);
#ifdef CONFIG_BLK_DEV_ZONED
bool blk_req_needs_zone_write_lock(struct request *rq);
void __blk_req_zone_write_lock(struct request *rq);
void __blk_req_zone_write_unlock(struct request *rq);
static inline void blk_req_zone_write_lock(struct request *rq)
{
if (blk_req_needs_zone_write_lock(rq))
__blk_req_zone_write_lock(rq);
}
static inline void blk_req_zone_write_unlock(struct request *rq)
{
if (rq->rq_flags & RQF_ZONE_WRITE_LOCKED)
__blk_req_zone_write_unlock(rq);
}
static inline bool blk_req_zone_is_write_locked(struct request *rq)
{
return rq->q->seq_zones_wlock &&
test_bit(blk_rq_zone_no(rq), rq->q->seq_zones_wlock);
}
static inline bool blk_req_can_dispatch_to_zone(struct request *rq)
{
if (!blk_req_needs_zone_write_lock(rq))
return true;
return !blk_req_zone_is_write_locked(rq);
}
#else
static inline bool blk_req_needs_zone_write_lock(struct request *rq)
{
return false;
}
static inline void blk_req_zone_write_lock(struct request *rq)
{
}
static inline void blk_req_zone_write_unlock(struct request *rq)
{
}
static inline bool blk_req_zone_is_write_locked(struct request *rq)
{
return false;
}
static inline bool blk_req_can_dispatch_to_zone(struct request *rq)
{
return true;
}
#endif /* CONFIG_BLK_DEV_ZONED */
#else /* CONFIG_BLOCK */
struct block_device;

94
include/linux/bpf.h
View file

@ -17,6 +17,7 @@
#include <linux/numa.h>
#include <linux/wait.h>
struct bpf_verifier_env;
struct perf_event;
struct bpf_prog;
struct bpf_map;
@ -24,6 +25,7 @@ struct bpf_map;
/* map is generic key/value storage optionally accesible by eBPF programs */
struct bpf_map_ops {
/* funcs callable from userspace (via syscall) */
int (*map_alloc_check)(union bpf_attr *attr);
struct bpf_map *(*map_alloc)(union bpf_attr *attr);
void (*map_release)(struct bpf_map *map, struct file *map_file);
void (*map_free)(struct bpf_map *map);
@ -72,6 +74,33 @@ struct bpf_map {
char name[BPF_OBJ_NAME_LEN];
};
struct bpf_offloaded_map;
struct bpf_map_dev_ops {
int (*map_get_next_key)(struct bpf_offloaded_map *map,
void *key, void *next_key);
int (*map_lookup_elem)(struct bpf_offloaded_map *map,
void *key, void *value);
int (*map_update_elem)(struct bpf_offloaded_map *map,
void *key, void *value, u64 flags);
int (*map_delete_elem)(struct bpf_offloaded_map *map, void *key);
};
struct bpf_offloaded_map {
struct bpf_map map;
struct net_device *netdev;
const struct bpf_map_dev_ops *dev_ops;
void *dev_priv;
struct list_head offloads;
};
static inline struct bpf_offloaded_map *map_to_offmap(struct bpf_map *map)
{
return container_of(map, struct bpf_offloaded_map, map);
}
extern const struct bpf_map_ops bpf_map_offload_ops;
/* function argument constraints */
enum bpf_arg_type {
ARG_DONTCARE = 0, /* unused argument in helper function */
@ -193,14 +222,20 @@ struct bpf_verifier_ops {
struct bpf_prog *prog, u32 *target_size);
};
struct bpf_dev_offload {
struct bpf_prog_offload_ops {
int (*insn_hook)(struct bpf_verifier_env *env,
int insn_idx, int prev_insn_idx);
};
struct bpf_prog_offload {
struct bpf_prog *prog;
struct net_device *netdev;
void *dev_priv;
struct list_head offloads;
bool dev_state;
bool verifier_running;
wait_queue_head_t verifier_done;
const struct bpf_prog_offload_ops *dev_ops;
void *jited_image;
u32 jited_len;
};
struct bpf_prog_aux {
@ -209,6 +244,10 @@ struct bpf_prog_aux {
u32 max_ctx_offset;
u32 stack_depth;
u32 id;
u32 func_cnt;
bool offload_requested;
struct bpf_prog **func;
void *jit_data; /* JIT specific data. arch dependent */
struct latch_tree_node ksym_tnode;
struct list_head ksym_lnode;
const struct bpf_prog_ops *ops;
@ -220,7 +259,7 @@ struct bpf_prog_aux {
#ifdef CONFIG_SECURITY
void *security;
#endif
struct bpf_dev_offload *offload;
struct bpf_prog_offload *offload;
union {
struct work_struct work;
struct rcu_head rcu;
@ -295,6 +334,9 @@ int bpf_prog_array_copy_to_user(struct bpf_prog_array __rcu *progs,
void bpf_prog_array_delete_safe(struct bpf_prog_array __rcu *progs,
struct bpf_prog *old_prog);
int bpf_prog_array_copy_info(struct bpf_prog_array __rcu *array,
__u32 __user *prog_ids, u32 request_cnt,
__u32 __user *prog_cnt);
int bpf_prog_array_copy(struct bpf_prog_array __rcu *old_array,
struct bpf_prog *exclude_prog,
struct bpf_prog *include_prog,
@ -355,6 +397,9 @@ void bpf_prog_put(struct bpf_prog *prog);
int __bpf_prog_charge(struct user_struct *user, u32 pages);
void __bpf_prog_uncharge(struct user_struct *user, u32 pages);
void bpf_prog_free_id(struct bpf_prog *prog, bool do_idr_lock);
void bpf_map_free_id(struct bpf_map *map, bool do_idr_lock);
struct bpf_map *bpf_map_get_with_uref(u32 ufd);
struct bpf_map *__bpf_map_get(struct fd f);
struct bpf_map * __must_check bpf_map_inc(struct bpf_map *map, bool uref);
@ -363,6 +408,7 @@ void bpf_map_put(struct bpf_map *map);
int bpf_map_precharge_memlock(u32 pages);
void *bpf_map_area_alloc(size_t size, int numa_node);
void bpf_map_area_free(void *base);
void bpf_map_init_from_attr(struct bpf_map *map, union bpf_attr *attr);
extern int sysctl_unprivileged_bpf_disabled;
@ -409,6 +455,7 @@ static inline void bpf_long_memcpy(void *dst, const void *src, u32 size)
/* verify correctness of eBPF program */
int bpf_check(struct bpf_prog **fp, union bpf_attr *attr);
void bpf_patch_call_args(struct bpf_insn *insn, u32 stack_depth);
/* Map specifics */
struct net_device *__dev_map_lookup_elem(struct bpf_map *map, u32 key);
@ -536,14 +583,35 @@ bool bpf_prog_get_ok(struct bpf_prog *, enum bpf_prog_type *, bool);
int bpf_prog_offload_compile(struct bpf_prog *prog);
void bpf_prog_offload_destroy(struct bpf_prog *prog);
int bpf_prog_offload_info_fill(struct bpf_prog_info *info,
struct bpf_prog *prog);
int bpf_map_offload_info_fill(struct bpf_map_info *info, struct bpf_map *map);
int bpf_map_offload_lookup_elem(struct bpf_map *map, void *key, void *value);
int bpf_map_offload_update_elem(struct bpf_map *map,
void *key, void *value, u64 flags);
int bpf_map_offload_delete_elem(struct bpf_map *map, void *key);
int bpf_map_offload_get_next_key(struct bpf_map *map,
void *key, void *next_key);
bool bpf_offload_dev_match(struct bpf_prog *prog, struct bpf_map *map);
#if defined(CONFIG_NET) && defined(CONFIG_BPF_SYSCALL)
int bpf_prog_offload_init(struct bpf_prog *prog, union bpf_attr *attr);
static inline bool bpf_prog_is_dev_bound(struct bpf_prog_aux *aux)
{
return aux->offload;
return aux->offload_requested;
}
static inline bool bpf_map_is_dev_bound(struct bpf_map *map)
{
return unlikely(map->ops == &bpf_map_offload_ops);
}
struct bpf_map *bpf_map_offload_map_alloc(union bpf_attr *attr);
void bpf_map_offload_map_free(struct bpf_map *map);
#else
static inline int bpf_prog_offload_init(struct bpf_prog *prog,
union bpf_attr *attr)
@ -555,9 +623,23 @@ static inline bool bpf_prog_is_dev_bound(struct bpf_prog_aux *aux)
{
return false;
}
static inline bool bpf_map_is_dev_bound(struct bpf_map *map)
{
return false;
}
static inline struct bpf_map *bpf_map_offload_map_alloc(union bpf_attr *attr)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline void bpf_map_offload_map_free(struct bpf_map *map)
{
}
#endif /* CONFIG_NET && CONFIG_BPF_SYSCALL */
#if defined(CONFIG_STREAM_PARSER) && defined(CONFIG_BPF_SYSCALL)
#if defined(CONFIG_STREAM_PARSER) && defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_INET)
struct sock *__sock_map_lookup_elem(struct bpf_map *map, u32 key);
int sock_map_prog(struct bpf_map *map, struct bpf_prog *prog, u32 type);
#else

2
include/linux/bpf_types.h
View file

@ -42,7 +42,7 @@ BPF_MAP_TYPE(BPF_MAP_TYPE_ARRAY_OF_MAPS, array_of_maps_map_ops)
BPF_MAP_TYPE(BPF_MAP_TYPE_HASH_OF_MAPS, htab_of_maps_map_ops)
#ifdef CONFIG_NET
BPF_MAP_TYPE(BPF_MAP_TYPE_DEVMAP, dev_map_ops)
#ifdef CONFIG_STREAM_PARSER
#if defined(CONFIG_STREAM_PARSER) && defined(CONFIG_INET)
BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKMAP, sock_map_ops)
#endif
BPF_MAP_TYPE(BPF_MAP_TYPE_CPUMAP, cpu_map_ops)

63
include/linux/bpf_verifier.h
View file

@ -76,6 +76,14 @@ struct bpf_reg_state {
s64 smax_value; /* maximum possible (s64)value */
u64 umin_value; /* minimum possible (u64)value */
u64 umax_value; /* maximum possible (u64)value */
/* Inside the callee two registers can be both PTR_TO_STACK like
* R1=fp-8 and R2=fp-8, but one of them points to this function stack
* while another to the caller's stack. To differentiate them 'frameno'
* is used which is an index in bpf_verifier_state->frame[] array
* pointing to bpf_func_state.
* This field must be second to last, for states_equal() reasons.
*/
u32 frameno;
/* This field must be last, for states_equal() reasons. */
enum bpf_reg_liveness live;
};
@ -83,7 +91,8 @@ struct bpf_reg_state {
enum bpf_stack_slot_type {
STACK_INVALID, /* nothing was stored in this stack slot */
STACK_SPILL, /* register spilled into stack */
STACK_MISC /* BPF program wrote some data into this slot */
STACK_MISC, /* BPF program wrote some data into this slot */
STACK_ZERO, /* BPF program wrote constant zero */
};
#define BPF_REG_SIZE 8 /* size of eBPF register in bytes */
@ -96,13 +105,34 @@ struct bpf_stack_state {
/* state of the program:
* type of all registers and stack info
*/
struct bpf_verifier_state {
struct bpf_func_state {
struct bpf_reg_state regs[MAX_BPF_REG];
struct bpf_verifier_state *parent;
/* index of call instruction that called into this func */
int callsite;
/* stack frame number of this function state from pov of
* enclosing bpf_verifier_state.
* 0 = main function, 1 = first callee.
*/
u32 frameno;
/* subprog number == index within subprog_stack_depth
* zero == main subprog
*/
u32 subprogno;
/* should be second to last. See copy_func_state() */
int allocated_stack;
struct bpf_stack_state *stack;
};
#define MAX_CALL_FRAMES 8
struct bpf_verifier_state {
/* call stack tracking */
struct bpf_func_state *frame[MAX_CALL_FRAMES];
struct bpf_verifier_state *parent;
u32 curframe;
};
/* linked list of verifier states used to prune search */
struct bpf_verifier_state_list {
struct bpf_verifier_state state;
@ -113,6 +143,7 @@ struct bpf_insn_aux_data {
union {
enum bpf_reg_type ptr_type; /* pointer type for load/store insns */
struct bpf_map *map_ptr; /* pointer for call insn into lookup_elem */
s32 call_imm; /* saved imm field of call insn */
};
int ctx_field_size; /* the ctx field size for load insn, maybe 0 */
bool seen; /* this insn was processed by the verifier */
@ -135,11 +166,7 @@ static inline bool bpf_verifier_log_full(const struct bpf_verifer_log *log)
return log->len_used >= log->len_total - 1;
}
struct bpf_verifier_env;
struct bpf_ext_analyzer_ops {
int (*insn_hook)(struct bpf_verifier_env *env,
int insn_idx, int prev_insn_idx);
};
#define BPF_MAX_SUBPROGS 256
/* single container for all structs
* one verifier_env per bpf_check() call
@ -152,29 +179,31 @@ struct bpf_verifier_env {
bool strict_alignment; /* perform strict pointer alignment checks */
struct bpf_verifier_state *cur_state; /* current verifier state */
struct bpf_verifier_state_list **explored_states; /* search pruning optimization */
const struct bpf_ext_analyzer_ops *dev_ops; /* device analyzer ops */
struct bpf_map *used_maps[MAX_USED_MAPS]; /* array of map's used by eBPF program */
u32 used_map_cnt; /* number of used maps */
u32 id_gen; /* used to generate unique reg IDs */
bool allow_ptr_leaks;
bool seen_direct_write;
struct bpf_insn_aux_data *insn_aux_data; /* array of per-insn state */
struct bpf_verifer_log log;
u32 subprog_starts[BPF_MAX_SUBPROGS];
/* computes the stack depth of each bpf function */
u16 subprog_stack_depth[BPF_MAX_SUBPROGS + 1];
u32 subprog_cnt;
};
__printf(2, 3) void bpf_verifier_log_write(struct bpf_verifier_env *env,
const char *fmt, ...);
static inline struct bpf_reg_state *cur_regs(struct bpf_verifier_env *env)
{
return env->cur_state->regs;
struct bpf_verifier_state *cur = env->cur_state;
return cur->frame[cur->curframe]->regs;
}
#if defined(CONFIG_NET) && defined(CONFIG_BPF_SYSCALL)
int bpf_prog_offload_verifier_prep(struct bpf_verifier_env *env);
#else
static inline int bpf_prog_offload_verifier_prep(struct bpf_verifier_env *env)
{
return -EOPNOTSUPP;
}
#endif
int bpf_prog_offload_verify_insn(struct bpf_verifier_env *env,
int insn_idx, int prev_insn_idx);
#endif /* _LINUX_BPF_VERIFIER_H */

1
include/linux/brcmphy.h
View file

@ -14,6 +14,7 @@
#define PHY_ID_BCM5241 0x0143bc30
#define PHY_ID_BCMAC131 0x0143bc70
#define PHY_ID_BCM5481 0x0143bca0
#define PHY_ID_BCM5395 0x0143bcf0
#define PHY_ID_BCM54810 0x03625d00
#define PHY_ID_BCM5482 0x0143bcb0
#define PHY_ID_BCM5411 0x00206070

6
include/linux/buffer_head.h
View file

@ -81,11 +81,14 @@ struct buffer_head {
/*
* macro tricks to expand the set_buffer_foo(), clear_buffer_foo()
* and buffer_foo() functions.
* To avoid reset buffer flags that are already set, because that causes
* a costly cache line transition, check the flag first.
*/
#define BUFFER_FNS(bit, name) \
static __always_inline void set_buffer_##name(struct buffer_head *bh) \
{ \
set_bit(BH_##bit, &(bh)->b_state); \
if (!test_bit(BH_##bit, &(bh)->b_state)) \
set_bit(BH_##bit, &(bh)->b_state); \
} \
static __always_inline void clear_buffer_##name(struct buffer_head *bh) \
{ \
@ -151,7 +154,6 @@ void buffer_check_dirty_writeback(struct page *page,
void mark_buffer_dirty(struct buffer_head *bh);
void mark_buffer_write_io_error(struct buffer_head *bh);
void init_buffer(struct buffer_head *, bh_end_io_t *, void *);
void touch_buffer(struct buffer_head *bh);
void set_bh_page(struct buffer_head *bh,
struct page *page, unsigned long offset);

2
include/linux/build_bug.h
View file

@ -8,7 +8,6 @@
#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
#define BUILD_BUG_ON_ZERO(e) (0)
#define BUILD_BUG_ON_NULL(e) ((void *)0)
#define BUILD_BUG_ON_INVALID(e) (0)
#define BUILD_BUG_ON_MSG(cond, msg) (0)
#define BUILD_BUG_ON(condition) (0)
@ -28,7 +27,6 @@
* aren't permitted).
*/
#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); }))
/*
* BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the

9
include/linux/bvec.h
View file

@ -125,4 +125,13 @@ static inline bool bvec_iter_rewind(const struct bio_vec *bv,
((bvl = bvec_iter_bvec((bio_vec), (iter))), 1); \
bvec_iter_advance((bio_vec), &(iter), (bvl).bv_len))
/* for iterating one bio from start to end */
#define BVEC_ITER_ALL_INIT (struct bvec_iter) \
{ \
.bi_sector = 0, \
.bi_size = UINT_MAX, \
.bi_idx = 0, \
.bi_bvec_done = 0, \
}
#endif /* __LINUX_BVEC_ITER_H */

7
include/linux/can/dev.h
View file

@ -46,6 +46,7 @@ struct can_priv {
unsigned int bitrate_const_cnt;
const u32 *data_bitrate_const;
unsigned int data_bitrate_const_cnt;
u32 bitrate_max;
struct can_clock clock;
enum can_state state;
@ -166,6 +167,12 @@ void can_put_echo_skb(struct sk_buff *skb, struct net_device *dev,
unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx);
void can_free_echo_skb(struct net_device *dev, unsigned int idx);
#ifdef CONFIG_OF
void of_can_transceiver(struct net_device *dev);
#else
static inline void of_can_transceiver(struct net_device *dev) { }
#endif
struct sk_buff *alloc_can_skb(struct net_device *dev, struct can_frame **cf);
struct sk_buff *alloc_canfd_skb(struct net_device *dev,
struct canfd_frame **cfd);

2
include/linux/cgroup-defs.h
View file

@ -561,7 +561,7 @@ struct cftype {
/*
* Control Group subsystem type.
* See Documentation/cgroups/cgroups.txt for details
* See Documentation/cgroup-v1/cgroups.txt for details
*/
struct cgroup_subsys {
struct cgroup_subsys_state *(*css_alloc)(struct cgroup_subsys_state *parent_css);

43
include/linux/clk-provider.h
View file

@ -20,6 +20,8 @@
* flags used across common struct clk. these flags should only affect the
* top-level framework. custom flags for dealing with hardware specifics
* belong in struct clk_foo
*
* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
*/
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
@ -412,7 +414,7 @@ extern const struct clk_ops clk_divider_ro_ops;
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
unsigned int val, const struct clk_div_table *table,
unsigned long flags);
unsigned long flags, unsigned long width);
long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
unsigned long rate, unsigned long *prate,
const struct clk_div_table *table,
@ -744,6 +746,7 @@ unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long __clk_get_flags(struct clk *clk);
unsigned long clk_hw_get_flags(const struct clk_hw *hw);
bool clk_hw_is_prepared(const struct clk_hw *hw);
bool clk_hw_rate_is_protected(const struct clk_hw *hw);
bool clk_hw_is_enabled(const struct clk_hw *hw);
bool __clk_is_enabled(struct clk *clk);
struct clk *__clk_lookup(const char *name);
@ -806,6 +809,44 @@ extern struct of_device_id __clk_of_table;
} \
OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
.name = _name, \
.parent_names = (const char *[]) { _parent }, \
.num_parents = 1, \
.ops = _ops, \
})
#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
.name = _name, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.ops = _ops, \
})
#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
.name = _name, \
.parent_names = NULL, \
.num_parents = 0, \
.ops = _ops, \
})
#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
_div, _mult, _flags) \
struct clk_fixed_factor _struct = { \
.div = _div, \
.mult = _mult, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&clk_fixed_factor_ops, \
_flags), \
}
#ifdef CONFIG_OF
int of_clk_add_provider(struct device_node *np,
struct clk *(*clk_src_get)(struct of_phandle_args *args,

62
include/linux/clk.h
View file

@ -331,6 +331,38 @@ struct clk *devm_clk_get(struct device *dev, const char *id);
*/
struct clk *devm_get_clk_from_child(struct device *dev,
struct device_node *np, const char *con_id);
/**
* clk_rate_exclusive_get - get exclusivity over the rate control of a
* producer
* @clk: clock source
*
* This function allows drivers to get exclusive control over the rate of a
* provider. It prevents any other consumer to execute, even indirectly,
* opereation which could alter the rate of the provider or cause glitches
*
* If exlusivity is claimed more than once on clock, even by the same driver,
* the rate effectively gets locked as exclusivity can't be preempted.
*
* Must not be called from within atomic context.
*
* Returns success (0) or negative errno.
*/
int clk_rate_exclusive_get(struct clk *clk);
/**
* clk_rate_exclusive_put - release exclusivity over the rate control of a
* producer
* @clk: clock source
*
* This function allows drivers to release the exclusivity it previously got
* from clk_rate_exclusive_get()
*
* The caller must balance the number of clk_rate_exclusive_get() and
* clk_rate_exclusive_put() calls.
*
* Must not be called from within atomic context.
*/
void clk_rate_exclusive_put(struct clk *clk);
/**
* clk_enable - inform the system when the clock source should be running.
@ -472,6 +504,23 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
*/
int clk_set_rate(struct clk *clk, unsigned long rate);
/**
* clk_set_rate_exclusive- set the clock rate and claim exclusivity over
* clock source
* @clk: clock source
* @rate: desired clock rate in Hz
*
* This helper function allows drivers to atomically set the rate of a producer
* and claim exclusivity over the rate control of the producer.
*
* It is essentially a combination of clk_set_rate() and
* clk_rate_exclusite_get(). Caller must balance this call with a call to
* clk_rate_exclusive_put()
*
* Returns success (0) or negative errno.
*/
int clk_set_rate_exclusive(struct clk *clk, unsigned long rate);
/**
* clk_has_parent - check if a clock is a possible parent for another
* @clk: clock source
@ -583,6 +632,14 @@ static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {}
static inline void devm_clk_put(struct device *dev, struct clk *clk) {}
static inline int clk_rate_exclusive_get(struct clk *clk)
{
return 0;
}
static inline void clk_rate_exclusive_put(struct clk *clk) {}
static inline int clk_enable(struct clk *clk)
{
return 0;
@ -609,6 +666,11 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
static inline int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
{
return 0;
}
static inline long clk_round_rate(struct clk *clk, unsigned long rate)
{
return 0;

7
include/linux/clkdev.h
View file

@ -12,7 +12,7 @@
#ifndef __CLKDEV_H
#define __CLKDEV_H
#include <asm/clkdev.h>
#include <linux/slab.h>
struct clk;
struct clk_hw;
@ -52,9 +52,4 @@ int clk_add_alias(const char *, const char *, const char *, struct device *);
int clk_register_clkdev(struct clk *, const char *, const char *);
int clk_hw_register_clkdev(struct clk_hw *, const char *, const char *);
#ifdef CONFIG_COMMON_CLK
int __clk_get(struct clk *clk);
void __clk_put(struct clk *clk);
#endif
#endif

Some files were not shown because too many files have changed in this diff Show more