ARM: arm-soc: Cleanups on various subarchitectures
Cleanup patches for various ARM platforms and some of their associated drivers. There's also a branch in here that enables Freescale i.MX to be part of the multiplatform support -- the first "big" SoC that is moved over (more multiplatform work comes in a separate branch later during the merge window). -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQx2p9AAoJEIwa5zzehBx3aPUQAIjV3VDf/ACkA4KUQu0BFg5U 57OIkl6RCZvfKhYgq5+6OJ2AK6VkGh9PqTmXkDS7Nj3QMS/uWcb3U419aPJsd3Z/ vNGpTl+J/YcAcFrKMqTyNv98TAiAOJlpm70CqmRbkhpMfoJb7//1JKqGTJPBO+tj 8ZEwNGC0WbRNOSQTY/TTAhbZE1sqXwKy9mDLGmcwqKBY8H1TFHyPB6yWYFSxMHxS JAegbYhYO9FawOOLoi9ovT+2vUR9vDu0xxV4zUK9f5DqKcCb/wYuN0QkusjnEutm RfIt7iXHHzi35YPxtlrGgSz9EIYXKAafSzkgf3Ydpjci5DH/vbVexm/CT+V+SwOT SvucYJMALI/aOEFJWN/50L6B9zipSrWb51tK7WFXz/sUCrMQrXH3Mu99mjHZXSoL 1cylsvs3DFQC7vHFLSjRpX6eJdfE+Hb0LZ878eXSbDVCOnU8odAQrofugqfmeVDk eN0+BWmchJgvljOiKVUQMC3PCquCaAAO1lm/HU7bWPlVigTuHSW0uisDyCYAtlt1 dGxnbbhoFJvSH7CMOoMO7hIFnoNJEe6+uVUuwA/+iJouMXMJLoY6Da4L72h1Mp81 o4Hr6Kxly/SMtURZ/6pCycx5ahb5TaahstYAoe7Qp1dMj5U2m6fUVfKkG7tUx1CW MIuvN3qJeW2qKWKmZRVM =zfPd -----END PGP SIGNATURE----- Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups on various subarchitectures from Olof Johansson: "Cleanup patches for various ARM platforms and some of their associated drivers. There's also a branch in here that enables Freescale i.MX to be part of the multiplatform support -- the first "big" SoC that is moved over (more multiplatform work comes in a separate branch later during the merge window)." Conflicts fixed as per Olof, including a silent semantic one in arch/arm/mach-omap2/board-generic.c (omap_prcm_restart() was renamed to omap3xxx_restart(), and a new user of the old name was added). * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (189 commits) ARM: omap: fix typo on timer cleanup ARM: EXYNOS: Remove unused regs-mem.h file ARM: EXYNOS: Remove unused non-dt support for dwmci controller ARM: Kirkwood: Use hw_pci.ops instead of hw_pci.scan ARM: OMAP3: cm-t3517: use GPTIMER for system clock ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER ARM: SAMSUNG: use devm_ functions for ADC driver ARM: EXYNOS: no duplicate mask/unmask in eint0_15 ARM: S3C24XX: SPI clock channel setup is fixed for S3C2443 ARM: EXYNOS: Remove i2c0 resource information and setting of device names ARM: Kirkwood: checkpatch cleanups ARM: Kirkwood: Fix sparse warnings. ARM: Kirkwood: Remove unused includes ARM: kirkwood: cleanup lsxl board includes ARM: integrator: use BUG_ON where possible ARM: integrator: push down SC dependencies ARM: integrator: delete static UART1 mapping ARM: integrator: delete SC mapping on the CP ARM: integrator: remove static CP syscon mapping ARM: integrator: remove static AP syscon mapping ...
This commit is contained in:
Linus Torvalds
commit
d01e4afdbb
496 changed files with 4717 additions and 4090 deletions
177
include/linux/dma/ipu-dma.h
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177
include/linux/dma/ipu-dma.h
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@ -0,0 +1,177 @@
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/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_DMA_IPU_DMA_H
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#define __LINUX_DMA_IPU_DMA_H
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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/* IPU DMA Controller channel definitions. */
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enum ipu_channel {
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IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
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IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
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IDMAC_ADC_0 = 1,
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IDMAC_IC_2 = 2,
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IDMAC_ADC_1 = 2,
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IDMAC_IC_3 = 3,
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IDMAC_IC_4 = 4,
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IDMAC_IC_5 = 5,
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IDMAC_IC_6 = 6,
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IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
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IDMAC_IC_8 = 8,
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IDMAC_IC_9 = 9,
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IDMAC_IC_10 = 10,
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IDMAC_IC_11 = 11,
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IDMAC_IC_12 = 12,
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IDMAC_IC_13 = 13,
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IDMAC_SDC_0 = 14, /* Background synchronous display data */
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IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
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IDMAC_SDC_2 = 16,
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IDMAC_SDC_3 = 17,
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IDMAC_ADC_2 = 18,
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IDMAC_ADC_3 = 19,
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IDMAC_ADC_4 = 20,
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IDMAC_ADC_5 = 21,
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IDMAC_ADC_6 = 22,
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IDMAC_ADC_7 = 23,
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IDMAC_PF_0 = 24,
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IDMAC_PF_1 = 25,
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IDMAC_PF_2 = 26,
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IDMAC_PF_3 = 27,
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IDMAC_PF_4 = 28,
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IDMAC_PF_5 = 29,
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IDMAC_PF_6 = 30,
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IDMAC_PF_7 = 31,
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};
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/* Order significant! */
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enum ipu_channel_status {
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IPU_CHANNEL_FREE,
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IPU_CHANNEL_INITIALIZED,
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IPU_CHANNEL_READY,
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IPU_CHANNEL_ENABLED,
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};
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#define IPU_CHANNELS_NUM 32
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enum pixel_fmt {
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/* 1 byte */
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IPU_PIX_FMT_GENERIC,
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IPU_PIX_FMT_RGB332,
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IPU_PIX_FMT_YUV420P,
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IPU_PIX_FMT_YUV422P,
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IPU_PIX_FMT_YUV420P2,
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IPU_PIX_FMT_YVU422P,
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/* 2 bytes */
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IPU_PIX_FMT_RGB565,
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IPU_PIX_FMT_RGB666,
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IPU_PIX_FMT_BGR666,
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IPU_PIX_FMT_YUYV,
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IPU_PIX_FMT_UYVY,
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/* 3 bytes */
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IPU_PIX_FMT_RGB24,
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IPU_PIX_FMT_BGR24,
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/* 4 bytes */
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IPU_PIX_FMT_GENERIC_32,
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IPU_PIX_FMT_RGB32,
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IPU_PIX_FMT_BGR32,
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IPU_PIX_FMT_ABGR32,
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IPU_PIX_FMT_BGRA32,
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IPU_PIX_FMT_RGBA32,
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};
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enum ipu_color_space {
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IPU_COLORSPACE_RGB,
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IPU_COLORSPACE_YCBCR,
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IPU_COLORSPACE_YUV
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};
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/*
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* Enumeration of IPU rotation modes
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*/
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enum ipu_rotate_mode {
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/* Note the enum values correspond to BAM value */
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IPU_ROTATE_NONE = 0,
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IPU_ROTATE_VERT_FLIP = 1,
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IPU_ROTATE_HORIZ_FLIP = 2,
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IPU_ROTATE_180 = 3,
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IPU_ROTATE_90_RIGHT = 4,
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IPU_ROTATE_90_RIGHT_VFLIP = 5,
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IPU_ROTATE_90_RIGHT_HFLIP = 6,
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IPU_ROTATE_90_LEFT = 7,
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};
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/*
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* Enumeration of DI ports for ADC.
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*/
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enum display_port {
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DISP0,
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DISP1,
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DISP2,
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DISP3
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};
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struct idmac_video_param {
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unsigned short in_width;
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unsigned short in_height;
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uint32_t in_pixel_fmt;
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unsigned short out_width;
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unsigned short out_height;
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uint32_t out_pixel_fmt;
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unsigned short out_stride;
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bool graphics_combine_en;
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bool global_alpha_en;
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bool key_color_en;
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enum display_port disp;
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unsigned short out_left;
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unsigned short out_top;
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};
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/*
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* Union of initialization parameters for a logical channel. So far only video
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* parameters are used.
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*/
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union ipu_channel_param {
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struct idmac_video_param video;
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};
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struct idmac_tx_desc {
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struct dma_async_tx_descriptor txd;
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struct scatterlist *sg; /* scatterlist for this */
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unsigned int sg_len; /* tx-descriptor. */
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struct list_head list;
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};
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struct idmac_channel {
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struct dma_chan dma_chan;
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dma_cookie_t completed; /* last completed cookie */
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union ipu_channel_param params;
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enum ipu_channel link; /* input channel, linked to the output */
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enum ipu_channel_status status;
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void *client; /* Only one client per channel */
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unsigned int n_tx_desc;
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struct idmac_tx_desc *desc; /* allocated tx-descriptors */
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struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */
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struct list_head free_list; /* free tx-descriptors */
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struct list_head queue; /* queued tx-descriptors */
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spinlock_t lock; /* protects sg[0,1], queue */
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struct mutex chan_mutex; /* protects status, cookie, free_list */
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bool sec_chan_en;
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int active_buffer;
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unsigned int eof_irq;
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char eof_name[16]; /* EOF IRQ name for request_irq() */
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};
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#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
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#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
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#endif /* __LINUX_DMA_IPU_DMA_H */
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@ -17,5 +17,7 @@ struct imx_ssi_platform_data {
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void (*ac97_warm_reset)(struct snd_ac97 *ac97);
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};
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extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
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#endif /* __MACH_SSI_H */
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@ -61,7 +61,9 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
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static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
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{
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return strstr(dev_name(chan->device->dev), "sdma") ||
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!strcmp(dev_name(chan->device->dev), "imx-dma");
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!strcmp(dev_name(chan->device->dev), "imx1-dma") ||
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!strcmp(dev_name(chan->device->dev), "imx21-dma") ||
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!strcmp(dev_name(chan->device->dev), "imx27-dma");
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}
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#endif
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31
include/linux/platform_data/dmtimer-omap.h
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31
include/linux/platform_data/dmtimer-omap.h
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/*
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* DMTIMER platform data for TI OMAP platforms
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*
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* Copyright (C) 2012 Texas Instruments
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* Author: Jon Hunter <jon-hunter@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__
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#define __PLATFORM_DATA_DMTIMER_OMAP_H__
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struct dmtimer_platform_data {
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/* set_timer_src - Only used for OMAP1 devices */
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int (*set_timer_src)(struct platform_device *pdev, int source);
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u32 timer_capability;
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u32 timer_errata;
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int (*get_context_loss_count)(struct device *);
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};
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#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */
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38
include/linux/platform_data/omap-wd-timer.h
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38
include/linux/platform_data/omap-wd-timer.h
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/*
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* OMAP2+ WDTIMER-specific function prototypes
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __LINUX_PLATFORM_DATA_OMAP_WD_TIMER_H
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#define __LINUX_PLATFORM_DATA_OMAP_WD_TIMER_H
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#include <linux/types.h>
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/*
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* Standardized OMAP reset source bits
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*
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* This is a subset of the ones listed in arch/arm/mach-omap2/prm.h
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* and are the only ones needed in the watchdog driver.
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*/
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#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
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/**
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* struct omap_wd_timer_platform_data - WDTIMER integration to the host SoC
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* @read_reset_sources - fn ptr for the SoC to indicate the last reset cause
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*
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* The function pointed to by @read_reset_sources must return its data
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* in a standard format - search for RST_SRC_ID_SHIFT in
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* arch/arm/mach-omap2
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*/
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struct omap_wd_timer_platform_data {
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u32 (*read_reset_sources)(void);
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};
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#endif
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19
include/linux/tegra-ahb.h
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19
include/linux/tegra-ahb.h
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __LINUX_AHB_H__
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#define __LINUX_AHB_H__
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extern int tegra_ahb_enable_smmu(struct device_node *ahb);
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#endif /* __LINUX_AHB_H__ */
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