kybaaz/linux-xiaomi-chiron
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

drm/i915/display: fix level 0 adjustement on display ver >= 12

Browse source 
We should no longer increment level 0 by 1usec when we have 16Gb DIMMs.
Instead spec says to add 3usec (as opposed to 2) to each valid level
when punit replies 0 to level 0.

So set wm_lv_0_adjust_needed to false for DISPLAY_VER() >= 12 and set
the proper adjustment value when handling WaWmMemoryReadLatency.

Bspec: 49326, 4381
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210622212210.3746133-1-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi 2021-06-22 14:22:09 -07:00
parent c4449742a7
commit cbeeb00f14
2 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

3
drivers/gpu/drm/i915/intel_dram.c
View file

@ -484,8 +484,7 @@ static int gen11_get_dram_info(struct drm_i915_private *i915)
static int gen12_get_dram_info(struct drm_i915_private *i915)
{
/* Always needed for GEN12+ */
i915->dram_info.wm_lv_0_adjust_needed = true;
i915->dram_info.wm_lv_0_adjust_needed = false;
return icl_pcode_read_mem_global_info(i915);
}

13
drivers/gpu/drm/i915/intel_pm.c
View file

@ -2913,18 +2913,20 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
}
/*
* WaWmMemoryReadLatency:skl+,glk
* WaWmMemoryReadLatency
*
* punit doesn't take into account the read latency so we need
* to add 2us to the various latency levels we retrieve from the
* punit when level 0 response data us 0us.
* to add proper adjustement to each valid level we retrieve
* from the punit when level 0 response data is 0us.
*/
if (wm[0] == 0) {
wm[0] += 2;
u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
wm[0] += adjust;
for (level = 1; level <= max_level; level++) {
if (wm[level] == 0)
break;
wm[level] += 2;
wm[level] += adjust;
}
}
@ -2936,7 +2938,6 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
*/
if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);