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various tests

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This commit is contained in:
AngeloGioacchino Del Regno 2021-08-10 20:48:37 +02:00 • committed by Jami Kettunen
parent 5679eca4df
commit c215a02270
6 changed files with 30 additions and 10 deletions
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7
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
View file

@ -780,12 +780,13 @@
#clock-cells = <0>; #clock-cells = <0>;
interrupt-parent = <&tlmm>; interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
interrupt-names = "intr1"; <53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <1>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
slim-ifc-dev = <&tasha_ifd>; slim-ifc-dev = <&tasha_ifd>;

4
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file

@ -2172,8 +2172,8 @@
}; };
adreno_smmu: iommu@5040000 { adreno_smmu: iommu@5040000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2", compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
"qcom,adreno-smmu"; // "qcom,adreno-smmu";
reg = <0x05040000 0x10000>; reg = <0x05040000 0x10000>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>, <&gcc GCC_BIMC_GFX_CLK>,

6
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View file

@ -563,8 +563,12 @@ static void a5xx_ucode_check_version(struct a5xx_gpu *a5xx_gpu,
* has been patched. The actual version is in dword [3] but we only care * has been patched. The actual version is in dword [3] but we only care
* about the patchlevel which is the lowest nibble of dword [3] * about the patchlevel which is the lowest nibble of dword [3]
*/ */
if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) {
pr_err("adreno HAS WHEREAMI!\n");
a5xx_gpu->has_whereami = true; a5xx_gpu->has_whereami = true;
} else {
pr_err("adreno has no whereami support\n");
}
msm_gem_put_vaddr(obj); msm_gem_put_vaddr(obj);
} }

2
drivers/gpu/drm/panel/panel-novatek-nt35950.c
View file

@ -551,7 +551,7 @@ static int nt35950_remove(struct mipi_dsi_device *dsi)
static const struct drm_display_mode sharp_ls055d1sx04_modes = { static const struct drm_display_mode sharp_ls055d1sx04_modes = {
/* TODO: Declare 2160x3840 mode when FBC/DSC will be working. */ /* TODO: Declare 2160x3840 mode when FBC/DSC will be working. */
.name = "1080x1920", .name = "1080x1920",
.clock = (1080 + 400 + 40 + 300) * (1920 + 12 + 2 + 10) * 60 / 1000, .clock = (1080 + 400 + 40 + 300) * (1920 + 12 + 2 + 10) * 60 / 400,
.hdisplay = 1080, .hdisplay = 1080,
.hsync_start = 1080 + 400, .hsync_start = 1080 + 400,
.hsync_end = 1080 + 400 + 40, .hsync_end = 1080 + 400 + 40,

15
sound/soc/codecs/wcd9335.c
View file

@ -493,7 +493,7 @@ static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
{WCD9335_RCO_CTRL_2, 0x0F, 0x08}, {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
{WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
{WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
{WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, {WCD9335_HPH_OCP_CTL, 0xFF, 0x7A}, /*downstream is ff 7a */
{WCD9335_HPH_L_TEST, 0x01, 0x01}, {WCD9335_HPH_L_TEST, 0x01, 0x01},
{WCD9335_HPH_R_TEST, 0x01, 0x01}, {WCD9335_HPH_R_TEST, 0x01, 0x01},
{WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
@ -506,6 +506,13 @@ static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
{WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
{WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
{WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
{WCD9335_DIFF_LO_CORE_OUT_PROG, 0xFC, 0xA0},
{WCD9335_SE_LO_COM1, 0xFF, 0xC0},
{WCD9335_CDC_RX3_RX_PATH_SEC0, 0xFC, 0xF4},
{WCD9335_CDC_RX4_RX_PATH_SEC0, 0xFC, 0xF4},
{WCD9335_CDC_RX5_RX_PATH_SEC0, 0xFC, 0xF8},
{WCD9335_CDC_RX6_RX_PATH_SEC0, 0xFC, 0xF8},
}; };
/* Cutoff frequency for high pass filter */ /* Cutoff frequency for high pass filter */
@ -3752,11 +3759,12 @@ static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode; int hph_mode = wcd->hph_mode;
pr_err("%s\n", __func__);
switch (event) { switch (event) {
case SND_SOC_DAPM_PRE_PMU: case SND_SOC_DAPM_PRE_PMU:
break; break;
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
pr_err("%s post pmu\n", __func__);
/* /*
* 7ms sleep is required after PA is enabled as per * 7ms sleep is required after PA is enabled as per
* HW requirement * HW requirement
@ -3780,6 +3788,7 @@ static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
break; break;
case SND_SOC_DAPM_PRE_PMD: case SND_SOC_DAPM_PRE_PMD:
pr_err("%s pre pmd\n", __func__);
wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
@ -3901,7 +3910,7 @@ static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
int hph_mode = wcd->hph_mode; int hph_mode = wcd->hph_mode;
pr_err("%s\n", __func__);
switch (event) { switch (event) {
case SND_SOC_DAPM_PRE_PMU: case SND_SOC_DAPM_PRE_PMU:
break; break;

6
sound/soc/codecs/wcd9335.h
View file

@ -368,8 +368,10 @@
#define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2) #define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2)
#define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea) #define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea)
#define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb) #define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb)
#define WCD9335_DIFF_LO_CORE_OUT_PROG WCD9335_REG(0x06, 0x0ef)
#define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1) #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1)
#define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2) #define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2)
#define WCD9335_SE_LO_COM1 WCD9335_REG(0x06, 0x0f6)
#define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8) #define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8)
#define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9) #define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9)
#define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa) #define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa)
@ -495,6 +497,7 @@
#define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082) #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082)
#define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083) #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083)
#define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084) #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084)
#define WCD9335_CDC_RX3_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x085)
#define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091) #define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091)
#define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092) #define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092)
#define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094) #define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094)
@ -502,6 +505,7 @@
#define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096) #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096)
#define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097) #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097)
#define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098) #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098)
#define WCD9335_CDC_RX4_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x099)
#define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5) #define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5)
#define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6) #define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6)
#define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8) #define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8)
@ -509,6 +513,7 @@
#define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa) #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa)
#define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab) #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab)
#define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac) #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac)
#define WCD9335_CDC_RX5_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x0ad)
#define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9) #define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9)
#define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba) #define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba)
#define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc) #define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc)
@ -516,6 +521,7 @@
#define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be) #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be)
#define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf) #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf)
#define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0) #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0)
#define WCD9335_CDC_RX6_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x0c1)
#define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd) #define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd)
#define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce) #define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce)
#define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf) #define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf)