IOMMU Updates for Linux v5.1
Including: - A big cleanup and optimization patch-set for the Tegra GART driver - Documentation updates and fixes for the IOMMU-API - Support for page request in Intel VT-d scalable mode - Intel VT-d dma_[un]map_resource() support - Updates to the ATS enabling code for PCI (acked by Bjorn) and Intel VT-d to align with the latest version of the ATS spec - Relaxed IRQ source checking in the Intel VT-d driver for some aliased devices, needed for future devices which send IRQ messages from more than on request-ID - IRQ remapping driver for Hyper-V - Patches to make generic IOVA and IO-Page-Table code usable outside of the IOMMU code - Various other small fixes and cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAlyCNlIACgkQK/BELZcB GuNDiRAAscgYj0BdqpZVUNHl4PySR12QJpS1myl/OC4HEbdB/EOh+bYT4Q1vptCU GNK6Gt9SVfcbtWrLiGfcP9ODXmbqZ6AIOIbHKv9cvw1mnyYAtVvT/kck7B/W5jEr /aP/5RTO7XcqscWO44zBkrtLFupegtpQFB0jXYTJYTrwQoNKRqCUqfetZGzMkXjL x/h7kFTTIRcVP8RFcOeAMwC6EieaI8z8HN976Gu7xSV8g0VJqoNsBN8jbUuBh5AN oPyd9nl1KBcIQEC1HsbN8I5wIhTh1sJ2UDqFHAgtlnO59zWHORuFUUt6SXbC9UqJ okJTzFp9Dh2BqmFPXxBTxAf3j+eJP2XPpDI9Ask6SytEPhgw39fdlOOn2MWfSFoW TaBJ4ww/r98GzVxCP7Up98xFZuHGDICL3/M7Mk3mRac/lgbNRbtfcBa5NV4fyQhY 184t656Zm/9gdWgGAvYQtApr6/iI+wRMLkIwuw63wqH09yfbDcpTOo6DEQE3B5KR 4H1qSIiVGVVZlWQateR6N32ZmY4dWzpnL2b8CfsdBytzHHFb/c3dPnZB8fxx9mwF onyvjg9nkIiv7mdcN4Ox2WXrAExTeSftyPajN0WWawNJU3uPTBgNrqNHyWSkiaN4 dAvEepfGuFQGz2Fj03Pv7OqY8veyRezErVRLwiMJRNyy7pi6Wng= =cKsD -----END PGP SIGNATURE----- Merge tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: - A big cleanup and optimization patch-set for the Tegra GART driver - Documentation updates and fixes for the IOMMU-API - Support for page request in Intel VT-d scalable mode - Intel VT-d dma_[un]map_resource() support - Updates to the ATS enabling code for PCI (acked by Bjorn) and Intel VT-d to align with the latest version of the ATS spec - Relaxed IRQ source checking in the Intel VT-d driver for some aliased devices, needed for future devices which send IRQ messages from more than on request-ID - IRQ remapping driver for Hyper-V - Patches to make generic IOVA and IO-Page-Table code usable outside of the IOMMU code - Various other small fixes and cleanups * tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (60 commits) iommu/vt-d: Get domain ID before clear pasid entry iommu/vt-d: Fix NULL pointer reference in intel_svm_bind_mm() iommu/vt-d: Set context field after value initialized iommu/vt-d: Disable ATS support on untrusted devices iommu/mediatek: Fix semicolon code style issue MAINTAINERS: Add Hyper-V IOMMU driver into Hyper-V CORE AND DRIVERS scope iommu/hyper-v: Add Hyper-V stub IOMMU driver x86/Hyper-V: Set x2apic destination mode to physical when x2apic is available PCI/ATS: Add inline to pci_prg_resp_pasid_required() iommu/vt-d: Check identity map for hot-added devices iommu: Fix IOMMU debugfs fallout iommu: Document iommu_ops.is_attach_deferred() iommu: Document iommu_ops.iotlb_sync_map() iommu/vt-d: Enable ATS only if the device uses page aligned address. PCI/ATS: Add pci_ats_page_aligned() interface iommu/vt-d: Fix PRI/PASID dependency issue. PCI/ATS: Add pci_prg_resp_pasid_required() interface. iommu/vt-d: Allow interrupts from the entire bus for aliased devices iommu/vt-d: Add helper to set an IRTE to verify only the bus number iommu: Fix flush_tlb_all typo ...
This commit is contained in:
Linus Torvalds
commit
bb97be23db
44 changed files with 844 additions and 617 deletions
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@ -374,20 +374,17 @@ enum {
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#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
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#define QI_DEV_EIOTLB_MAX_INVS 32
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#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
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#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
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#define QI_PGRP_RESP_CODE(res) ((u64)(res))
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#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
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#define QI_PGRP_DID(did) (((u64)(did)) << 16)
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/* Page group response descriptor QW0 */
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#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
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#define QI_PGRP_PDP(p) (((u64)(p)) << 5)
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#define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
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#define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
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#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
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/* Page group response descriptor QW1 */
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#define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
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#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
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#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
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#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
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#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
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#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
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#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
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#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
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#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
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#define QI_RESP_SUCCESS 0x0
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#define QI_RESP_INVALID 0x1
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@ -20,7 +20,7 @@ struct device;
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struct svm_dev_ops {
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void (*fault_cb)(struct device *dev, int pasid, u64 address,
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u32 private, int rwxp, int response);
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void *private, int rwxp, int response);
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};
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/* Values for rxwp in fault_cb callback */
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213
include/linux/io-pgtable.h
Normal file
213
include/linux/io-pgtable.h
Normal file
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@ -0,0 +1,213 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __IO_PGTABLE_H
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#define __IO_PGTABLE_H
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#include <linux/bitops.h>
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/*
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* Public API for use by IOMMU drivers
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*/
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enum io_pgtable_fmt {
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ARM_32_LPAE_S1,
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ARM_32_LPAE_S2,
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ARM_64_LPAE_S1,
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ARM_64_LPAE_S2,
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ARM_V7S,
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IO_PGTABLE_NUM_FMTS,
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};
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/**
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* struct iommu_gather_ops - IOMMU callbacks for TLB and page table management.
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*
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* @tlb_flush_all: Synchronously invalidate the entire TLB context.
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* @tlb_add_flush: Queue up a TLB invalidation for a virtual address range.
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* @tlb_sync: Ensure any queued TLB invalidation has taken effect, and
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* any corresponding page table updates are visible to the
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* IOMMU.
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*
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* Note that these can all be called in atomic context and must therefore
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* not block.
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*/
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struct iommu_gather_ops {
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void (*tlb_flush_all)(void *cookie);
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void (*tlb_add_flush)(unsigned long iova, size_t size, size_t granule,
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bool leaf, void *cookie);
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void (*tlb_sync)(void *cookie);
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};
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/**
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* struct io_pgtable_cfg - Configuration data for a set of page tables.
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*
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* @quirks: A bitmap of hardware quirks that require some special
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* action by the low-level page table allocator.
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* @pgsize_bitmap: A bitmap of page sizes supported by this set of page
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* tables.
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* @ias: Input address (iova) size, in bits.
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* @oas: Output address (paddr) size, in bits.
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* @tlb: TLB management callbacks for this set of tables.
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* @iommu_dev: The device representing the DMA configuration for the
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* page table walker.
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*/
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struct io_pgtable_cfg {
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/*
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* IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
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* stage 1 PTEs, for hardware which insists on validating them
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* even in non-secure state where they should normally be ignored.
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*
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* IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
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* IOMMU_NOEXEC flags and map everything with full access, for
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* hardware which does not implement the permissions of a given
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* format, and/or requires some format-specific default value.
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*
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* IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
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* (unmapped) entries but the hardware might do so anyway, perform
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* TLB maintenance when mapping as well as when unmapping.
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*
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* IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
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* PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
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* when the SoC is in "4GB mode" and they can only access the high
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* remap of DRAM (0x1_00000000 to 0x1_ffffffff).
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*
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* IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever
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* be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a
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* software-emulated IOMMU), such that pagetable updates need not
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* be treated as explicit DMA data.
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*
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* IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs
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* on unmap, for DMA domains using the flush queue mechanism for
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* delayed invalidation.
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*/
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#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
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#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
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#define IO_PGTABLE_QUIRK_TLBI_ON_MAP BIT(2)
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#define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3)
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#define IO_PGTABLE_QUIRK_NO_DMA BIT(4)
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#define IO_PGTABLE_QUIRK_NON_STRICT BIT(5)
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unsigned long quirks;
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unsigned long pgsize_bitmap;
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unsigned int ias;
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unsigned int oas;
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const struct iommu_gather_ops *tlb;
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struct device *iommu_dev;
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/* Low-level data specific to the table format */
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union {
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struct {
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u64 ttbr[2];
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u64 tcr;
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u64 mair[2];
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} arm_lpae_s1_cfg;
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struct {
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u64 vttbr;
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u64 vtcr;
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} arm_lpae_s2_cfg;
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struct {
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u32 ttbr[2];
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u32 tcr;
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u32 nmrr;
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u32 prrr;
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} arm_v7s_cfg;
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};
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};
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/**
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* struct io_pgtable_ops - Page table manipulation API for IOMMU drivers.
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*
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* @map: Map a physically contiguous memory region.
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* @unmap: Unmap a physically contiguous memory region.
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* @iova_to_phys: Translate iova to physical address.
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*
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* These functions map directly onto the iommu_ops member functions with
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* the same names.
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*/
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struct io_pgtable_ops {
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int (*map)(struct io_pgtable_ops *ops, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot);
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size_t (*unmap)(struct io_pgtable_ops *ops, unsigned long iova,
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size_t size);
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phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,
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unsigned long iova);
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};
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/**
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* alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU.
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*
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* @fmt: The page table format.
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* @cfg: The page table configuration. This will be modified to represent
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* the configuration actually provided by the allocator (e.g. the
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* pgsize_bitmap may be restricted).
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* the callback routines in cfg->tlb.
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*/
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struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
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struct io_pgtable_cfg *cfg,
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void *cookie);
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/**
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* free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller
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* *must* ensure that the page table is no longer
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* live, but the TLB can be dirty.
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*
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* @ops: The ops returned from alloc_io_pgtable_ops.
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*/
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void free_io_pgtable_ops(struct io_pgtable_ops *ops);
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/*
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* Internal structures for page table allocator implementations.
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*/
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/**
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* struct io_pgtable - Internal structure describing a set of page tables.
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*
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* @fmt: The page table format.
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* any callback routines.
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* @cfg: A copy of the page table configuration.
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* @ops: The page table operations in use for this set of page tables.
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*/
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struct io_pgtable {
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enum io_pgtable_fmt fmt;
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void *cookie;
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops ops;
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};
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#define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops)
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static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
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{
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iop->cfg.tlb->tlb_flush_all(iop->cookie);
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}
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static inline void io_pgtable_tlb_add_flush(struct io_pgtable *iop,
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unsigned long iova, size_t size, size_t granule, bool leaf)
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{
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iop->cfg.tlb->tlb_add_flush(iova, size, granule, leaf, iop->cookie);
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}
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static inline void io_pgtable_tlb_sync(struct io_pgtable *iop)
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{
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iop->cfg.tlb->tlb_sync(iop->cookie);
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}
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/**
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* struct io_pgtable_init_fns - Alloc/free a set of page tables for a
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* particular format.
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*
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* @alloc: Allocate a set of page tables described by cfg.
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* @free: Free the page tables associated with iop.
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*/
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struct io_pgtable_init_fns {
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struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie);
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void (*free)(struct io_pgtable *iop);
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};
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
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#endif /* __IO_PGTABLE_H */
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@ -167,8 +167,9 @@ struct iommu_resv_region {
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* @detach_dev: detach device from an iommu domain
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* @map: map a physically contiguous memory region to an iommu domain
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* @unmap: unmap a physically contiguous memory region from an iommu domain
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* @flush_tlb_all: Synchronously flush all hardware TLBs for this domain
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* @flush_iotlb_all: Synchronously flush all hardware TLBs for this domain
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* @iotlb_range_add: Add a given iova range to the flush queue for this domain
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* @iotlb_sync_map: Sync mappings created recently using @map to the hardware
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* @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
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* queue
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* @iova_to_phys: translate iova to physical address
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@ -183,6 +184,8 @@ struct iommu_resv_region {
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* @domain_window_enable: Configure and enable a particular window for a domain
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* @domain_window_disable: Disable a particular window for a domain
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* @of_xlate: add OF master IDs to iommu grouping
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* @is_attach_deferred: Check if domain attach should be deferred from iommu
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* driver init to device driver init (default no)
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* @pgsize_bitmap: bitmap of all possible supported page sizes
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*/
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struct iommu_ops {
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@ -201,6 +204,7 @@ struct iommu_ops {
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void (*flush_iotlb_all)(struct iommu_domain *domain);
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void (*iotlb_range_add)(struct iommu_domain *domain,
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unsigned long iova, size_t size);
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void (*iotlb_sync_map)(struct iommu_domain *domain);
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void (*iotlb_sync)(struct iommu_domain *domain);
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phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova);
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int (*add_device)(struct device *dev);
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@ -40,6 +40,7 @@ void pci_disable_pasid(struct pci_dev *pdev);
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void pci_restore_pasid_state(struct pci_dev *pdev);
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int pci_pasid_features(struct pci_dev *pdev);
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int pci_max_pasids(struct pci_dev *pdev);
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int pci_prg_resp_pasid_required(struct pci_dev *pdev);
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#else /* CONFIG_PCI_PASID */
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@ -66,6 +67,10 @@ static inline int pci_max_pasids(struct pci_dev *pdev)
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return -EINVAL;
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}
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static inline int pci_prg_resp_pasid_required(struct pci_dev *pdev)
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{
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return 0;
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}
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#endif /* CONFIG_PCI_PASID */
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@ -1527,11 +1527,13 @@ void pci_ats_init(struct pci_dev *dev);
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int pci_enable_ats(struct pci_dev *dev, int ps);
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void pci_disable_ats(struct pci_dev *dev);
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int pci_ats_queue_depth(struct pci_dev *dev);
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int pci_ats_page_aligned(struct pci_dev *dev);
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#else
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static inline void pci_ats_init(struct pci_dev *d) { }
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static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
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static inline void pci_disable_ats(struct pci_dev *d) { }
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static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
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static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
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#endif
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#ifdef CONFIG_PCIE_PTM
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|
|
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Loading…
Add table
Add a link
Reference in a new issue