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Merge 3.11-rc3 into driver-core-next

Browse source 
We want these fixes in this branch.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2013-07-29 12:30:13 -07:00
commit b78b6b3a9a
339 changed files with 6949 additions and 4821 deletions
Download patch file Download diff file Expand all files Collapse all files

1
include/linux/acpi.h
View file

@ -191,7 +191,6 @@ extern bool wmi_has_guid(const char *guid);
#define ACPI_VIDEO_BACKLIGHT_DMI_VIDEO 0x0200
#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR 0x0400
#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO 0x0800
#define ACPI_VIDEO_SKIP_BACKLIGHT 0x1000
#if defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE)

3
include/linux/cgroup.h
View file

@ -542,8 +542,7 @@ int cgroup_rm_cftypes(struct cgroup_subsys *ss, struct cftype *cfts);
bool cgroup_is_descendant(struct cgroup *cgrp, struct cgroup *ancestor);
int cgroup_path(const struct cgroup *cgrp, char *buf, int buflen);
int task_cgroup_path_from_hierarchy(struct task_struct *task, int hierarchy_id,
char *buf, size_t buflen);
int task_cgroup_path(struct task_struct *task, char *buf, size_t buflen);
int cgroup_task_count(const struct cgroup *cgrp);

45
include/linux/cgroup_subsys.h
View file

@ -1,86 +1,55 @@
/* Add subsystem definitions of the form SUBSYS(<name>) in this
* file. Surround each one by a line of comment markers so that
* patches don't collide
/*
* List of cgroup subsystems.
*
* DO NOT ADD ANY SUBSYSTEM WITHOUT EXPLICIT ACKS FROM CGROUP MAINTAINERS.
*/
/* */
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CPUSETS)
SUBSYS(cpuset)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_DEBUG)
SUBSYS(debug)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_SCHED)
SUBSYS(cpu_cgroup)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_CPUACCT)
SUBSYS(cpuacct)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_MEMCG)
SUBSYS(mem_cgroup)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_DEVICE)
SUBSYS(devices)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_FREEZER)
SUBSYS(freezer)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_NET_CLS_CGROUP)
SUBSYS(net_cls)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_BLK_CGROUP)
SUBSYS(blkio)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_PERF)
SUBSYS(perf)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_NETPRIO_CGROUP)
SUBSYS(net_prio)
#endif
/* */
#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_HUGETLB)
SUBSYS(hugetlb)
#endif
/* */
#ifdef CONFIG_CGROUP_BCACHE
SUBSYS(bcache)
#endif
/* */
/*
* DO NOT ADD ANY SUBSYSTEM WITHOUT EXPLICIT ACKS FROM CGROUP MAINTAINERS.
*/

4
include/linux/crc-t10dif.h
View file

@ -3,10 +3,6 @@
#include <linux/types.h>
#define CRC_T10DIF_DIGEST_SIZE 2
#define CRC_T10DIF_BLOCK_SIZE 1
__u16 crc_t10dif_generic(__u16 crc, const unsigned char *buffer, size_t len);
__u16 crc_t10dif(unsigned char const *, size_t);
#endif

6
include/linux/drbd.h
View file

@ -177,7 +177,11 @@ enum drbd_ret_code {
ERR_NEED_APV_100 = 163,
ERR_NEED_ALLOW_TWO_PRI = 164,
ERR_MD_UNCLEAN = 165,
ERR_MD_LAYOUT_CONNECTED = 166,
ERR_MD_LAYOUT_TOO_BIG = 167,
ERR_MD_LAYOUT_TOO_SMALL = 168,
ERR_MD_LAYOUT_NO_FIT = 169,
ERR_IMPLICIT_SHRINK = 170,
/* insert new ones above this line */
AFTER_LAST_ERR_CODE
};

2
include/linux/drbd_genl.h
View file

@ -181,6 +181,8 @@ GENL_struct(DRBD_NLA_RESIZE_PARMS, 7, resize_parms,
__u64_field(1, DRBD_GENLA_F_MANDATORY, resize_size)
__flg_field(2, DRBD_GENLA_F_MANDATORY, resize_force)
__flg_field(3, DRBD_GENLA_F_MANDATORY, no_resync)
__u32_field_def(4, 0 /* OPTIONAL */, al_stripes, DRBD_AL_STRIPES_DEF)
__u32_field_def(5, 0 /* OPTIONAL */, al_stripe_size, DRBD_AL_STRIPE_SIZE_DEF)
)
GENL_struct(DRBD_NLA_STATE_INFO, 8, state_info,

9
include/linux/drbd_limits.h
View file

@ -215,4 +215,13 @@
#define DRBD_ALWAYS_ASBP_DEF 0
#define DRBD_USE_RLE_DEF 1
#define DRBD_AL_STRIPES_MIN 1
#define DRBD_AL_STRIPES_MAX 1024
#define DRBD_AL_STRIPES_DEF 1
#define DRBD_AL_STRIPES_SCALE '1'
#define DRBD_AL_STRIPE_SIZE_MIN 4
#define DRBD_AL_STRIPE_SIZE_MAX 16777216
#define DRBD_AL_STRIPE_SIZE_DEF 32
#define DRBD_AL_STRIPE_SIZE_SCALE 'k' /* kilobytes */
#endif

7
include/linux/edac.h
View file

@ -622,7 +622,7 @@ struct edac_raw_error_desc {
*/
struct mem_ctl_info {
struct device dev;
struct bus_type bus;
struct bus_type *bus;
struct list_head link; /* for global list of mem_ctl_info structs */
@ -742,4 +742,9 @@ struct mem_ctl_info {
#endif
};
/*
* Maximum number of memory controllers in the coherent fabric.
*/
#define EDAC_MAX_MCS 16
#endif

137
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
View file

@ -103,15 +103,15 @@
#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
@ -279,41 +279,88 @@
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16)
#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16)
#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16)
#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16)
#define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0
#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
#define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11)
#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11)
#define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7)
#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7)
#define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2)
#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

2
include/linux/platform_data/mmc-pxamci.h
View file

@ -12,7 +12,7 @@ struct pxamci_platform_data {
unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
int (*init)(struct device *, irq_handler_t , void *);
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
int (*setpower)(struct device *, unsigned int);
void (*exit)(struct device *, void *);
int gpio_card_detect; /* gpio detecting card insertion */
int gpio_card_ro; /* gpio detecting read only toggle */

4
include/linux/shdma-base.h
View file

@ -124,6 +124,10 @@ void shdma_chan_remove(struct shdma_chan *schan);
int shdma_init(struct device *dev, struct shdma_dev *sdev,
int chan_num);
void shdma_cleanup(struct shdma_dev *sdev);
#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
bool shdma_chan_filter(struct dma_chan *chan, void *arg);
#else
#define shdma_chan_filter NULL
#endif
#endif

11
include/linux/usb.h
View file

@ -367,17 +367,6 @@ struct usb_bus {
/* ----------------------------------------------------------------------- */
/* This is arbitrary.
* From USB 2.0 spec Table 11-13, offset 7, a hub can
* have up to 255 ports. The most yet reported is 10.
*
* Current Wireless USB host hardware (Intel i1480 for example) allows
* up to 22 devices to connect. Upcoming hardware might raise that
* limit. Because the arrays need to add a bit for hub status data, we
* do 31, so plus one evens out to four bytes.
*/
#define USB_MAXCHILDREN (31)
struct usb_tt;
enum usb_device_removable {