ARM driver updates for 5.18
There are a few separately maintained driver subsystems that we merge through
the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs,
and clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport based
on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ
and older NVIDIA Tegra chips
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Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are a few separately maintained driver subsystems that we merge
through the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs, and
clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport
based on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
NVIDIA Tegra chips"
* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
ARM: spear: fix typos in comments
soc/microchip: fix invalid free in mpfs_sys_controller_delete
soc: s4: Add support for power domains controller
dt-bindings: power: add Amlogic s4 power domains bindings
ARM: at91: add support in soc driver for new SAMA5D29
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
memory: emif: check the pointer temp in get_device_details()
memory: emif: Add check for setup_interrupts
dt-bindings: arm: mediatek: mmsys: add support for MT8186
dt-bindings: mediatek: add compatible for MT8186 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
soc: mediatek: mmsys: add mmsys reset control for MT8186
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
soc: ti: k3-socinfo: Add AM62x JTAG ID
soc: mediatek: add MTK mutex support for MT8186
soc: mediatek: mmsys: add mt8186 mmsys routing table
soc: mediatek: pm-domains: Add support for mt8186
dt-bindings: power: Add MT8186 power domains
soc: mediatek: pm-domains: Add support for mt8195
...
This commit is contained in:
Linus Torvalds
commit
b4bc93bd76
124 changed files with 7644 additions and 1435 deletions
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@ -2,6 +2,88 @@
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
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#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
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#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
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#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
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#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
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#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
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#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
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#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
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#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
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#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
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#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
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#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
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#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
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#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
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#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
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#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
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#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
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#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
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#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
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#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
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#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
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#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
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#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
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#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
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#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
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#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
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#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
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#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1)
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#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)
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#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12))
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23)
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#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24)
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#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25)
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26)
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#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28))
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#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29))
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19))
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20)
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21)
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#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
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@ -58,6 +140,54 @@
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#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
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#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
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#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
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#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
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#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
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#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
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#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
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#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
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#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
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#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
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#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
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#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
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#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
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#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
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/* MFG1 */
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#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
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#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
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#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
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#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
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/* DIS */
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#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
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#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
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/* IMG */
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#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
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#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
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/* IPE */
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#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
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#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
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/* CAM */
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#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
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#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
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/* VENC */
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#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
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#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
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/* VDEC */
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#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
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#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
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/* WPE */
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#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
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#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
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/* CONN_ON */
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#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
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#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
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#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
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#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
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/* ADSP_TOP */
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#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
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#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
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#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
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#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
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@ -147,6 +277,9 @@
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#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
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#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
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#define MT8192_INFRA_CTRL 0x290
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#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9)
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#define REG_INFRA_MISC 0xf00
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#define F_DDR_4GB_SUPPORT_EN BIT(13)
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@ -35,7 +35,12 @@
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#define LLCC_WRCACHE 31
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#define LLCC_CVPFW 32
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#define LLCC_CPUSS1 33
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#define LLCC_CAMEXP0 34
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#define LLCC_CPUMTE 35
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#define LLCC_CPUHWT 36
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#define LLCC_MDMCLAD2 37
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#define LLCC_CAMEXP1 38
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#define LLCC_AENPU 45
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/**
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* struct llcc_slice_desc - Cache slice descriptor
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@ -83,7 +88,7 @@ struct llcc_edac_reg_data {
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* @bitmap: Bit map to track the active slice ids
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* @offsets: Pointer to the bank offsets array
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* @ecc_irq: interrupt for llcc cache error detection and reporting
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* @major_version: Indicates the LLCC major version
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* @version: Indicates the LLCC version
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*/
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struct llcc_drv_data {
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struct regmap *regmap;
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@ -96,7 +101,7 @@ struct llcc_drv_data {
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unsigned long *bitmap;
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u32 *offsets;
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int ecc_irq;
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u32 major_version;
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u32 version;
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};
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#if IS_ENABLED(CONFIG_QCOM_LLCC)
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@ -10,10 +10,14 @@
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struct device;
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struct firmware;
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struct qcom_scm_pas_metadata;
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#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
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ssize_t qcom_mdt_get_size(const struct firmware *fw);
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int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
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const char *fw_name, int pas_id, phys_addr_t mem_phys,
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struct qcom_scm_pas_metadata *pas_metadata_ctx);
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int qcom_mdt_load(struct device *dev, const struct firmware *fw,
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const char *fw_name, int pas_id, void *mem_region,
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phys_addr_t mem_phys, size_t mem_size,
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@ -23,7 +27,8 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
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const char *fw_name, int pas_id, void *mem_region,
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phys_addr_t mem_phys, size_t mem_size,
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phys_addr_t *reloc_base);
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void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len);
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void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
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const char *fw_name, struct device *dev);
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#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
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@ -32,6 +37,13 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
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return -ENODEV;
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}
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static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
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const char *fw_name, int pas_id, phys_addr_t mem_phys,
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struct qcom_scm_pas_metadata *pas_metadata_ctx)
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{
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return -ENODEV;
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}
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static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
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const char *fw_name, int pas_id,
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void *mem_region, phys_addr_t mem_phys,
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@ -51,7 +63,8 @@ static inline int qcom_mdt_load_no_init(struct device *dev,
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}
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static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
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size_t *data_len)
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size_t *data_len, const char *fw_name,
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struct device *dev)
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{
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return ERR_PTR(-ENODEV);
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}
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|
|
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@ -645,7 +645,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
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static inline struct ti_sci_resource *
|
||||
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
|
||||
u32 dev_id, u32 sub_type);
|
||||
u32 dev_id, u32 sub_type)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue