ARM driver updates for 5.18
There are a few separately maintained driver subsystems that we merge through
the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs,
and clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport based
on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ
and older NVIDIA Tegra chips
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Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are a few separately maintained driver subsystems that we merge
through the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs, and
clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport
based on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
NVIDIA Tegra chips"
* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
ARM: spear: fix typos in comments
soc/microchip: fix invalid free in mpfs_sys_controller_delete
soc: s4: Add support for power domains controller
dt-bindings: power: add Amlogic s4 power domains bindings
ARM: at91: add support in soc driver for new SAMA5D29
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
memory: emif: check the pointer temp in get_device_details()
memory: emif: Add check for setup_interrupts
dt-bindings: arm: mediatek: mmsys: add support for MT8186
dt-bindings: mediatek: add compatible for MT8186 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
soc: mediatek: mmsys: add mmsys reset control for MT8186
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
soc: ti: k3-socinfo: Add AM62x JTAG ID
soc: mediatek: add MTK mutex support for MT8186
soc: mediatek: mmsys: add mt8186 mmsys routing table
soc: mediatek: pm-domains: Add support for mt8186
dt-bindings: power: Add MT8186 power domains
soc: mediatek: pm-domains: Add support for mt8195
...
This commit is contained in:
Linus Torvalds
commit
b4bc93bd76
124 changed files with 7644 additions and 1435 deletions
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@ -59,11 +59,16 @@ enum imx_sc_rm_func {
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#if IS_ENABLED(CONFIG_IMX_SCU)
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bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource);
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int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt);
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#else
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static inline bool
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imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource)
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{
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return true;
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}
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static inline int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt)
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{
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return -EOPNOTSUPP;
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}
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#endif
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#endif
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@ -63,13 +63,21 @@ enum qcom_scm_ice_cipher {
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extern bool qcom_scm_is_available(void);
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_cold_boot_addr(void *entry);
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extern int qcom_scm_set_warm_boot_addr(void *entry);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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struct qcom_scm_pas_metadata {
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void *ptr;
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dma_addr_t phys;
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ssize_t size;
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};
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size);
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size_t size,
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struct qcom_scm_pas_metadata *ctx);
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void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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@ -83,6 +91,7 @@ extern bool qcom_scm_restore_sec_cfg_available(void);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
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extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
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u32 cp_nonpixel_start,
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u32 cp_nonpixel_size);
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@ -107,6 +116,7 @@ extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
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extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
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@ -42,6 +42,7 @@ struct scmi_revision_info {
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struct scmi_clock_info {
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char name[SCMI_MAX_STR_SIZE];
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unsigned int enable_latency;
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bool rate_discrete;
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union {
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struct {
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@ -82,6 +83,9 @@ struct scmi_clk_proto_ops {
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u64 rate);
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int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id);
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int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id);
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int (*enable_atomic)(const struct scmi_protocol_handle *ph, u32 clk_id);
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int (*disable_atomic)(const struct scmi_protocol_handle *ph,
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u32 clk_id);
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};
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/**
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@ -612,6 +616,15 @@ struct scmi_notify_ops {
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* @devm_protocol_get: devres managed method to acquire a protocol and get specific
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* operations and a dedicated protocol handler
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* @devm_protocol_put: devres managed method to release a protocol
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* @is_transport_atomic: method to check if the underlying transport for this
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* instance handle is configured to support atomic
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* transactions for commands.
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* Some users of the SCMI stack in the upper layers could
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* be interested to know if they can assume SCMI
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* command transactions associated to this handle will
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* never sleep and act accordingly.
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* An optional atomic threshold value could be returned
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* where configured.
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* @notify_ops: pointer to set of notifications related operations
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*/
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struct scmi_handle {
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@ -622,6 +635,8 @@ struct scmi_handle {
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(*devm_protocol_get)(struct scmi_device *sdev, u8 proto,
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struct scmi_protocol_handle **ph);
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void (*devm_protocol_put)(struct scmi_device *sdev, u8 proto);
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bool (*is_transport_atomic)(const struct scmi_handle *handle,
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unsigned int *atomic_threshold);
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const struct scmi_notify_ops *notify_ops;
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};
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@ -2,6 +2,88 @@
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
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#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
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#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
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#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
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#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
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#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
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#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
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#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
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#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
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#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
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#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
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#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
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#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
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#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
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#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
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#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
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#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
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#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
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#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
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#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
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#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
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#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
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#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
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#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
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#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
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#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
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#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
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#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
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#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1)
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#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)
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#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12))
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23)
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#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24)
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#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25)
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#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26)
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#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29)
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#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22)
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#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28))
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#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29))
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13)
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#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14)
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19))
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20)
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#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21)
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#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
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@ -58,6 +140,54 @@
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#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
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#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
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#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
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#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
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#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
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#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
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#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
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#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
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#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
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#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
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#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
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#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
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#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
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#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
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/* MFG1 */
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#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
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#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
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#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
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#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
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/* DIS */
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#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
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#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
|
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/* IMG */
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#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
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#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
|
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/* IPE */
|
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#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
|
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#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
|
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/* CAM */
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#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
|
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#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
|
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/* VENC */
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#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
|
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#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
|
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/* VDEC */
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#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
|
||||
/* WPE */
|
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#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
|
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#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
|
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/* CONN_ON */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
|
||||
/* ADSP_TOP */
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
|
||||
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
|
||||
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
|
|
@ -147,6 +277,9 @@
|
|||
#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
|
||||
#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
|
||||
|
||||
#define MT8192_INFRA_CTRL 0x290
|
||||
#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9)
|
||||
|
||||
#define REG_INFRA_MISC 0xf00
|
||||
#define F_DDR_4GB_SUPPORT_EN BIT(13)
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,12 @@
|
|||
#define LLCC_WRCACHE 31
|
||||
#define LLCC_CVPFW 32
|
||||
#define LLCC_CPUSS1 33
|
||||
#define LLCC_CAMEXP0 34
|
||||
#define LLCC_CPUMTE 35
|
||||
#define LLCC_CPUHWT 36
|
||||
#define LLCC_MDMCLAD2 37
|
||||
#define LLCC_CAMEXP1 38
|
||||
#define LLCC_AENPU 45
|
||||
|
||||
/**
|
||||
* struct llcc_slice_desc - Cache slice descriptor
|
||||
|
|
@ -83,7 +88,7 @@ struct llcc_edac_reg_data {
|
|||
* @bitmap: Bit map to track the active slice ids
|
||||
* @offsets: Pointer to the bank offsets array
|
||||
* @ecc_irq: interrupt for llcc cache error detection and reporting
|
||||
* @major_version: Indicates the LLCC major version
|
||||
* @version: Indicates the LLCC version
|
||||
*/
|
||||
struct llcc_drv_data {
|
||||
struct regmap *regmap;
|
||||
|
|
@ -96,7 +101,7 @@ struct llcc_drv_data {
|
|||
unsigned long *bitmap;
|
||||
u32 *offsets;
|
||||
int ecc_irq;
|
||||
u32 major_version;
|
||||
u32 version;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_LLCC)
|
||||
|
|
|
|||
|
|
@ -10,10 +10,14 @@
|
|||
|
||||
struct device;
|
||||
struct firmware;
|
||||
struct qcom_scm_pas_metadata;
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
|
||||
|
||||
ssize_t qcom_mdt_get_size(const struct firmware *fw);
|
||||
int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_metadata *pas_metadata_ctx);
|
||||
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
|
|
@ -23,7 +27,8 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
|
|||
const char *fw_name, int pas_id, void *mem_region,
|
||||
phys_addr_t mem_phys, size_t mem_size,
|
||||
phys_addr_t *reloc_base);
|
||||
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len);
|
||||
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
|
||||
const char *fw_name, struct device *dev);
|
||||
|
||||
#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
|
||||
|
||||
|
|
@ -32,6 +37,13 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id, phys_addr_t mem_phys,
|
||||
struct qcom_scm_pas_metadata *pas_metadata_ctx)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
|
||||
const char *fw_name, int pas_id,
|
||||
void *mem_region, phys_addr_t mem_phys,
|
||||
|
|
@ -51,7 +63,8 @@ static inline int qcom_mdt_load_no_init(struct device *dev,
|
|||
}
|
||||
|
||||
static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
|
||||
size_t *data_len)
|
||||
size_t *data_len, const char *fw_name,
|
||||
struct device *dev)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -645,7 +645,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
|
|||
|
||||
static inline struct ti_sci_resource *
|
||||
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
|
||||
u32 dev_id, u32 sub_type);
|
||||
u32 dev_id, u32 sub_type)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Linaro Limited
|
||||
* Copyright (c) 2015-2022 Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef __TEE_DRV_H
|
||||
|
|
@ -20,14 +20,11 @@
|
|||
* specific TEE driver.
|
||||
*/
|
||||
|
||||
#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */
|
||||
#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */
|
||||
#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */
|
||||
#define TEE_SHM_REGISTER BIT(3) /* Memory registered in secure world */
|
||||
#define TEE_SHM_USER_MAPPED BIT(4) /* Memory mapped in user space */
|
||||
#define TEE_SHM_POOL BIT(5) /* Memory allocated from pool */
|
||||
#define TEE_SHM_KERNEL_MAPPED BIT(6) /* Memory mapped in kernel space */
|
||||
#define TEE_SHM_PRIV BIT(7) /* Memory private to TEE driver */
|
||||
#define TEE_SHM_DYNAMIC BIT(0) /* Dynamic shared memory registered */
|
||||
/* in secure world */
|
||||
#define TEE_SHM_USER_MAPPED BIT(1) /* Memory mapped in user space */
|
||||
#define TEE_SHM_POOL BIT(2) /* Memory allocated from pool */
|
||||
#define TEE_SHM_PRIV BIT(3) /* Memory private to TEE driver */
|
||||
|
||||
struct device;
|
||||
struct tee_device;
|
||||
|
|
@ -221,92 +218,39 @@ struct tee_shm {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct tee_shm_pool_mgr - shared memory manager
|
||||
* struct tee_shm_pool - shared memory pool
|
||||
* @ops: operations
|
||||
* @private_data: private data for the shared memory manager
|
||||
*/
|
||||
struct tee_shm_pool_mgr {
|
||||
const struct tee_shm_pool_mgr_ops *ops;
|
||||
struct tee_shm_pool {
|
||||
const struct tee_shm_pool_ops *ops;
|
||||
void *private_data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tee_shm_pool_mgr_ops - shared memory pool manager operations
|
||||
* struct tee_shm_pool_ops - shared memory pool operations
|
||||
* @alloc: called when allocating shared memory
|
||||
* @free: called when freeing shared memory
|
||||
* @destroy_poolmgr: called when destroying the pool manager
|
||||
* @destroy_pool: called when destroying the pool
|
||||
*/
|
||||
struct tee_shm_pool_mgr_ops {
|
||||
int (*alloc)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm,
|
||||
size_t size);
|
||||
void (*free)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm);
|
||||
void (*destroy_poolmgr)(struct tee_shm_pool_mgr *poolmgr);
|
||||
struct tee_shm_pool_ops {
|
||||
int (*alloc)(struct tee_shm_pool *pool, struct tee_shm *shm,
|
||||
size_t size, size_t align);
|
||||
void (*free)(struct tee_shm_pool *pool, struct tee_shm *shm);
|
||||
void (*destroy_pool)(struct tee_shm_pool *pool);
|
||||
};
|
||||
|
||||
/**
|
||||
* tee_shm_pool_alloc() - Create a shared memory pool from shm managers
|
||||
* @priv_mgr: manager for driver private shared memory allocations
|
||||
* @dmabuf_mgr: manager for dma-buf shared memory allocations
|
||||
*
|
||||
* Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied
|
||||
* in @dmabuf, others will use the range provided by @priv.
|
||||
*
|
||||
* @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure.
|
||||
*/
|
||||
struct tee_shm_pool *tee_shm_pool_alloc(struct tee_shm_pool_mgr *priv_mgr,
|
||||
struct tee_shm_pool_mgr *dmabuf_mgr);
|
||||
|
||||
/*
|
||||
* tee_shm_pool_mgr_alloc_res_mem() - Create a shm manager for reserved
|
||||
* memory
|
||||
* tee_shm_pool_alloc_res_mem() - Create a shm manager for reserved memory
|
||||
* @vaddr: Virtual address of start of pool
|
||||
* @paddr: Physical address of start of pool
|
||||
* @size: Size in bytes of the pool
|
||||
*
|
||||
* @returns pointer to a 'struct tee_shm_pool_mgr' or an ERR_PTR on failure.
|
||||
*/
|
||||
struct tee_shm_pool_mgr *tee_shm_pool_mgr_alloc_res_mem(unsigned long vaddr,
|
||||
phys_addr_t paddr,
|
||||
size_t size,
|
||||
int min_alloc_order);
|
||||
|
||||
/**
|
||||
* tee_shm_pool_mgr_destroy() - Free a shared memory manager
|
||||
*/
|
||||
static inline void tee_shm_pool_mgr_destroy(struct tee_shm_pool_mgr *poolm)
|
||||
{
|
||||
poolm->ops->destroy_poolmgr(poolm);
|
||||
}
|
||||
|
||||
/**
|
||||
* struct tee_shm_pool_mem_info - holds information needed to create a shared
|
||||
* memory pool
|
||||
* @vaddr: Virtual address of start of pool
|
||||
* @paddr: Physical address of start of pool
|
||||
* @size: Size in bytes of the pool
|
||||
*/
|
||||
struct tee_shm_pool_mem_info {
|
||||
unsigned long vaddr;
|
||||
phys_addr_t paddr;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
/**
|
||||
* tee_shm_pool_alloc_res_mem() - Create a shared memory pool from reserved
|
||||
* memory range
|
||||
* @priv_info: Information for driver private shared memory pool
|
||||
* @dmabuf_info: Information for dma-buf shared memory pool
|
||||
*
|
||||
* Start and end of pools will must be page aligned.
|
||||
*
|
||||
* Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied
|
||||
* in @dmabuf, others will use the range provided by @priv.
|
||||
*
|
||||
* @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure.
|
||||
*/
|
||||
struct tee_shm_pool *
|
||||
tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info,
|
||||
struct tee_shm_pool_mem_info *dmabuf_info);
|
||||
struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr,
|
||||
phys_addr_t paddr, size_t size,
|
||||
int min_alloc_order);
|
||||
|
||||
/**
|
||||
* tee_shm_pool_free() - Free a shared memory pool
|
||||
|
|
@ -315,7 +259,10 @@ tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info,
|
|||
* The must be no remaining shared memory allocated from this pool when
|
||||
* this function is called.
|
||||
*/
|
||||
void tee_shm_pool_free(struct tee_shm_pool *pool);
|
||||
static inline void tee_shm_pool_free(struct tee_shm_pool *pool)
|
||||
{
|
||||
pool->ops->destroy_pool(pool);
|
||||
}
|
||||
|
||||
/**
|
||||
* tee_get_drvdata() - Return driver_data pointer
|
||||
|
|
@ -323,43 +270,20 @@ void tee_shm_pool_free(struct tee_shm_pool *pool);
|
|||
*/
|
||||
void *tee_get_drvdata(struct tee_device *teedev);
|
||||
|
||||
/**
|
||||
* tee_shm_alloc() - Allocate shared memory
|
||||
* @ctx: Context that allocates the shared memory
|
||||
* @size: Requested size of shared memory
|
||||
* @flags: Flags setting properties for the requested shared memory.
|
||||
*
|
||||
* Memory allocated as global shared memory is automatically freed when the
|
||||
* TEE file pointer is closed. The @flags field uses the bits defined by
|
||||
* TEE_SHM_* above. TEE_SHM_MAPPED must currently always be set. If
|
||||
* TEE_SHM_DMA_BUF global shared memory will be allocated and associated
|
||||
* with a dma-buf handle, else driver private memory.
|
||||
*
|
||||
* @returns a pointer to 'struct tee_shm'
|
||||
*/
|
||||
struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags);
|
||||
struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size);
|
||||
struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size);
|
||||
|
||||
/**
|
||||
* tee_shm_register() - Register shared memory buffer
|
||||
* @ctx: Context that registers the shared memory
|
||||
* @addr: Address is userspace of the shared buffer
|
||||
* @length: Length of the shared buffer
|
||||
* @flags: Flags setting properties for the requested shared memory.
|
||||
*
|
||||
* @returns a pointer to 'struct tee_shm'
|
||||
*/
|
||||
struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr,
|
||||
size_t length, u32 flags);
|
||||
struct tee_shm *tee_shm_register_kernel_buf(struct tee_context *ctx,
|
||||
void *addr, size_t length);
|
||||
|
||||
/**
|
||||
* tee_shm_is_registered() - Check if shared memory object in registered in TEE
|
||||
* tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind
|
||||
* @shm: Shared memory handle
|
||||
* @returns true if object is registered in TEE
|
||||
* @returns true if object is dynamic shared memory
|
||||
*/
|
||||
static inline bool tee_shm_is_registered(struct tee_shm *shm)
|
||||
static inline bool tee_shm_is_dynamic(struct tee_shm *shm)
|
||||
{
|
||||
return shm && (shm->flags & TEE_SHM_REGISTER);
|
||||
return shm && (shm->flags & TEE_SHM_DYNAMIC);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue