arm64 updates for 4.12:
- kdump support, including two necessary memblock additions: memblock_clear_nomap() and memblock_cap_memory_range() - ARMv8.3 HWCAP bits for JavaScript conversion instructions, complex numbers and weaker release consistency - arm64 ACPI platform MSI support - arm perf updates: ACPI PMU support, L3 cache PMU in some Qualcomm SoCs, Cortex-A53 L2 cache events and DTLB refills, MAINTAINERS update for DT perf bindings - architected timer errata framework (the arch/arm64 changes only) - support for DMA_ATTR_FORCE_CONTIGUOUS in the arm64 iommu DMA API - arm64 KVM refactoring to use common system register definitions - remove support for ASID-tagged VIVT I-cache (no ARMv8 implementation using it and deprecated in the architecture) together with some I-cache handling clean-up - PE/COFF EFI header clean-up/hardening - define BUG() instruction without CONFIG_BUG -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZDKMoAAoJEGvWsS0AyF7xR+YP/0EMEz5MDfCv0PVYj7/AIa0G Zphl7OhysIkeDAz7urXw9Jdl0NfORNIqmD1vZNVSc321IyNp56Od+kWd82lBrOWB ad3nNT67pEmu0pAW7CO48ju3rTesEnEl3ra45E1tULeLihmv93jc4ZlfXgumlKq3 /GE84XJ5ZFmluuhq1zgNefeUtyl1tbxTxHJ74+INF7dTd/5sJcphpqS4Dzpb+msT 20WYliccQCBF9zBFUYHc2KjcXXKRQGxLulGS3MuoN2DLkD+U9YyR/OmA7SoXh2J2 WXC5b0x856xTQJFCJ39pb7rw5xHjt3l5zfU3VLSvqEVL/+asBqCcgGNtNUgOW1Es dEHC6bc66Ley6mn7bbpFE3MK8D+K5q8HwMF6G5KDtIVB6DB/iQ6kzi5aXKoupxtb 1EuU4OW6cDhmOFQYjgIDofLgqbmVvJofdF6+NfxasfZmWrMgHzv0rYvaCDnAV/Tr t7bhH7hf9/KcP/wpk86O2AMKKpgoNTqe1Qy8cWVFFLnut567Pb6zs/L3ZXfleoLv t613yM8Zj2fE05ja8ylMDjaasidNpXGttb08/4kAn06Daaoueqla0jmduAhy4aaV dQ3OFP9lJ5MFaFnMMTPfU3vtvNLMHuo9MZsYCrv5zCaNNs3lpAPUiPNh588ZscKa sWx4PEiaCi+wcOsLsJvh =SDkm -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - kdump support, including two necessary memblock additions: memblock_clear_nomap() and memblock_cap_memory_range() - ARMv8.3 HWCAP bits for JavaScript conversion instructions, complex numbers and weaker release consistency - arm64 ACPI platform MSI support - arm perf updates: ACPI PMU support, L3 cache PMU in some Qualcomm SoCs, Cortex-A53 L2 cache events and DTLB refills, MAINTAINERS update for DT perf bindings - architected timer errata framework (the arch/arm64 changes only) - support for DMA_ATTR_FORCE_CONTIGUOUS in the arm64 iommu DMA API - arm64 KVM refactoring to use common system register definitions - remove support for ASID-tagged VIVT I-cache (no ARMv8 implementation using it and deprecated in the architecture) together with some I-cache handling clean-up - PE/COFF EFI header clean-up/hardening - define BUG() instruction without CONFIG_BUG * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) arm64: Fix the DMA mmap and get_sgtable API with DMA_ATTR_FORCE_CONTIGUOUS arm64: Print DT machine model in setup_machine_fdt() arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills arm64: module: split core and init PLT sections arm64: pmuv3: handle pmuv3+ arm64: Add CNTFRQ_EL0 trap handler arm64: Silence spurious kbuild warning on menuconfig arm64: pmuv3: use arm_pmu ACPI framework arm64: pmuv3: handle !PMUv3 when probing drivers/perf: arm_pmu: add ACPI framework arm64: add function to get a cpu's MADT GICC table drivers/perf: arm_pmu: split out platform device probe logic drivers/perf: arm_pmu: move irq request/free into probe drivers/perf: arm_pmu: split cpu-local irq request/free drivers/perf: arm_pmu: rename irq request/free functions drivers/perf: arm_pmu: handle no platform_device drivers/perf: arm_pmu: simplify cpu_pmu_request_irqs() drivers/perf: arm_pmu: factor out pmu registration drivers/perf: arm_pmu: fold init into alloc drivers/perf: arm_pmu: define armpmu_init_fn ...
This commit is contained in:
Linus Torvalds
commit
ab182e67ec
77 changed files with 3761 additions and 1263 deletions
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@ -34,6 +34,8 @@ void acpi_iort_init(void);
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bool iort_node_match(u8 type);
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u32 iort_msi_map_rid(struct device *dev, u32 req_id);
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struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id);
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void acpi_configure_pmsi_domain(struct device *dev);
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int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
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/* IOMMU interface */
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void iort_set_dma_mask(struct device *dev);
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const struct iommu_ops *iort_iommu_configure(struct device *dev);
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@ -45,6 +47,7 @@ static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
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static inline struct irq_domain *iort_get_device_domain(struct device *dev,
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u32 req_id)
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{ return NULL; }
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static inline void acpi_configure_pmsi_domain(struct device *dev) { }
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/* IOMMU interface */
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static inline void iort_set_dma_mask(struct device *dev) { }
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static inline
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@ -94,6 +94,7 @@ enum cpuhp_state {
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CPUHP_AP_ARM_VFP_STARTING,
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CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING,
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CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
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CPUHP_AP_PERF_ARM_ACPI_STARTING,
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CPUHP_AP_PERF_ARM_STARTING,
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CPUHP_AP_ARM_L2X0_STARTING,
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CPUHP_AP_ARM_ARCH_TIMER_STARTING,
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@ -137,6 +138,7 @@ enum cpuhp_state {
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CPUHP_AP_PERF_ARM_CCN_ONLINE,
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CPUHP_AP_PERF_ARM_L2X0_ONLINE,
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CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
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CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
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CPUHP_AP_WORKQUEUE_ONLINE,
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CPUHP_AP_RCUTREE_ONLINE,
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CPUHP_AP_ONLINE_DYN,
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@ -93,6 +93,7 @@ int memblock_mark_hotplug(phys_addr_t base, phys_addr_t size);
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int memblock_clear_hotplug(phys_addr_t base, phys_addr_t size);
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int memblock_mark_mirror(phys_addr_t base, phys_addr_t size);
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int memblock_mark_nomap(phys_addr_t base, phys_addr_t size);
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int memblock_clear_nomap(phys_addr_t base, phys_addr_t size);
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ulong choose_memblock_flags(void);
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/* Low level functions */
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@ -335,6 +336,7 @@ phys_addr_t memblock_mem_size(unsigned long limit_pfn);
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phys_addr_t memblock_start_of_DRAM(void);
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phys_addr_t memblock_end_of_DRAM(void);
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void memblock_enforce_memory_limit(phys_addr_t memory_limit);
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void memblock_cap_memory_range(phys_addr_t base, phys_addr_t size);
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void memblock_mem_limit_remove_map(phys_addr_t limit);
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bool memblock_is_memory(phys_addr_t addr);
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int memblock_is_map_memory(phys_addr_t addr);
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@ -23,34 +23,6 @@
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#define MZ_MAGIC 0x5a4d /* "MZ" */
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struct mz_hdr {
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uint16_t magic; /* MZ_MAGIC */
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uint16_t lbsize; /* size of last used block */
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uint16_t blocks; /* pages in file, 0x3 */
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uint16_t relocs; /* relocations */
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uint16_t hdrsize; /* header size in "paragraphs" */
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uint16_t min_extra_pps; /* .bss */
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uint16_t max_extra_pps; /* runtime limit for the arena size */
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uint16_t ss; /* relative stack segment */
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uint16_t sp; /* initial %sp register */
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uint16_t checksum; /* word checksum */
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uint16_t ip; /* initial %ip register */
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uint16_t cs; /* initial %cs relative to load segment */
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uint16_t reloc_table_offset; /* offset of the first relocation */
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uint16_t overlay_num; /* overlay number. set to 0. */
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uint16_t reserved0[4]; /* reserved */
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uint16_t oem_id; /* oem identifier */
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uint16_t oem_info; /* oem specific */
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uint16_t reserved1[10]; /* reserved */
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uint32_t peaddr; /* address of pe header */
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char message[64]; /* message to print */
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};
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struct mz_reloc {
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uint16_t offset;
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uint16_t segment;
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};
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#define PE_MAGIC 0x00004550 /* "PE\0\0" */
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#define PE_OPT_MAGIC_PE32 0x010b
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#define PE_OPT_MAGIC_PE32_ROM 0x0107
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@ -62,6 +34,7 @@ struct mz_reloc {
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#define IMAGE_FILE_MACHINE_AMD64 0x8664
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#define IMAGE_FILE_MACHINE_ARM 0x01c0
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#define IMAGE_FILE_MACHINE_ARMV7 0x01c4
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#define IMAGE_FILE_MACHINE_ARM64 0xaa64
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#define IMAGE_FILE_MACHINE_EBC 0x0ebc
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#define IMAGE_FILE_MACHINE_I386 0x014c
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#define IMAGE_FILE_MACHINE_IA64 0x0200
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@ -98,17 +71,6 @@ struct mz_reloc {
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#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000
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#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000
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struct pe_hdr {
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uint32_t magic; /* PE magic */
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uint16_t machine; /* machine type */
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uint16_t sections; /* number of sections */
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uint32_t timestamp; /* time_t */
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uint32_t symbol_table; /* symbol table offset */
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uint32_t symbols; /* number of symbols */
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uint16_t opt_hdr_size; /* size of optional header */
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uint16_t flags; /* flags */
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};
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#define IMAGE_FILE_OPT_ROM_MAGIC 0x107
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#define IMAGE_FILE_OPT_PE32_MAGIC 0x10b
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#define IMAGE_FILE_OPT_PE32_PLUS_MAGIC 0x20b
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@ -134,6 +96,95 @@ struct pe_hdr {
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#define IMAGE_DLLCHARACTERISTICS_WDM_DRIVER 0x2000
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#define IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE 0x8000
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/* they actually defined 0x00000000 as well, but I think we'll skip that one. */
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#define IMAGE_SCN_RESERVED_0 0x00000001
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#define IMAGE_SCN_RESERVED_1 0x00000002
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#define IMAGE_SCN_RESERVED_2 0x00000004
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#define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* don't pad - obsolete */
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#define IMAGE_SCN_RESERVED_3 0x00000010
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#define IMAGE_SCN_CNT_CODE 0x00000020 /* .text */
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#define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 /* .data */
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#define IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080 /* .bss */
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#define IMAGE_SCN_LNK_OTHER 0x00000100 /* reserved */
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#define IMAGE_SCN_LNK_INFO 0x00000200 /* .drectve comments */
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#define IMAGE_SCN_RESERVED_4 0x00000400
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#define IMAGE_SCN_LNK_REMOVE 0x00000800 /* .o only - scn to be rm'd*/
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#define IMAGE_SCN_LNK_COMDAT 0x00001000 /* .o only - COMDAT data */
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#define IMAGE_SCN_RESERVED_5 0x00002000 /* spec omits this */
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#define IMAGE_SCN_RESERVED_6 0x00004000 /* spec omits this */
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#define IMAGE_SCN_GPREL 0x00008000 /* global pointer referenced data */
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/* spec lists 0x20000 twice, I suspect they meant 0x10000 for one of them */
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#define IMAGE_SCN_MEM_PURGEABLE 0x00010000 /* reserved for "future" use */
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#define IMAGE_SCN_16BIT 0x00020000 /* reserved for "future" use */
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#define IMAGE_SCN_LOCKED 0x00040000 /* reserved for "future" use */
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#define IMAGE_SCN_PRELOAD 0x00080000 /* reserved for "future" use */
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/* and here they just stuck a 1-byte integer in the middle of a bitfield */
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#define IMAGE_SCN_ALIGN_1BYTES 0x00100000 /* it does what it says on the box */
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#define IMAGE_SCN_ALIGN_2BYTES 0x00200000
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#define IMAGE_SCN_ALIGN_4BYTES 0x00300000
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#define IMAGE_SCN_ALIGN_8BYTES 0x00400000
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#define IMAGE_SCN_ALIGN_16BYTES 0x00500000
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#define IMAGE_SCN_ALIGN_32BYTES 0x00600000
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#define IMAGE_SCN_ALIGN_64BYTES 0x00700000
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#define IMAGE_SCN_ALIGN_128BYTES 0x00800000
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#define IMAGE_SCN_ALIGN_256BYTES 0x00900000
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#define IMAGE_SCN_ALIGN_512BYTES 0x00a00000
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#define IMAGE_SCN_ALIGN_1024BYTES 0x00b00000
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#define IMAGE_SCN_ALIGN_2048BYTES 0x00c00000
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#define IMAGE_SCN_ALIGN_4096BYTES 0x00d00000
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#define IMAGE_SCN_ALIGN_8192BYTES 0x00e00000
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#define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* extended relocations */
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#define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 /* scn can be discarded */
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#define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* cannot be cached */
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#define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* not pageable */
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#define IMAGE_SCN_MEM_SHARED 0x10000000 /* can be shared */
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#define IMAGE_SCN_MEM_EXECUTE 0x20000000 /* can be executed as code */
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#define IMAGE_SCN_MEM_READ 0x40000000 /* readable */
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#define IMAGE_SCN_MEM_WRITE 0x80000000 /* writeable */
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#define IMAGE_DEBUG_TYPE_CODEVIEW 2
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#ifndef __ASSEMBLY__
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struct mz_hdr {
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uint16_t magic; /* MZ_MAGIC */
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uint16_t lbsize; /* size of last used block */
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uint16_t blocks; /* pages in file, 0x3 */
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uint16_t relocs; /* relocations */
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uint16_t hdrsize; /* header size in "paragraphs" */
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uint16_t min_extra_pps; /* .bss */
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uint16_t max_extra_pps; /* runtime limit for the arena size */
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uint16_t ss; /* relative stack segment */
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uint16_t sp; /* initial %sp register */
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uint16_t checksum; /* word checksum */
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uint16_t ip; /* initial %ip register */
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uint16_t cs; /* initial %cs relative to load segment */
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uint16_t reloc_table_offset; /* offset of the first relocation */
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uint16_t overlay_num; /* overlay number. set to 0. */
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uint16_t reserved0[4]; /* reserved */
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uint16_t oem_id; /* oem identifier */
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uint16_t oem_info; /* oem specific */
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uint16_t reserved1[10]; /* reserved */
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uint32_t peaddr; /* address of pe header */
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char message[64]; /* message to print */
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};
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struct mz_reloc {
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uint16_t offset;
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uint16_t segment;
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};
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struct pe_hdr {
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uint32_t magic; /* PE magic */
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uint16_t machine; /* machine type */
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uint16_t sections; /* number of sections */
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uint32_t timestamp; /* time_t */
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uint32_t symbol_table; /* symbol table offset */
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uint32_t symbols; /* number of symbols */
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uint16_t opt_hdr_size; /* size of optional header */
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uint16_t flags; /* flags */
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};
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/* the fact that pe32 isn't padded where pe32+ is 64-bit means union won't
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* work right. vomit. */
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struct pe32_opt_hdr {
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@ -243,52 +294,6 @@ struct section_header {
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uint32_t flags;
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};
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/* they actually defined 0x00000000 as well, but I think we'll skip that one. */
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#define IMAGE_SCN_RESERVED_0 0x00000001
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#define IMAGE_SCN_RESERVED_1 0x00000002
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#define IMAGE_SCN_RESERVED_2 0x00000004
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#define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* don't pad - obsolete */
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#define IMAGE_SCN_RESERVED_3 0x00000010
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#define IMAGE_SCN_CNT_CODE 0x00000020 /* .text */
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#define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 /* .data */
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#define IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080 /* .bss */
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#define IMAGE_SCN_LNK_OTHER 0x00000100 /* reserved */
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#define IMAGE_SCN_LNK_INFO 0x00000200 /* .drectve comments */
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#define IMAGE_SCN_RESERVED_4 0x00000400
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#define IMAGE_SCN_LNK_REMOVE 0x00000800 /* .o only - scn to be rm'd*/
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#define IMAGE_SCN_LNK_COMDAT 0x00001000 /* .o only - COMDAT data */
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#define IMAGE_SCN_RESERVED_5 0x00002000 /* spec omits this */
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#define IMAGE_SCN_RESERVED_6 0x00004000 /* spec omits this */
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#define IMAGE_SCN_GPREL 0x00008000 /* global pointer referenced data */
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/* spec lists 0x20000 twice, I suspect they meant 0x10000 for one of them */
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#define IMAGE_SCN_MEM_PURGEABLE 0x00010000 /* reserved for "future" use */
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#define IMAGE_SCN_16BIT 0x00020000 /* reserved for "future" use */
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#define IMAGE_SCN_LOCKED 0x00040000 /* reserved for "future" use */
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#define IMAGE_SCN_PRELOAD 0x00080000 /* reserved for "future" use */
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/* and here they just stuck a 1-byte integer in the middle of a bitfield */
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#define IMAGE_SCN_ALIGN_1BYTES 0x00100000 /* it does what it says on the box */
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#define IMAGE_SCN_ALIGN_2BYTES 0x00200000
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#define IMAGE_SCN_ALIGN_4BYTES 0x00300000
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#define IMAGE_SCN_ALIGN_8BYTES 0x00400000
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#define IMAGE_SCN_ALIGN_16BYTES 0x00500000
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#define IMAGE_SCN_ALIGN_32BYTES 0x00600000
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#define IMAGE_SCN_ALIGN_64BYTES 0x00700000
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#define IMAGE_SCN_ALIGN_128BYTES 0x00800000
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#define IMAGE_SCN_ALIGN_256BYTES 0x00900000
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#define IMAGE_SCN_ALIGN_512BYTES 0x00a00000
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#define IMAGE_SCN_ALIGN_1024BYTES 0x00b00000
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#define IMAGE_SCN_ALIGN_2048BYTES 0x00c00000
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#define IMAGE_SCN_ALIGN_4096BYTES 0x00d00000
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#define IMAGE_SCN_ALIGN_8192BYTES 0x00e00000
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#define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* extended relocations */
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#define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 /* scn can be discarded */
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#define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* cannot be cached */
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#define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* not pageable */
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#define IMAGE_SCN_MEM_SHARED 0x10000000 /* can be shared */
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#define IMAGE_SCN_MEM_EXECUTE 0x20000000 /* can be executed as code */
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#define IMAGE_SCN_MEM_READ 0x40000000 /* readable */
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#define IMAGE_SCN_MEM_WRITE 0x80000000 /* writeable */
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enum x64_coff_reloc_type {
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IMAGE_REL_AMD64_ABSOLUTE = 0,
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IMAGE_REL_AMD64_ADDR64,
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@ -445,4 +450,6 @@ struct win_certificate {
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uint16_t cert_type;
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};
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#endif /* !__ASSEMBLY__ */
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#endif /* __LINUX_PE_H */
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|
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@ -75,6 +75,8 @@ struct pmu_hw_events {
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* already have to allocate this struct per cpu.
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*/
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struct arm_pmu *percpu_pmu;
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int irq;
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};
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enum armpmu_attr_groups {
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@ -88,7 +90,6 @@ struct arm_pmu {
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struct pmu pmu;
|
||||
cpumask_t active_irqs;
|
||||
cpumask_t supported_cpus;
|
||||
int *irq_affinity;
|
||||
char *name;
|
||||
irqreturn_t (*handle_irq)(int irq_num, void *dev);
|
||||
void (*enable)(struct perf_event *event);
|
||||
|
|
@ -104,12 +105,8 @@ struct arm_pmu {
|
|||
void (*start)(struct arm_pmu *);
|
||||
void (*stop)(struct arm_pmu *);
|
||||
void (*reset)(void *);
|
||||
int (*request_irq)(struct arm_pmu *, irq_handler_t handler);
|
||||
void (*free_irq)(struct arm_pmu *);
|
||||
int (*map_event)(struct perf_event *event);
|
||||
int num_events;
|
||||
atomic_t active_events;
|
||||
struct mutex reserve_mutex;
|
||||
u64 max_period;
|
||||
bool secure_access; /* 32-bit ARM only */
|
||||
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
|
||||
|
|
@ -120,6 +117,9 @@ struct arm_pmu {
|
|||
struct notifier_block cpu_pm_nb;
|
||||
/* the attr_groups array must be NULL-terminated */
|
||||
const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
|
||||
|
||||
/* Only to be used by ACPI probing code */
|
||||
unsigned long acpi_cpuid;
|
||||
};
|
||||
|
||||
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
|
||||
|
|
@ -135,10 +135,12 @@ int armpmu_map_event(struct perf_event *event,
|
|||
[PERF_COUNT_HW_CACHE_RESULT_MAX],
|
||||
u32 raw_event_mask);
|
||||
|
||||
typedef int (*armpmu_init_fn)(struct arm_pmu *);
|
||||
|
||||
struct pmu_probe_info {
|
||||
unsigned int cpuid;
|
||||
unsigned int mask;
|
||||
int (*init)(struct arm_pmu *);
|
||||
armpmu_init_fn init;
|
||||
};
|
||||
|
||||
#define PMU_PROBE(_cpuid, _mask, _fn) \
|
||||
|
|
@ -160,6 +162,21 @@ int arm_pmu_device_probe(struct platform_device *pdev,
|
|||
const struct of_device_id *of_table,
|
||||
const struct pmu_probe_info *probe_table);
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
|
||||
#else
|
||||
static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
|
||||
#endif
|
||||
|
||||
/* Internal functions only for core arm_pmu code */
|
||||
struct arm_pmu *armpmu_alloc(void);
|
||||
void armpmu_free(struct arm_pmu *pmu);
|
||||
int armpmu_register(struct arm_pmu *pmu);
|
||||
int armpmu_request_irqs(struct arm_pmu *armpmu);
|
||||
void armpmu_free_irqs(struct arm_pmu *armpmu);
|
||||
int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
|
||||
void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
|
||||
|
||||
#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
|
||||
|
||||
#endif /* CONFIG_ARM_PMU */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue