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Merge branch 'seville-shared-mdio'

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Colin Foster says:

====================
update seville to use shared MDIO driver

This patch set exposes and utilizes the shared MDIO bus in
drivers/net/mdio/msio-mscc-miim.c

v3:
    * Fix errors using uninitilized "dev" inside the probe function.
    * Remove phy_regmap from the setup function, since it currently
    isn't used
    * Remove GCB_PHY_PHY_CFG definition from ocelot.h - it isn't used
    yet...

v2:
    * Error handling (thanks Andrew Lunn)
    * Fix logic errors calling mscc_miim_setup during patch 1/3 (thanks
    Jakub Kicinski)
    * Remove unnecessary felix_mdio file (thanks Vladimir Oltean)
    * Pass NULL to mscc_miim_setup instead of GCB_PHY_PHY_CFG, since the
    phy reset isn't handled at that point of the Seville driver (patch
    3/3)
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2021-11-29 13:02:01 +00:00
commit a4920d5d98
4 changed files with 170 additions and 138 deletions
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1
drivers/net/dsa/ocelot/Kconfig
View file

@ -21,6 +21,7 @@ config NET_DSA_MSCC_SEVILLE
depends on NET_VENDOR_MICROSEMI
depends on HAS_IOMEM
depends on PTP_1588_CLOCK_OPTIONAL
select MDIO_MSCC_MIIM
select MSCC_OCELOT_SWITCH_LIB
select NET_DSA_TAG_OCELOT_8021Q
select NET_DSA_TAG_OCELOT

103
drivers/net/dsa/ocelot/seville_vsc9953.c
View file

@ -6,18 +6,14 @@
#include <soc/mscc/ocelot_vcap.h>
#include <soc/mscc/ocelot_sys.h>
#include <soc/mscc/ocelot.h>
#include <linux/mdio/mdio-mscc-miim.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/pcs-lynx.h>
#include <linux/dsa/ocelot.h>
#include <linux/iopoll.h>
#include "felix.h"
#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
#define MSCC_MIIM_CMD_OPR_READ BIT(2)
#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
#define MSCC_MIIM_CMD_REGAD_SHIFT 20
#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
#define MSCC_MIIM_CMD_VLD BIT(31)
#define VSC9953_VCAP_POLICER_BASE 11
#define VSC9953_VCAP_POLICER_MAX 31
#define VSC9953_VCAP_POLICER_BASE2 120
@ -861,7 +857,6 @@ static struct vcap_props vsc9953_vcap_props[] = {
#define VSC9953_INIT_TIMEOUT 50000
#define VSC9953_GCB_RST_SLEEP 100
#define VSC9953_SYS_RAMINIT_SLEEP 80
#define VCS9953_MII_TIMEOUT 10000
static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
{
@ -881,82 +876,6 @@ static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
return val;
}
static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot)
{
int val;
ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val);
return val;
}
static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot)
{
int val;
ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val);
return val;
}
static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
u16 value)
{
struct ocelot *ocelot = bus->priv;
int err, cmd, val;
/* Wait while MIIM controller becomes idle */
err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
val, !val, 10, VCS9953_MII_TIMEOUT);
if (err) {
dev_err(ocelot->dev, "MDIO write: pending timeout\n");
goto out;
}
cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
MSCC_MIIM_CMD_OPR_WRITE;
ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
out:
return err;
}
static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
struct ocelot *ocelot = bus->priv;
int err, cmd, val;
/* Wait until MIIM controller becomes idle */
err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
val, !val, 10, VCS9953_MII_TIMEOUT);
if (err) {
dev_err(ocelot->dev, "MDIO read: pending timeout\n");
goto out;
}
/* Write the MIIM COMMAND register */
cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ;
ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
/* Wait while read operation via the MIIM controller is in progress */
err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot,
val, !val, 10, VCS9953_MII_TIMEOUT);
if (err) {
dev_err(ocelot->dev, "MDIO read: busy timeout\n");
goto out;
}
val = ocelot_read(ocelot, GCB_MIIM_MII_DATA);
err = val & 0xFFFF;
out:
return err;
}
/* CORE_ENA is in SYS:SYSTEM:RESET_CFG
* MEM_INIT is in SYS:SYSTEM:RESET_CFG
@ -1100,19 +1019,17 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
return -ENOMEM;
}
bus = devm_mdiobus_alloc(dev);
if (!bus)
return -ENOMEM;
rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus",
ocelot->targets[GCB],
ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]);
bus->name = "VSC9953 internal MDIO bus";
bus->read = vsc9953_mdio_read;
bus->write = vsc9953_mdio_write;
bus->parent = dev;
bus->priv = ocelot;
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
if (rc) {
dev_err(dev, "failed to setup MDIO bus\n");
return rc;
}
/* Needed in order to initialize the bus mutex lock */
rc = mdiobus_register(bus);
rc = of_mdiobus_register(bus, NULL);
if (rc < 0) {
dev_err(dev, "failed to register MDIO bus\n");
return rc;

185
drivers/net/mdio/mdio-mscc-miim.c
View file

@ -10,10 +10,12 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mdio/mdio-mscc-miim.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define MSCC_MIIM_REG_STATUS 0x0
#define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
@ -35,37 +37,52 @@
#define MSCC_PHY_REG_PHY_STATUS 0x4
struct mscc_miim_dev {
void __iomem *regs;
void __iomem *phy_regs;
struct regmap *regs;
int mii_status_offset;
struct regmap *phy_regs;
int phy_reset_offset;
};
/* When high resolution timers aren't built-in: we can't use usleep_range() as
* we would sleep way too long. Use udelay() instead.
*/
#define mscc_readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \
({ \
if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
readl_poll_timeout_atomic(addr, val, cond, delay_us, \
timeout_us); \
readl_poll_timeout(addr, val, cond, delay_us, timeout_us); \
#define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
({ \
if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
readx_poll_timeout_atomic(op, addr, val, cond, delay_us, \
timeout_us); \
readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us); \
})
static int mscc_miim_status(struct mii_bus *bus)
{
struct mscc_miim_dev *miim = bus->priv;
int val, ret;
ret = regmap_read(miim->regs,
MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
if (ret < 0) {
WARN_ONCE(1, "mscc miim status read error %d\n", ret);
return ret;
}
return val;
}
static int mscc_miim_wait_ready(struct mii_bus *bus)
{
struct mscc_miim_dev *miim = bus->priv;
u32 val;
return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val,
return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
!(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
10000);
}
static int mscc_miim_wait_pending(struct mii_bus *bus)
{
struct mscc_miim_dev *miim = bus->priv;
u32 val;
return mscc_readl_poll_timeout(miim->regs + MSCC_MIIM_REG_STATUS, val,
return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
!(val & MSCC_MIIM_STATUS_STAT_PENDING),
50, 10000);
}
@ -80,15 +97,29 @@ static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
if (ret)
goto out;
writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ,
miim->regs + MSCC_MIIM_REG_CMD);
ret = regmap_write(miim->regs,
MSCC_MIIM_REG_CMD + miim->mii_status_offset,
MSCC_MIIM_CMD_VLD |
(mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
MSCC_MIIM_CMD_OPR_READ);
if (ret < 0) {
WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
goto out;
}
ret = mscc_miim_wait_ready(bus);
if (ret)
goto out;
val = readl(miim->regs + MSCC_MIIM_REG_DATA);
ret = regmap_read(miim->regs,
MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
if (ret < 0) {
WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
goto out;
}
if (val & MSCC_MIIM_DATA_ERROR) {
ret = -EIO;
goto out;
@ -109,12 +140,16 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id,
if (ret < 0)
goto out;
writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
MSCC_MIIM_CMD_OPR_WRITE,
miim->regs + MSCC_MIIM_REG_CMD);
ret = regmap_write(miim->regs,
MSCC_MIIM_REG_CMD + miim->mii_status_offset,
MSCC_MIIM_CMD_VLD |
(mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
MSCC_MIIM_CMD_OPR_WRITE);
if (ret < 0)
WARN_ONCE(1, "mscc miim write error %d\n", ret);
out:
return ret;
}
@ -122,51 +157,111 @@ out:
static int mscc_miim_reset(struct mii_bus *bus)
{
struct mscc_miim_dev *miim = bus->priv;
int offset = miim->phy_reset_offset;
int ret;
if (miim->phy_regs) {
writel(0, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
writel(0x1ff, miim->phy_regs + MSCC_PHY_REG_PHY_CFG);
ret = regmap_write(miim->phy_regs,
MSCC_PHY_REG_PHY_CFG + offset, 0);
if (ret < 0) {
WARN_ONCE(1, "mscc reset set error %d\n", ret);
return ret;
}
ret = regmap_write(miim->phy_regs,
MSCC_PHY_REG_PHY_CFG + offset, 0x1ff);
if (ret < 0) {
WARN_ONCE(1, "mscc reset clear error %d\n", ret);
return ret;
}
mdelay(500);
}
return 0;
}
static int mscc_miim_probe(struct platform_device *pdev)
{
struct mscc_miim_dev *dev;
struct resource *res;
struct mii_bus *bus;
int ret;
static const struct regmap_config mscc_miim_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*dev));
int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
struct regmap *mii_regmap, int status_offset)
{
struct mscc_miim_dev *miim;
struct mii_bus *bus;
bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
if (!bus)
return -ENOMEM;
bus->name = "mscc_miim";
bus->name = name;
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
bus->reset = mscc_miim_reset;
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
bus->parent = &pdev->dev;
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
bus->parent = dev;
dev = bus->priv;
dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(dev->regs)) {
miim = bus->priv;
*pbus = bus;
miim->regs = mii_regmap;
miim->mii_status_offset = status_offset;
*pbus = bus;
return 0;
}
EXPORT_SYMBOL(mscc_miim_setup);
static int mscc_miim_probe(struct platform_device *pdev)
{
struct regmap *mii_regmap, *phy_regmap;
void __iomem *regs, *phy_regs;
struct mscc_miim_dev *miim;
struct mii_bus *bus;
int ret;
regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(regs)) {
dev_err(&pdev->dev, "Unable to map MIIM registers\n");
return PTR_ERR(dev->regs);
return PTR_ERR(regs);
}
/* This resource is optional */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (res) {
dev->phy_regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dev->phy_regs)) {
dev_err(&pdev->dev, "Unable to map internal phy registers\n");
return PTR_ERR(dev->phy_regs);
}
mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&mscc_miim_regmap_config);
if (IS_ERR(mii_regmap)) {
dev_err(&pdev->dev, "Unable to create MIIM regmap\n");
return PTR_ERR(mii_regmap);
}
phy_regs = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(phy_regs)) {
dev_err(&pdev->dev, "Unable to map internal phy registers\n");
return PTR_ERR(phy_regs);
}
phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs,
&mscc_miim_regmap_config);
if (IS_ERR(phy_regmap)) {
dev_err(&pdev->dev, "Unable to create phy register regmap\n");
return PTR_ERR(phy_regmap);
}
ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to setup the MDIO bus\n");
return ret;
}
miim = bus->priv;
miim->phy_regs = phy_regmap;
miim->phy_reset_offset = 0;
ret = of_mdiobus_register(bus, pdev->dev.of_node);
if (ret < 0) {
dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);

19
include/linux/mdio/mdio-mscc-miim.h Normal file
View file

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Driver for the MDIO interface of Microsemi network switches.
*
* Author: Colin Foster <colin.foster@in-advantage.com>
* Copyright (C) 2021 Innovative Advantage
*/
#ifndef MDIO_MSCC_MIIM_H
#define MDIO_MSCC_MIIM_H
#include <linux/device.h>
#include <linux/phy.h>
#include <linux/regmap.h>
int mscc_miim_setup(struct device *device, struct mii_bus **bus,
const char *name, struct regmap *mii_regmap,
int status_offset);
#endif