serial: 8250: Add new port type for TI DA8xx/66AK2x
This adds a new UART port type for TI DA8xx/OMAPL13x/AM17xx/AM18xx/66AK2x. These SoCs have standard 8250 registers plus some extra non-standard registers. The UART will not function unless the non-standard Power and Emulation Management Register (PWREMU_MGMT) is configured correctly. This is currently handled in arch/arm/mach-davinci/serial.c for non-device-tree boards. Making this part of the UART driver will allow UART to work on device-tree boards as well and the mach code can eventually be removed. Signed-off-by: David Lechner <david@lechnology.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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4 changed files with 33 additions and 1 deletions
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@ -56,7 +56,8 @@
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#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
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#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
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#define PORT_MAX_8250 30 /* max port ID */
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#define PORT_DA830 31 /* TI DA8xx/66AK2x */
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#define PORT_MAX_8250 31 /* max port ID */
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/*
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* ARM specific type numbers. These are not currently guaranteed
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@ -327,6 +327,14 @@
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#define SERIAL_RSA_BAUD_BASE (921600)
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#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
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/* Extra registers for TI DA8xx/66AK2x */
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#define UART_DA830_PWREMU_MGMT 12
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/* PWREMU_MGMT register bits */
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#define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
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#define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
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#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
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/*
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* Extra serial register definitions for the internal UARTs
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* in TI OMAP processors.
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