Updates for interrupt core and drivers:
core:
- Fix a few inconsistencies between UP and SMP vs. interrupt affinities
- Small updates and cleanups all over the place
drivers:
- New driver for the LoongArch interrupt controller
- New driver for the Renesas RZ/G2L interrupt controller
- Hotpath optimization for SiFive PLIC
- Workaround for broken PLIC edge triggered interrupts
- Simall cleanups and improvements as usual
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmLn5agTHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYoV2HD/4u0+09Fd8Awt1Knnb4CInmwFihZ/bu
EiS1Air+MEJ/fyFb5sT/Dn8YdUWYA6a3ifpLMGBwrKCcb5pMwPEtI8uqjSmtgsN/
2Z4o3N5v6EgM25CtrHNBrXK0E9Rz5Py49gm5p3K7+h4g63z9JwrM4G0Bvr8+krLS
EV9IZU6kVmGC6gnG/MspkArsLk1rCM0PU0SJ2lEPsWd1fjhVSDfunvy/qnnzXRzz
wjrcAf+a2Kgb1TMnpL6tx9d2Xx8KrKfODZTdOmPHrdv58F0EbJzapJnAVkYZDPtR
LE2kQc2Qhdawx0kgNNNhvu9P6oZtpnK9N7KAhDQdw17sgrRygINjAMSEe2RykYL1
lK+lJOIzfyd2JkEuC/8w1ZezL88S0EaTNawrkxjJ8L3fa7WDbwilCC+1w95QydCv
sQB137OaLKgWetcRsht9PLWFb4ujkWzxoPf2cPPsm81EzCicNtBuNPLReBTcNrWJ
X2VPpbaqRK8t8bnkXRqhahbq7f8c86feoICHfA4c7T4eZUp/Oq6T8aNvf6WPgjae
I2/FO6kxZj3CQqFkhJGhiZRtGZdx6HLCsL84A+2Ktsra+D8+/qecZCnkHYtz0Vo6
aFuGg+Wj+zuc2QfdaWwG8Dh5dijbxgHGHhzbh9znsWzytN9gfoBxuvBejf65i6sC
In63mEkv35ttfA==
=OnhF
-----END PGP SIGNATURE-----
Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"Updates for interrupt core and drivers:
Core:
- Fix a few inconsistencies between UP and SMP vs interrupt
affinities
- Small updates and cleanups all over the place
New drivers:
- LoongArch interrupt controller
- Renesas RZ/G2L interrupt controller
Updates:
- Hotpath optimization for SiFive PLIC
- Workaround for broken PLIC edge triggered interrupts
- Simall cleanups and improvements as usual"
* tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits)
irqchip/mmp: Declare init functions in common header file
irqchip/mips-gic: Check the return value of ioremap() in gic_of_init()
genirq: Use for_each_action_of_desc in actions_show()
irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
irqchip: Add LoongArch CPU interrupt controller support
irqchip: Add Loongson Extended I/O interrupt controller support
irqchip/loongson-liointc: Add ACPI init support
irqchip/loongson-pch-msi: Add ACPI init support
irqchip/loongson-pch-pic: Add ACPI init support
irqchip: Add Loongson PCH LPC controller support
LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
LoongArch: Use ACPI_GENERIC_GSI for gsi handling
genirq/generic_chip: Export irq_unmap_generic_chip
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
APCI: irq: Add support for multiple GSI domains
LoongArch: Provisionally add ACPICA data structures
irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains
irqdomain: Report irq number for NOMAP domains
irqchip/gic-v3: Fix comment typo
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC
...
This commit is contained in:
commit
9de1f9c8ca
69 changed files with 2784 additions and 667 deletions
|
|
@ -105,6 +105,7 @@ enum acpi_irq_model_id {
|
|||
ACPI_IRQ_MODEL_IOSAPIC,
|
||||
ACPI_IRQ_MODEL_PLATFORM,
|
||||
ACPI_IRQ_MODEL_GIC,
|
||||
ACPI_IRQ_MODEL_LPIC,
|
||||
ACPI_IRQ_MODEL_COUNT
|
||||
};
|
||||
|
||||
|
|
@ -356,7 +357,8 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
|
|||
int acpi_isa_irq_to_gsi (unsigned isa_irq, u32 *gsi);
|
||||
|
||||
void acpi_set_irq_model(enum acpi_irq_model_id model,
|
||||
struct fwnode_handle *fwnode);
|
||||
struct fwnode_handle *(*)(u32));
|
||||
void acpi_set_gsi_to_irq_fallback(u32 (*)(u32));
|
||||
|
||||
struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
|
||||
unsigned int size,
|
||||
|
|
|
|||
|
|
@ -150,6 +150,7 @@ enum cpuhp_state {
|
|||
CPUHP_AP_IRQ_BCM2836_STARTING,
|
||||
CPUHP_AP_IRQ_MIPS_GIC_STARTING,
|
||||
CPUHP_AP_IRQ_RISCV_STARTING,
|
||||
CPUHP_AP_IRQ_LOONGARCH_STARTING,
|
||||
CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
|
||||
CPUHP_AP_ARM_MVEBU_COHERENCY,
|
||||
CPUHP_AP_MICROCODE_LOADER,
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
#include <linux/property.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/msi.h>
|
||||
|
||||
struct gpio_desc;
|
||||
struct of_phandle_args;
|
||||
struct device_node;
|
||||
|
|
@ -23,6 +25,13 @@ enum gpio_lookup_flags;
|
|||
|
||||
struct gpio_chip;
|
||||
|
||||
union gpio_irq_fwspec {
|
||||
struct irq_fwspec fwspec;
|
||||
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
|
||||
msi_alloc_info_t msiinfo;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define GPIO_LINE_DIRECTION_IN 1
|
||||
#define GPIO_LINE_DIRECTION_OUT 0
|
||||
|
||||
|
|
@ -103,9 +112,10 @@ struct gpio_irq_chip {
|
|||
* variant named &gpiochip_populate_parent_fwspec_fourcell is also
|
||||
* available.
|
||||
*/
|
||||
void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type);
|
||||
int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
|
||||
union gpio_irq_fwspec *fwspec,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type);
|
||||
|
||||
/**
|
||||
* @child_offset_to_irq:
|
||||
|
|
@ -649,28 +659,14 @@ struct bgpio_pdata {
|
|||
|
||||
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
||||
|
||||
void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
|
||||
int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
|
||||
union gpio_irq_fwspec *gfwspec,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type);
|
||||
int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
|
||||
union gpio_irq_fwspec *gfwspec,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type);
|
||||
void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type);
|
||||
|
||||
#else
|
||||
|
||||
static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
|
||||
unsigned int parent_hwirq,
|
||||
unsigned int parent_type)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
|
||||
|
||||
|
|
|
|||
|
|
@ -151,7 +151,9 @@ struct irq_common_data {
|
|||
#endif
|
||||
void *handler_data;
|
||||
struct msi_desc *msi_desc;
|
||||
#ifdef CONFIG_SMP
|
||||
cpumask_var_t affinity;
|
||||
#endif
|
||||
#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
||||
cpumask_var_t effective_affinity;
|
||||
#endif
|
||||
|
|
@ -879,21 +881,34 @@ static inline int irq_data_get_node(struct irq_data *d)
|
|||
return irq_common_data_get_node(d->common);
|
||||
}
|
||||
|
||||
static inline struct cpumask *irq_get_affinity_mask(int irq)
|
||||
static inline
|
||||
const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
return d->common->affinity;
|
||||
#else
|
||||
return cpumask_of(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void irq_data_update_affinity(struct irq_data *d,
|
||||
const struct cpumask *m)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
cpumask_copy(d->common->affinity, m);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline const struct cpumask *irq_get_affinity_mask(int irq)
|
||||
{
|
||||
struct irq_data *d = irq_get_irq_data(irq);
|
||||
|
||||
return d ? d->common->affinity : NULL;
|
||||
}
|
||||
|
||||
static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
|
||||
{
|
||||
return d->common->affinity;
|
||||
return d ? irq_data_get_affinity_mask(d) : NULL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
||||
static inline
|
||||
struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
|
||||
const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
|
||||
{
|
||||
return d->common->effective_affinity;
|
||||
}
|
||||
|
|
@ -908,13 +923,14 @@ static inline void irq_data_update_effective_affinity(struct irq_data *d,
|
|||
{
|
||||
}
|
||||
static inline
|
||||
struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
|
||||
const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
|
||||
{
|
||||
return d->common->affinity;
|
||||
return irq_data_get_affinity_mask(d);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
|
||||
static inline
|
||||
const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
|
||||
{
|
||||
struct irq_data *d = irq_get_irq_data(irq);
|
||||
|
||||
|
|
@ -1121,6 +1137,7 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on);
|
|||
/* Setup functions for irq_chip_generic */
|
||||
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw_irq);
|
||||
void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
|
||||
struct irq_chip_generic *
|
||||
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
|
||||
void __iomem *reg_base, irq_flow_handler_t handler);
|
||||
|
|
|
|||
|
|
@ -4,4 +4,7 @@
|
|||
|
||||
extern struct irq_chip icu_irq_chip;
|
||||
|
||||
extern void icu_init_irq(void);
|
||||
extern void mmp2_init_icu(void);
|
||||
|
||||
#endif /* __IRQCHIP_MMP_H */
|
||||
|
|
|
|||
|
|
@ -209,14 +209,15 @@ static inline void irq_set_handler_locked(struct irq_data *data,
|
|||
* Must be called with irq_desc locked and valid parameters.
|
||||
*/
|
||||
static inline void
|
||||
irq_set_chip_handler_name_locked(struct irq_data *data, struct irq_chip *chip,
|
||||
irq_set_chip_handler_name_locked(struct irq_data *data,
|
||||
const struct irq_chip *chip,
|
||||
irq_flow_handler_t handler, const char *name)
|
||||
{
|
||||
struct irq_desc *desc = irq_data_to_desc(data);
|
||||
|
||||
desc->handle_irq = handler;
|
||||
desc->name = name;
|
||||
data->chip = chip;
|
||||
data->chip = (struct irq_chip *)chip;
|
||||
}
|
||||
|
||||
bool irq_check_status_bit(unsigned int irq, unsigned int bitmask);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue