Immutable branch for both MFD and EXTCON tree.
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This commit is contained in:
Lee Jones
commit
8848ff4206
52 changed files with 2659 additions and 146 deletions
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@ -5,12 +5,19 @@
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|||
#include <linux/types.h>
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extern u16 const crc_ccitt_table[256];
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extern u16 const crc_ccitt_false_table[256];
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extern u16 crc_ccitt(u16 crc, const u8 *buffer, size_t len);
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extern u16 crc_ccitt_false(u16 crc, const u8 *buffer, size_t len);
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static inline u16 crc_ccitt_byte(u16 crc, const u8 c)
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{
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return (crc >> 8) ^ crc_ccitt_table[(crc ^ c) & 0xff];
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}
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static inline u16 crc_ccitt_false_byte(u16 crc, const u8 c)
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{
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return (crc << 8) ^ crc_ccitt_false_table[(crc >> 8) ^ c];
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}
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#endif /* _LINUX_CRC_CCITT_H */
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@ -645,11 +645,6 @@ struct axp20x_dev {
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const struct regmap_irq_chip *regmap_irq_chip;
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};
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struct axp288_extcon_pdata {
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/* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */
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struct gpio_desc *gpio_mux_cntl;
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};
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/* generic helper function for reading 9-16 bit wide regs */
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static inline int axp20x_read_variable_width(struct regmap *regmap,
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unsigned int reg, unsigned int width)
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@ -322,6 +322,10 @@ extern struct attribute_group cros_ec_attr_group;
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extern struct attribute_group cros_ec_lightbar_attr_group;
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extern struct attribute_group cros_ec_vbc_attr_group;
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/* debugfs stuff */
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int cros_ec_debugfs_init(struct cros_ec_dev *ec);
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void cros_ec_debugfs_remove(struct cros_ec_dev *ec);
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/* ACPI GPE handler */
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#ifdef CONFIG_ACPI
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|
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@ -2904,16 +2904,33 @@ enum usb_pd_control_mux {
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USB_PD_CTRL_MUX_AUTO = 5,
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};
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enum usb_pd_control_swap {
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USB_PD_CTRL_SWAP_NONE = 0,
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USB_PD_CTRL_SWAP_DATA = 1,
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USB_PD_CTRL_SWAP_POWER = 2,
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USB_PD_CTRL_SWAP_VCONN = 3,
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USB_PD_CTRL_SWAP_COUNT
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};
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struct ec_params_usb_pd_control {
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uint8_t port;
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uint8_t role;
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uint8_t mux;
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uint8_t swap;
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} __packed;
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#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */
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#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */
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#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */
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#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
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#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
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#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
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#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
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#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
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#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
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#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */
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struct ec_response_usb_pd_control_v1 {
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uint8_t enabled;
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uint8_t role;
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60
include/linux/mfd/rave-sp.h
Normal file
60
include/linux/mfd/rave-sp.h
Normal file
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Core definitions for RAVE SP MFD driver.
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*
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* Copyright (C) 2017 Zodiac Inflight Innovations
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*/
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#ifndef _LINUX_RAVE_SP_H_
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#define _LINUX_RAVE_SP_H_
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#include <linux/notifier.h>
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enum rave_sp_command {
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RAVE_SP_CMD_GET_FIRMWARE_VERSION = 0x20,
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RAVE_SP_CMD_GET_BOOTLOADER_VERSION = 0x21,
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RAVE_SP_CMD_BOOT_SOURCE = 0x26,
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RAVE_SP_CMD_GET_BOARD_COPPER_REV = 0x2B,
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RAVE_SP_CMD_GET_GPIO_STATE = 0x2F,
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RAVE_SP_CMD_STATUS = 0xA0,
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RAVE_SP_CMD_SW_WDT = 0xA1,
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RAVE_SP_CMD_PET_WDT = 0xA2,
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RAVE_SP_CMD_RESET = 0xA7,
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RAVE_SP_CMD_RESET_REASON = 0xA8,
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RAVE_SP_CMD_REQ_COPPER_REV = 0xB6,
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RAVE_SP_CMD_GET_I2C_DEVICE_STATUS = 0xBA,
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RAVE_SP_CMD_GET_SP_SILICON_REV = 0xB9,
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RAVE_SP_CMD_CONTROL_EVENTS = 0xBB,
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RAVE_SP_EVNT_BASE = 0xE0,
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};
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struct rave_sp;
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static inline unsigned long rave_sp_action_pack(u8 event, u8 value)
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{
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return ((unsigned long)value << 8) | event;
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}
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static inline u8 rave_sp_action_unpack_event(unsigned long action)
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{
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return action;
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}
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static inline u8 rave_sp_action_unpack_value(unsigned long action)
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{
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return action >> 8;
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}
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int rave_sp_exec(struct rave_sp *sp,
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void *__data, size_t data_size,
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void *reply_data, size_t reply_data_size);
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struct device;
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int devm_rave_sp_register_event_notifier(struct device *dev,
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struct notifier_block *nb);
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#endif /* _LINUX_RAVE_SP_H_ */
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@ -24,7 +24,7 @@
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/mfd/rtsx_common.h>
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#include <linux/rtsx_common.h>
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#define MAX_RW_REG_CNT 1024
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@ -203,6 +203,7 @@
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#define SD_DDR_MODE 0x04
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#define SD_30_MODE 0x08
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#define SD_CLK_DIVIDE_MASK 0xC0
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#define SD_MODE_SELECT_MASK 0x0C
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#define SD_CFG2 0xFDA1
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#define SD_CALCULATE_CRC7 0x00
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#define SD_NO_CALCULATE_CRC7 0x80
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@ -226,6 +227,7 @@
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#define SD_RSP_TYPE_R6 0x01
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#define SD_RSP_TYPE_R7 0x01
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#define SD_CFG3 0xFDA2
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#define SD30_CLK_END_EN 0x10
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#define SD_RSP_80CLK_TIMEOUT_EN 0x01
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#define SD_STAT1 0xFDA3
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@ -309,6 +311,12 @@
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#define SD_DATA_STATE 0xFDB6
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#define SD_DATA_IDLE 0x80
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#define REG_SD_STOP_SDCLK_CFG 0xFDB8
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#define SD30_CLK_STOP_CFG_EN 0x04
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#define SD30_CLK_STOP_CFG1 0x02
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#define SD30_CLK_STOP_CFG0 0x01
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#define REG_PRE_RW_MODE 0xFD70
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#define EN_INFINITE_MODE 0x01
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#define SRCTL 0xFC13
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@ -434,6 +442,7 @@
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#define CARD_CLK_EN 0xFD69
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#define SD_CLK_EN 0x04
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#define MS_CLK_EN 0x08
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#define SD40_CLK_EN 0x10
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#define SDIO_CTRL 0xFD6B
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#define CD_PAD_CTL 0xFD73
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#define CD_DISABLE_MASK 0x07
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@ -453,8 +462,8 @@
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#define FPDCTL 0xFC00
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#define SSC_POWER_DOWN 0x01
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#define SD_OC_POWER_DOWN 0x02
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#define ALL_POWER_DOWN 0x07
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#define OC_POWER_DOWN 0x06
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#define ALL_POWER_DOWN 0x03
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#define OC_POWER_DOWN 0x02
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#define PDINFO 0xFC01
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#define CLK_CTL 0xFC02
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@ -490,6 +499,9 @@
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#define FPGA_PULL_CTL 0xFC1D
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#define OLT_LED_CTL 0xFC1E
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#define LED_SHINE_MASK 0x08
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#define LED_SHINE_EN 0x08
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#define LED_SHINE_DISABLE 0x00
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#define GPIO_CTL 0xFC1F
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#define LDO_CTL 0xFC1E
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@ -511,7 +523,11 @@
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#define BPP_LDO_ON 0x00
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#define BPP_LDO_SUSPEND 0x02
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#define BPP_LDO_OFF 0x03
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#define EFUSE_CTL 0xFC30
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#define EFUSE_ADD 0xFC31
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#define SYS_VER 0xFC32
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#define EFUSE_DATAL 0xFC34
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#define EFUSE_DATAH 0xFC35
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#define CARD_PULL_CTL1 0xFD60
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#define CARD_PULL_CTL2 0xFD61
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@ -553,6 +569,9 @@
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#define RBBC1 0xFE2F
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#define RBDAT 0xFE30
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#define RBCTL 0xFE34
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#define U_AUTO_DMA_EN_MASK 0x20
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#define U_AUTO_DMA_DISABLE 0x00
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#define RB_FLUSH 0x80
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#define CFGADDR0 0xFE35
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#define CFGADDR1 0xFE36
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#define CFGDATA0 0xFE37
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@ -581,6 +600,8 @@
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#define LTR_LATENCY_MODE_HW 0
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#define LTR_LATENCY_MODE_SW BIT(6)
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#define OBFF_CFG 0xFE4C
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#define OBFF_EN_MASK 0x03
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#define OBFF_DISABLE 0x00
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#define CDRESUMECTL 0xFE52
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#define WAKE_SEL_CTL 0xFE54
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@ -595,6 +616,7 @@
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#define FORCE_ASPM_L0_EN 0x01
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#define FORCE_ASPM_NO_ASPM 0x00
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#define PM_CLK_FORCE_CTL 0xFE58
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#define CLK_PM_EN 0x01
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#define FUNC_FORCE_CTL 0xFE59
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#define FUNC_FORCE_UPME_XMT_DBG 0x02
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#define PERST_GLITCH_WIDTH 0xFE5C
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@ -620,14 +642,23 @@
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#define LDO_PWR_SEL 0xFE78
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#define L1SUB_CONFIG1 0xFE8D
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#define AUX_CLK_ACTIVE_SEL_MASK 0x01
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#define MAC_CKSW_DONE 0x00
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#define L1SUB_CONFIG2 0xFE8E
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#define L1SUB_AUTO_CFG 0x02
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#define L1SUB_CONFIG3 0xFE8F
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#define L1OFF_MBIAS2_EN_5250 BIT(7)
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#define DUMMY_REG_RESET_0 0xFE90
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#define IC_VERSION_MASK 0x0F
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#define REG_VREF 0xFE97
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#define PWD_SUSPND_EN 0x10
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#define RTS5260_DMA_RST_CTL_0 0xFEBF
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#define RTS5260_DMA_RST 0x80
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#define RTS5260_ADMA3_RST 0x40
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#define AUTOLOAD_CFG_BASE 0xFF00
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#define RELINK_TIME_MASK 0x01
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#define PETXCFG 0xFF03
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#define FORCE_CLKREQ_DELINK_MASK BIT(7)
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#define FORCE_CLKREQ_LOW 0x80
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|
|
@ -667,15 +698,24 @@
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#define LDO_DV18_CFG 0xFF70
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#define LDO_DV18_SR_MASK 0xC0
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#define LDO_DV18_SR_DF 0x40
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#define DV331812_MASK 0x70
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#define DV331812_33 0x70
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#define DV331812_17 0x30
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|
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#define LDO_CONFIG2 0xFF71
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#define LDO_D3318_MASK 0x07
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#define LDO_D3318_33V 0x07
|
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#define LDO_D3318_18V 0x02
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#define DV331812_VDD1 0x04
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#define DV331812_POWERON 0x08
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#define DV331812_POWEROFF 0x00
|
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|
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#define LDO_VCC_CFG0 0xFF72
|
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#define LDO_VCC_LMTVTH_MASK 0x30
|
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#define LDO_VCC_LMTVTH_2A 0x10
|
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/*RTS5260*/
|
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#define RTS5260_DVCC_TUNE_MASK 0x70
|
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#define RTS5260_DVCC_33 0x70
|
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|
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#define LDO_VCC_CFG1 0xFF73
|
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#define LDO_VCC_REF_TUNE_MASK 0x30
|
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|
|
@ -684,6 +724,10 @@
|
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#define LDO_VCC_1V8 0x04
|
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#define LDO_VCC_3V3 0x07
|
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#define LDO_VCC_LMT_EN 0x08
|
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/*RTS5260*/
|
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#define LDO_POW_SDVDD1_MASK 0x08
|
||||
#define LDO_POW_SDVDD1_ON 0x08
|
||||
#define LDO_POW_SDVDD1_OFF 0x00
|
||||
|
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#define LDO_VIO_CFG 0xFF75
|
||||
#define LDO_VIO_SR_MASK 0xC0
|
||||
|
|
@ -711,6 +755,160 @@
|
|||
#define SD_VIO_LDO_1V8 0x40
|
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#define SD_VIO_LDO_3V3 0x70
|
||||
|
||||
#define RTS5260_AUTOLOAD_CFG4 0xFF7F
|
||||
#define RTS5260_MIMO_DISABLE 0x8A
|
||||
|
||||
#define RTS5260_REG_GPIO_CTL0 0xFC1A
|
||||
#define RTS5260_REG_GPIO_MASK 0x01
|
||||
#define RTS5260_REG_GPIO_ON 0x01
|
||||
#define RTS5260_REG_GPIO_OFF 0x00
|
||||
|
||||
#define PWR_GLOBAL_CTRL 0xF200
|
||||
#define PCIE_L1_2_EN 0x0C
|
||||
#define PCIE_L1_1_EN 0x0A
|
||||
#define PCIE_L1_0_EN 0x09
|
||||
#define PWR_FE_CTL 0xF201
|
||||
#define PCIE_L1_2_PD_FE_EN 0x0C
|
||||
#define PCIE_L1_1_PD_FE_EN 0x0A
|
||||
#define PCIE_L1_0_PD_FE_EN 0x09
|
||||
#define CFG_PCIE_APHY_OFF_0 0xF204
|
||||
#define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
|
||||
#define CFG_PCIE_APHY_OFF_1 0xF205
|
||||
#define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
|
||||
#define CFG_PCIE_APHY_OFF_2 0xF206
|
||||
#define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
|
||||
#define CFG_PCIE_APHY_OFF_3 0xF207
|
||||
#define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
|
||||
#define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
|
||||
#define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
|
||||
#define CFG_L1_0_SYS_RET_VALUE 0xF210
|
||||
#define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
|
||||
#define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
|
||||
#define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
|
||||
#define CFG_LP_FPWM_VALUE 0xF219
|
||||
#define CFG_LP_FPWM_VALUE_DEFAULT 0x18
|
||||
#define PWC_CDR 0xF253
|
||||
#define PWC_CDR_DEFAULT 0x03
|
||||
#define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
|
||||
#define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
|
||||
|
||||
/* OCPCTL */
|
||||
#define SD_DETECT_EN 0x08
|
||||
#define SD_OCP_INT_EN 0x04
|
||||
#define SD_OCP_INT_CLR 0x02
|
||||
#define SD_OC_CLR 0x01
|
||||
|
||||
#define SDVIO_DETECT_EN (1 << 7)
|
||||
#define SDVIO_OCP_INT_EN (1 << 6)
|
||||
#define SDVIO_OCP_INT_CLR (1 << 5)
|
||||
#define SDVIO_OC_CLR (1 << 4)
|
||||
|
||||
/* OCPSTAT */
|
||||
#define SD_OCP_DETECT 0x08
|
||||
#define SD_OC_NOW 0x04
|
||||
#define SD_OC_EVER 0x02
|
||||
|
||||
#define SDVIO_OC_NOW (1 << 6)
|
||||
#define SDVIO_OC_EVER (1 << 5)
|
||||
|
||||
#define REG_OCPCTL 0xFD6A
|
||||
#define REG_OCPSTAT 0xFD6E
|
||||
#define REG_OCPGLITCH 0xFD6C
|
||||
#define REG_OCPPARA1 0xFD6B
|
||||
#define REG_OCPPARA2 0xFD6D
|
||||
|
||||
/* rts5260 DV3318 OCP-related registers */
|
||||
#define REG_DV3318_OCPCTL 0xFD89
|
||||
#define DV3318_OCP_TIME_MASK 0xF0
|
||||
#define DV3318_DETECT_EN 0x08
|
||||
#define DV3318_OCP_INT_EN 0x04
|
||||
#define DV3318_OCP_INT_CLR 0x02
|
||||
#define DV3318_OCP_CLR 0x01
|
||||
|
||||
#define REG_DV3318_OCPSTAT 0xFD8A
|
||||
#define DV3318_OCP_GlITCH_TIME_MASK 0xF0
|
||||
#define DV3318_OCP_DETECT 0x08
|
||||
#define DV3318_OCP_NOW 0x04
|
||||
#define DV3318_OCP_EVER 0x02
|
||||
|
||||
#define SD_OCP_GLITCH_MASK 0x0F
|
||||
|
||||
/* OCPPARA1 */
|
||||
#define SDVIO_OCP_TIME_60 0x00
|
||||
#define SDVIO_OCP_TIME_100 0x10
|
||||
#define SDVIO_OCP_TIME_200 0x20
|
||||
#define SDVIO_OCP_TIME_400 0x30
|
||||
#define SDVIO_OCP_TIME_600 0x40
|
||||
#define SDVIO_OCP_TIME_800 0x50
|
||||
#define SDVIO_OCP_TIME_1100 0x60
|
||||
#define SDVIO_OCP_TIME_MASK 0x70
|
||||
|
||||
#define SD_OCP_TIME_60 0x00
|
||||
#define SD_OCP_TIME_100 0x01
|
||||
#define SD_OCP_TIME_200 0x02
|
||||
#define SD_OCP_TIME_400 0x03
|
||||
#define SD_OCP_TIME_600 0x04
|
||||
#define SD_OCP_TIME_800 0x05
|
||||
#define SD_OCP_TIME_1100 0x06
|
||||
#define SD_OCP_TIME_MASK 0x07
|
||||
|
||||
/* OCPPARA2 */
|
||||
#define SDVIO_OCP_THD_190 0x00
|
||||
#define SDVIO_OCP_THD_250 0x10
|
||||
#define SDVIO_OCP_THD_320 0x20
|
||||
#define SDVIO_OCP_THD_380 0x30
|
||||
#define SDVIO_OCP_THD_440 0x40
|
||||
#define SDVIO_OCP_THD_500 0x50
|
||||
#define SDVIO_OCP_THD_570 0x60
|
||||
#define SDVIO_OCP_THD_630 0x70
|
||||
#define SDVIO_OCP_THD_MASK 0x70
|
||||
|
||||
#define SD_OCP_THD_450 0x00
|
||||
#define SD_OCP_THD_550 0x01
|
||||
#define SD_OCP_THD_650 0x02
|
||||
#define SD_OCP_THD_750 0x03
|
||||
#define SD_OCP_THD_850 0x04
|
||||
#define SD_OCP_THD_950 0x05
|
||||
#define SD_OCP_THD_1050 0x06
|
||||
#define SD_OCP_THD_1150 0x07
|
||||
#define SD_OCP_THD_MASK 0x07
|
||||
|
||||
#define SDVIO_OCP_GLITCH_MASK 0xF0
|
||||
#define SDVIO_OCP_GLITCH_NONE 0x00
|
||||
#define SDVIO_OCP_GLITCH_50U 0x10
|
||||
#define SDVIO_OCP_GLITCH_100U 0x20
|
||||
#define SDVIO_OCP_GLITCH_200U 0x30
|
||||
#define SDVIO_OCP_GLITCH_600U 0x40
|
||||
#define SDVIO_OCP_GLITCH_800U 0x50
|
||||
#define SDVIO_OCP_GLITCH_1M 0x60
|
||||
#define SDVIO_OCP_GLITCH_2M 0x70
|
||||
#define SDVIO_OCP_GLITCH_3M 0x80
|
||||
#define SDVIO_OCP_GLITCH_4M 0x90
|
||||
#define SDVIO_OCP_GLIVCH_5M 0xA0
|
||||
#define SDVIO_OCP_GLITCH_6M 0xB0
|
||||
#define SDVIO_OCP_GLITCH_7M 0xC0
|
||||
#define SDVIO_OCP_GLITCH_8M 0xD0
|
||||
#define SDVIO_OCP_GLITCH_9M 0xE0
|
||||
#define SDVIO_OCP_GLITCH_10M 0xF0
|
||||
|
||||
#define SD_OCP_GLITCH_MASK 0x0F
|
||||
#define SD_OCP_GLITCH_NONE 0x00
|
||||
#define SD_OCP_GLITCH_50U 0x01
|
||||
#define SD_OCP_GLITCH_100U 0x02
|
||||
#define SD_OCP_GLITCH_200U 0x03
|
||||
#define SD_OCP_GLITCH_600U 0x04
|
||||
#define SD_OCP_GLITCH_800U 0x05
|
||||
#define SD_OCP_GLITCH_1M 0x06
|
||||
#define SD_OCP_GLITCH_2M 0x07
|
||||
#define SD_OCP_GLITCH_3M 0x08
|
||||
#define SD_OCP_GLITCH_4M 0x09
|
||||
#define SD_OCP_GLIVCH_5M 0x0A
|
||||
#define SD_OCP_GLITCH_6M 0x0B
|
||||
#define SD_OCP_GLITCH_7M 0x0C
|
||||
#define SD_OCP_GLITCH_8M 0x0D
|
||||
#define SD_OCP_GLITCH_9M 0x0E
|
||||
#define SD_OCP_GLITCH_10M 0x0F
|
||||
|
||||
/* Phy register */
|
||||
#define PHY_PCR 0x00
|
||||
#define PHY_PCR_FORCE_CODE 0xB000
|
||||
|
|
@ -857,6 +1055,7 @@
|
|||
|
||||
#define PCR_ASPM_SETTING_REG1 0x160
|
||||
#define PCR_ASPM_SETTING_REG2 0x168
|
||||
#define PCR_ASPM_SETTING_5260 0x178
|
||||
|
||||
#define PCR_SETTING_REG1 0x724
|
||||
#define PCR_SETTING_REG2 0x814
|
||||
|
|
@ -890,6 +1089,7 @@ struct pcr_ops {
|
|||
int (*conv_clk_and_div_n)(int clk, int dir);
|
||||
void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
|
||||
void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
|
||||
void (*stop_cmd)(struct rtsx_pcr *pcr);
|
||||
|
||||
void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
|
||||
int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
|
||||
|
|
@ -897,6 +1097,12 @@ struct pcr_ops {
|
|||
void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
|
||||
void (*full_on)(struct rtsx_pcr *pcr);
|
||||
void (*power_saving)(struct rtsx_pcr *pcr);
|
||||
void (*enable_ocp)(struct rtsx_pcr *pcr);
|
||||
void (*disable_ocp)(struct rtsx_pcr *pcr);
|
||||
void (*init_ocp)(struct rtsx_pcr *pcr);
|
||||
void (*process_ocp)(struct rtsx_pcr *pcr);
|
||||
int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
|
||||
void (*clear_ocpstat)(struct rtsx_pcr *pcr);
|
||||
};
|
||||
|
||||
enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
|
||||
|
|
@ -935,6 +1141,9 @@ enum dev_aspm_mode {
|
|||
* @l1_snooze_delay: l1 snooze delay
|
||||
* @ltr_l1off_sspwrgate: ltr l1off sspwrgate
|
||||
* @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
|
||||
* @ocp_en: enable ocp flag
|
||||
* @sd_400mA_ocp_thd: 400mA ocp thd
|
||||
* @sd_800mA_ocp_thd: 800mA ocp thd
|
||||
*/
|
||||
struct rtsx_cr_option {
|
||||
u32 dev_flags;
|
||||
|
|
@ -949,6 +1158,19 @@ struct rtsx_cr_option {
|
|||
u32 l1_snooze_delay;
|
||||
u8 ltr_l1off_sspwrgate;
|
||||
u8 ltr_l1off_snooze_sspwrgate;
|
||||
bool ocp_en;
|
||||
u8 sd_400mA_ocp_thd;
|
||||
u8 sd_800mA_ocp_thd;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct rtsx_hw_param - card reader hardware param
|
||||
* @interrupt_en: indicate which interrutp enable
|
||||
* @ocp_glitch: ocp glitch time
|
||||
*/
|
||||
struct rtsx_hw_param {
|
||||
u32 interrupt_en;
|
||||
u8 ocp_glitch;
|
||||
};
|
||||
|
||||
#define rtsx_set_dev_flag(cr, flag) \
|
||||
|
|
@ -963,6 +1185,7 @@ struct rtsx_pcr {
|
|||
unsigned int id;
|
||||
int pcie_cap;
|
||||
struct rtsx_cr_option option;
|
||||
struct rtsx_hw_param hw_param;
|
||||
|
||||
/* pci resources */
|
||||
unsigned long addr;
|
||||
|
|
@ -1042,12 +1265,15 @@ struct rtsx_pcr {
|
|||
struct rtsx_slot *slots;
|
||||
|
||||
u8 dma_error_count;
|
||||
u8 ocp_stat;
|
||||
u8 ocp_stat2;
|
||||
};
|
||||
|
||||
#define PID_524A 0x524A
|
||||
#define PID_5249 0x5249
|
||||
#define PID_5250 0x5250
|
||||
#define PID_5249 0x5249
|
||||
#define PID_5250 0x5250
|
||||
#define PID_525A 0x525A
|
||||
#define PID_5260 0x5260
|
||||
|
||||
#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
|
||||
#define PCI_VID(pcr) ((pcr)->pci->vendor)
|
||||
|
|
@ -193,6 +193,7 @@ static inline int serdev_controller_receive_buf(struct serdev_controller *ctrl,
|
|||
|
||||
int serdev_device_open(struct serdev_device *);
|
||||
void serdev_device_close(struct serdev_device *);
|
||||
int devm_serdev_device_open(struct device *, struct serdev_device *);
|
||||
unsigned int serdev_device_set_baudrate(struct serdev_device *, unsigned int);
|
||||
void serdev_device_set_flow_control(struct serdev_device *, bool);
|
||||
int serdev_device_write_buf(struct serdev_device *, const unsigned char *, size_t);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue