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Qualcomm ARM64 DT fixes for v5.19

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This removes duplicate includes in the sc7180-trogdor files, which
 accidentally ended up disabling nodes intended to be enabled.
 
 It corrects identifiers for CPU6/7 on MSM8994. On SM8450 the UFS node's
 interconnects property is updated to match the #interconnect-cells,
 avoiding sync_state issues and the GIC ITS is defined, to correct the
 references from the PCIe nodes. On SDM845 the display subsystem's AHB
 clock is corrected and on msm8992 devices, the supplies for lvs 1 and 2
 are correctly specified.
 
 Lastly, a welcome addition of Konrad as reviewer for the Qualcomm SoC.
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Merge tag 'qcom-arm64-fixes-for-5.19' into arm64-for-5.20

This merges the 'qcom-arm64-fixes-for-5.19' tag into arm64-for-5.20 to
handle the merge conflict related to the header file changes in
sc7180-trogdor.
This commit is contained in:
Bjorn Andersson 2022-07-02 22:03:46 -05:00
commit 817c2f3519
8 changed files with 20 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

1
MAINTAINERS
View file

@ -2537,6 +2537,7 @@ W: http://www.armlinux.org.uk/
ARM/QUALCOMM SUPPORT
M: Andy Gross <agross@kernel.org>
M: Bjorn Andersson <bjorn.andersson@linaro.org>
R: Konrad Dybcio <konrad.dybcio@somainline.org>
L: linux-arm-msm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git

2
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
View file

@ -74,7 +74,7 @@
vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>;
vdd_lvs1_2-supply = <&pm8994_s4>;
/* S1, S2, S6 and S12 are managed by RPMPD */

2
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View file

@ -169,7 +169,7 @@
vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>;
vdd_lvs1_2-supply = <&pm8994_s4>;
/* S1, S2, S6 and S12 are managed by RPMPD */

4
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file

@ -100,7 +100,7 @@
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
@ -108,7 +108,7 @@
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View file

@ -5,7 +5,7 @@
* Copyright 2021 Google LLC.
*/
#include "sc7180-trogdor.dtsi"
/* This file must be included after sc7180-trogdor.dtsi */
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View file

@ -5,7 +5,7 @@
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor.dtsi"
/* This file must be included after sc7180-trogdor.dtsi */
#include <arm/cros-ec-keyboard.dtsi>
&ap_sar_sensor {

2
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -4244,7 +4244,7 @@
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";

14
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file

@ -2872,6 +2872,16 @@
reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
<0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@17140000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x17140000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
};
timer@17420000 {
@ -3056,8 +3066,8 @@
iommus = <&apps_smmu 0xe0 0x0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names =
"core_clk",