Char/Misc driver patches for 3.9-rc1
Here's the big char/misc driver patches for 3.9-rc1. Nothing major here, just lots of different driver updates (mei, hyperv, ipack, extcon, vmci, etc.). All of these have been in the linux-next tree for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iEYEABECAAYFAlEmZJgACgkQMUfUDdst+ymhZgCgo2dn37r9uMCwgTSpxSq92Je5 x8kAnRF1UnD6ZvySRIlLUBV5LW1YgFnK =i5HH -----END PGP SIGNATURE----- Merge tag 'char-misc-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver patches from Greg Kroah-Hartman: "Here's the big char/misc driver patches for 3.9-rc1. Nothing major here, just lots of different driver updates (mei, hyperv, ipack, extcon, vmci, etc.). All of these have been in the linux-next tree for a while." * tag 'char-misc-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (209 commits) w1: w1_therm: Add force-pullup option for "broken" sensors w1: ds2482: Added 1-Wire pull-up support to the driver vme: add missing put_device() after device_register() fails extcon: max8997: Use workqueue to check cable state after completing boot of platform extcon: max8997: Set default UART/USB path on probe extcon: max8997: Consolidate duplicate code for checking ADC/CHG cable type extcon: max8997: Set default of ADC debounce time during initialization extcon: max8997: Remove duplicate code related to set H/W line path extcon: max8997: Move defined constant to header file extcon: max77693: Make max77693_extcon_cable static extcon: max8997: Remove unreachable code extcon: max8997: Make max8997_extcon_cable static extcon: max77693: Remove unnecessary goto statement to improve readability extcon: max77693: Convert to devm_input_allocate_device() extcon: gpio: Rename filename of extcon-gpio.c according to kernel naming style CREDITS: update email and address of Harald Hoyer extcon: arizona: Use MICDET for final microphone identification extcon: arizona: Always take the first HPDET reading as the final one extcon: arizona: Clear _trig_sts bits after jack detection extcon: arizona: Don't HPDET magic when headphones are enabled ...
This commit is contained in:
Linus Torvalds
commit
7ed214ac20
107 changed files with 20759 additions and 4125 deletions
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@ -75,8 +75,10 @@ enum arizona_type {
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#define ARIZONA_IRQ_DCS_HP_DONE 47
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#define ARIZONA_IRQ_FLL2_CLOCK_OK 48
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#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
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#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
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#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
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#define ARIZONA_NUM_IRQ 50
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#define ARIZONA_NUM_IRQ 52
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struct snd_soc_dapm_context;
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@ -105,9 +105,30 @@ struct arizona_pdata {
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*/
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int max_channels_clocked[ARIZONA_MAX_AIF];
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/** GPIO5 is used for jack detection */
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bool jd_gpio5;
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/** Use the headphone detect circuit to identify the accessory */
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bool hpdet_acc_id;
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/** GPIO used for mic isolation with HPDET */
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int hpdet_id_gpio;
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/** GPIO for mic detection polarity */
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int micd_pol_gpio;
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/** Mic detect ramp rate */
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int micd_bias_start_time;
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/** Mic detect sample rate */
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int micd_rate;
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/** Mic detect debounce level */
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int micd_dbtime;
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/** Force MICBIAS on for mic detect */
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bool micd_force_micbias;
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/** Headset polarity configurations */
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struct arizona_micd_config *micd_configs;
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int num_micd_configs;
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@ -119,6 +119,8 @@
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#define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
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#define ARIZONA_HEADPHONE_DETECT_1 0x29B
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#define ARIZONA_HEADPHONE_DETECT_2 0x29C
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#define ARIZONA_HP_DACVAL 0x29F
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#define ARIZONA_MICD_CLAMP_CONTROL 0x2A2
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#define ARIZONA_MIC_DETECT_1 0x2A3
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#define ARIZONA_MIC_DETECT_2 0x2A4
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#define ARIZONA_MIC_DETECT_3 0x2A5
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@ -1194,6 +1196,14 @@
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/*
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* R64 (0x40) - Wake control
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*/
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#define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */
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#define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */
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#define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */
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#define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */
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#define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */
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#define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */
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#define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */
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#define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */
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#define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
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#define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
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#define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
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@ -2035,6 +2045,9 @@
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/*
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* R667 (0x29B) - Headphone Detect 1
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*/
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#define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */
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#define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */
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#define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */
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#define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
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#define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
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#define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
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@ -2069,6 +2082,21 @@
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#define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
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#define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
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#define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */
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#define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */
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#define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */
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#define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */
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#define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */
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#define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */
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#define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */
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/*
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* R674 (0x2A2) - MICD clamp control
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*/
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#define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */
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#define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */
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#define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */
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/*
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* R675 (0x2A3) - Mic Detect 1
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*/
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@ -5239,6 +5267,14 @@
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/*
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* R3408 (0xD50) - AOD wkup and trig
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*/
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#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */
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#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */
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#define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
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#define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
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#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
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@ -5267,6 +5303,12 @@
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/*
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* R3409 (0xD51) - AOD IRQ1
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*/
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#define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */
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#define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */
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#define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */
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#define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
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#define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
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#define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
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@ -5295,6 +5337,12 @@
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/*
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* R3410 (0xD52) - AOD IRQ2
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*/
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#define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */
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#define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */
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#define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */
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#define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */
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#define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
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#define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
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#define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
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@ -5379,6 +5427,10 @@
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/*
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* R3413 (0xD55) - AOD IRQ Raw Status
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*/
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#define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */
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#define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */
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#define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */
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#define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */
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#define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
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#define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
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#define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
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@ -5395,6 +5447,10 @@
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/*
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* R3414 (0xD56) - Jack detect debounce
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*/
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#define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */
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#define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */
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#define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */
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#define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */
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#define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
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#define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
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#define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
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@ -106,6 +106,92 @@ enum max77693_muic_reg {
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MAX77693_MUIC_REG_END,
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};
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/* MAX77693 MUIC - STATUS1~3 Register */
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#define STATUS1_ADC_SHIFT (0)
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#define STATUS1_ADCLOW_SHIFT (5)
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#define STATUS1_ADCERR_SHIFT (6)
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#define STATUS1_ADC1K_SHIFT (7)
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#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
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#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
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#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
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#define STATUS2_CHGTYP_SHIFT (0)
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#define STATUS2_CHGDETRUN_SHIFT (3)
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#define STATUS2_DCDTMR_SHIFT (4)
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#define STATUS2_DXOVP_SHIFT (5)
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#define STATUS2_VBVOLT_SHIFT (6)
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#define STATUS2_VIDRM_SHIFT (7)
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#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
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#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
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#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
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#define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
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#define STATUS3_OVP_SHIFT (2)
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#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
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/* MAX77693 CDETCTRL1~2 register */
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#define CDETCTRL1_CHGDETEN_SHIFT (0)
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#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
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#define CDETCTRL1_DCDEN_SHIFT (2)
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#define CDETCTRL1_DCD2SCT_SHIFT (3)
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#define CDETCTRL1_CDDELAY_SHIFT (4)
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#define CDETCTRL1_DCDCPL_SHIFT (5)
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#define CDETCTRL1_CDPDET_SHIFT (7)
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#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
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#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
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#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
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#define CDETCTRL2_VIDRMEN_SHIFT (1)
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#define CDETCTRL2_DXOVPEN_SHIFT (3)
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#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
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#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
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/* MAX77693 MUIC - CONTROL1~3 register */
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#define COMN1SW_SHIFT (0)
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#define COMP2SW_SHIFT (3)
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#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
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#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
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#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
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#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
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| (1 << COMN1SW_SHIFT))
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#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
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| (2 << COMN1SW_SHIFT))
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#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
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| (3 << COMN1SW_SHIFT))
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#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
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| (0 << COMN1SW_SHIFT))
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#define CONTROL2_LOWPWR_SHIFT (0)
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#define CONTROL2_ADCEN_SHIFT (1)
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#define CONTROL2_CPEN_SHIFT (2)
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#define CONTROL2_SFOUTASRT_SHIFT (3)
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#define CONTROL2_SFOUTORD_SHIFT (4)
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#define CONTROL2_ACCDET_SHIFT (5)
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#define CONTROL2_USBCPINT_SHIFT (6)
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#define CONTROL2_RCPS_SHIFT (7)
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#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
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#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
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#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
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#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
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#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
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#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
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#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
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#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
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#define CONTROL3_JIGSET_SHIFT (0)
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#define CONTROL3_BTLDSET_SHIFT (2)
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#define CONTROL3_ADCDBSET_SHIFT (4)
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#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
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#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
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#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
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/* Slave addr = 0x90: Haptic */
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enum max77693_haptic_reg {
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MAX77693_HAPTIC_REG_STATUS = 0x00,
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@ -38,6 +38,15 @@ struct max77693_reg_data {
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struct max77693_muic_platform_data {
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struct max77693_reg_data *init_data;
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int num_init_data;
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int detcable_delay_ms;
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/*
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* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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* h/w path of COMP2/COMN1 on CONTROL1 register.
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*/
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int path_usb;
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int path_uart;
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};
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struct max77693_platform_data {
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@ -194,6 +194,70 @@ enum max8997_muic_reg {
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MAX8997_MUIC_REG_END = 0xf,
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};
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/* MAX8997-MUIC STATUS1 register */
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#define STATUS1_ADC_SHIFT 0
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#define STATUS1_ADCLOW_SHIFT 5
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#define STATUS1_ADCERR_SHIFT 6
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#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
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#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
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/* MAX8997-MUIC STATUS2 register */
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#define STATUS2_CHGTYP_SHIFT 0
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#define STATUS2_CHGDETRUN_SHIFT 3
|
||||
#define STATUS2_DCDTMR_SHIFT 4
|
||||
#define STATUS2_DBCHG_SHIFT 5
|
||||
#define STATUS2_VBVOLT_SHIFT 6
|
||||
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
|
||||
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
|
||||
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
|
||||
#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
|
||||
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
|
||||
|
||||
/* MAX8997-MUIC STATUS3 register */
|
||||
#define STATUS3_OVP_SHIFT 2
|
||||
#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
|
||||
|
||||
/* MAX8997-MUIC CONTROL1 register */
|
||||
#define COMN1SW_SHIFT 0
|
||||
#define COMP2SW_SHIFT 3
|
||||
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
|
||||
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
|
||||
#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
|
||||
|
||||
#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
|
||||
| (1 << COMN1SW_SHIFT))
|
||||
#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
|
||||
| (2 << COMN1SW_SHIFT))
|
||||
#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
|
||||
| (3 << COMN1SW_SHIFT))
|
||||
#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
|
||||
| (0 << COMN1SW_SHIFT))
|
||||
|
||||
#define CONTROL2_LOWPWR_SHIFT (0)
|
||||
#define CONTROL2_ADCEN_SHIFT (1)
|
||||
#define CONTROL2_CPEN_SHIFT (2)
|
||||
#define CONTROL2_SFOUTASRT_SHIFT (3)
|
||||
#define CONTROL2_SFOUTORD_SHIFT (4)
|
||||
#define CONTROL2_ACCDET_SHIFT (5)
|
||||
#define CONTROL2_USBCPINT_SHIFT (6)
|
||||
#define CONTROL2_RCPS_SHIFT (7)
|
||||
#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
|
||||
#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
|
||||
#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
|
||||
#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
|
||||
#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
|
||||
#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
|
||||
#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
|
||||
#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
|
||||
|
||||
#define CONTROL3_JIGSET_SHIFT (0)
|
||||
#define CONTROL3_BTLDSET_SHIFT (2)
|
||||
#define CONTROL3_ADCDBSET_SHIFT (4)
|
||||
#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
|
||||
#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
|
||||
#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
|
||||
|
||||
enum max8997_haptic_reg {
|
||||
MAX8997_HAPTIC_REG_GENERAL = 0x00,
|
||||
MAX8997_HAPTIC_REG_CONF1 = 0x01,
|
||||
|
|
|
|||
|
|
@ -78,21 +78,6 @@ struct max8997_regulator_data {
|
|||
struct device_node *reg_node;
|
||||
};
|
||||
|
||||
enum max8997_muic_usb_type {
|
||||
MAX8997_USB_HOST,
|
||||
MAX8997_USB_DEVICE,
|
||||
};
|
||||
|
||||
enum max8997_muic_charger_type {
|
||||
MAX8997_CHARGER_TYPE_NONE = 0,
|
||||
MAX8997_CHARGER_TYPE_USB,
|
||||
MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT,
|
||||
MAX8997_CHARGER_TYPE_DEDICATED_CHG,
|
||||
MAX8997_CHARGER_TYPE_500MA,
|
||||
MAX8997_CHARGER_TYPE_1A,
|
||||
MAX8997_CHARGER_TYPE_DEAD_BATTERY = 7,
|
||||
};
|
||||
|
||||
struct max8997_muic_reg_data {
|
||||
u8 addr;
|
||||
u8 data;
|
||||
|
|
@ -107,6 +92,16 @@ struct max8997_muic_reg_data {
|
|||
struct max8997_muic_platform_data {
|
||||
struct max8997_muic_reg_data *init_data;
|
||||
int num_init_data;
|
||||
|
||||
/* Check cable state after certain delay */
|
||||
int detcable_delay_ms;
|
||||
|
||||
/*
|
||||
* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
|
||||
* h/w path of COMP2/COMN1 on CONTROL1 register.
|
||||
*/
|
||||
int path_usb;
|
||||
int path_uart;
|
||||
};
|
||||
|
||||
enum max8997_haptic_motor_type {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue