drm-misc-next for v5.16:
UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuXvWqAysSYEJGuVH/lWMcqZwE8MFAmFdfuwACgkQ/lWMcqZw E8OTgg/+Nmsqhj1tsbSCWF1yx81CXHVSOhExPaMl+GPs6+y+sZ+U2rN99dnbULvA U56eOmjc8FvgmK89BwhSYNt++QYIRRpzjBGlCYm4bwpgqFOmYsK+en35PYMwHdxM Ke8newhzqa6/detvjX52igddZzrBv1Cs8aXuV5rw7Dg0ivlSlQUV0MO8JYwCliWI arRT8bg7wzUzhyRZqwqOqKXjvRirqBlFjJmvfL0WgHevZbzYuXbn4eWCUgCVthMH pU9QgK6FMW912pBxVppDO2aTDmNvqwj1BsB3RFfRuqS/JJ4s/gf39JxsipnI+/qn kPxZVFzzonR8Nl6h9sPi1jZrcVDCBebFgyG8hSgIVb/09U7AVYomtP18VKeh8yCy Pp4iQINqOcyMPmXKF491LIL92dcXZAIRaRQFKc/ZSHcfIDA7ZB1+7zf1ixBjlxjP GqtjLbmPspI2DzBRlTFEdf58jvX70E5nFYdQyYcy3VprJHuqEgL5PKz2Xcnve6R0 dEkGA2vMrGtb23YyjbFTNfkdvg9WYXze9HbQLt7kc8mI77TugkG0/rCcwv5pEEu3 WSwqMeb+5H+7va4AI715MoXbxgnCba2zPTUm1s8kSqTK0Oighc/vWcnnJ4iVuEGE 8Xt8AIIYUtccufR6ujucVUh7nju2ZOnFE7S92LybnGnByAIADfM= =qxpr -----END PGP SIGNATURE----- Merge tag 'drm-misc-next-2021-10-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.16: UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Wed 06 Oct 2021 20:48:12 AEST # gpg: using RSA key B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Good signature from "Maarten Lankhorst <maarten.lankhorst@linux.intel.com>" [expired] # gpg: aka "Maarten Lankhorst <maarten@debian.org>" [expired] # gpg: aka "Maarten Lankhorst <maarten.lankhorst@canonical.com>" [expired] # gpg: Note: This key has expired! # Primary key fingerprint: B97B D6A8 0CAC 4981 091A E547 FE55 8C72 A670 13C3 From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2602f4e9-a8ac-83f8-6c2a-39fd9ca2e1ba@linux.intel.com
This commit is contained in:
Dave Airlie
commit
797d72ce8e
99 changed files with 3158 additions and 1141 deletions
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@ -1112,7 +1112,8 @@ struct drm_mode_destroy_blob {
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* Lease mode resources, creating another drm_master.
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*
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* The @object_ids array must reference at least one CRTC, one connector and
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* one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled.
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* one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,
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* the lease can be completely empty.
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*/
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struct drm_mode_create_lease {
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/** @object_ids: Pointer to array of object ids (__u32) */
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@ -58,6 +58,67 @@ extern "C" {
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struct drm_v3d_perfmon_get_values)
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#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
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#define DRM_V3D_SUBMIT_EXTENSION 0x02
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/* struct drm_v3d_extension - ioctl extensions
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*
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* Linked-list of generic extensions where the id identify which struct is
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* pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
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* the extension type.
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*/
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struct drm_v3d_extension {
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__u64 next;
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__u32 id;
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#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
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__u32 flags; /* mbz */
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};
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/* struct drm_v3d_sem - wait/signal semaphore
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*
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* If binary semaphore, it only takes syncobj handle and ignores flags and
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* point fields. Point is defined for timeline syncobj feature.
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*/
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struct drm_v3d_sem {
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__u32 handle; /* syncobj */
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/* rsv below, for future uses */
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__u32 flags;
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__u64 point; /* for timeline sem support */
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__u64 mbz[2]; /* must be zero, rsv */
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};
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/* Enum for each of the V3D queues. */
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enum v3d_queue {
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V3D_BIN,
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V3D_RENDER,
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V3D_TFU,
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V3D_CSD,
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V3D_CACHE_CLEAN,
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};
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/**
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* struct drm_v3d_multi_sync - ioctl extension to add support multiples
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* syncobjs for commands submission.
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*
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* When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
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* this extension to define wait and signal dependencies, instead of single
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* in/out sync entries on submitting commands. The field flags is used to
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* determine the stage to set wait dependencies.
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*/
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struct drm_v3d_multi_sync {
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struct drm_v3d_extension base;
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/* Array of wait and signal semaphores */
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__u64 in_syncs;
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__u64 out_syncs;
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/* Number of entries */
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__u32 in_sync_count;
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__u32 out_sync_count;
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/* set the stage (v3d_queue) to sync */
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__u32 wait_stage;
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__u32 pad; /* mbz */
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};
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/**
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* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
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@ -135,12 +196,16 @@ struct drm_v3d_submit_cl {
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/* Number of BO handles passed in (size is that times 4). */
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__u32 bo_handle_count;
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/* DRM_V3D_SUBMIT_* properties */
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__u32 flags;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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__u32 pad;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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};
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/**
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@ -210,6 +275,7 @@ enum drm_v3d_param {
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DRM_V3D_PARAM_SUPPORTS_CSD,
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DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
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DRM_V3D_PARAM_SUPPORTS_PERFMON,
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DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
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};
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struct drm_v3d_get_param {
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@ -248,6 +314,11 @@ struct drm_v3d_submit_tfu {
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__u32 in_sync;
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/* Sync object to signal when the TFU job is done. */
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__u32 out_sync;
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__u32 flags;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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};
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/* Submits a compute shader for dispatch. This job will block on any
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@ -276,6 +347,13 @@ struct drm_v3d_submit_csd {
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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__u32 flags;
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__u32 pad;
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};
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enum {
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@ -47,12 +47,15 @@ extern "C" {
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#define DRM_VIRTGPU_WAIT 0x08
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#define DRM_VIRTGPU_GET_CAPS 0x09
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#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
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#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
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#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
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#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
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#define VIRTGPU_EXECBUF_RING_IDX 0x04
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#define VIRTGPU_EXECBUF_FLAGS (\
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VIRTGPU_EXECBUF_FENCE_FD_IN |\
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VIRTGPU_EXECBUF_FENCE_FD_OUT |\
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VIRTGPU_EXECBUF_RING_IDX |\
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0)
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struct drm_virtgpu_map {
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@ -68,6 +71,8 @@ struct drm_virtgpu_execbuffer {
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__u64 bo_handles;
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__u32 num_bo_handles;
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__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
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__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
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__u32 pad;
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};
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#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
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@ -75,6 +80,8 @@ struct drm_virtgpu_execbuffer {
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#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
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#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
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#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
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#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
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#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
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struct drm_virtgpu_getparam {
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__u64 param;
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@ -173,6 +180,22 @@ struct drm_virtgpu_resource_create_blob {
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__u64 blob_id;
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};
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#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
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#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
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#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
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struct drm_virtgpu_context_set_param {
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__u64 param;
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__u64 value;
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};
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struct drm_virtgpu_context_init {
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__u32 num_params;
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__u32 pad;
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/* pointer to drm_virtgpu_context_set_param array */
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__u64 ctx_set_params;
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};
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#define DRM_IOCTL_VIRTGPU_MAP \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
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@ -212,6 +235,10 @@ struct drm_virtgpu_resource_create_blob {
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
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struct drm_virtgpu_resource_create_blob)
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#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
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struct drm_virtgpu_context_init)
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#if defined(__cplusplus)
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}
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#endif
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@ -59,6 +59,11 @@
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* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
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*/
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#define VIRTIO_GPU_F_RESOURCE_BLOB 3
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/*
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* VIRTIO_GPU_CMD_CREATE_CONTEXT with
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* context_init and multiple timelines
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*/
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#define VIRTIO_GPU_F_CONTEXT_INIT 4
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enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_UNDEFINED = 0,
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@ -122,14 +127,20 @@ enum virtio_gpu_shm_id {
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VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
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};
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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/*
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* If the following flag is set, then ring_idx contains the index
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* of the command ring that needs to used when creating the fence
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*/
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#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
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struct virtio_gpu_ctrl_hdr {
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__le32 type;
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__le32 flags;
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__le64 fence_id;
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__le32 ctx_id;
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__le32 padding;
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__u8 ring_idx;
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__u8 padding[3];
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};
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/* data passed in the cursor vq */
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@ -269,10 +280,11 @@ struct virtio_gpu_resource_create_3d {
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};
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/* VIRTIO_GPU_CMD_CTX_CREATE */
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#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
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struct virtio_gpu_ctx_create {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 nlen;
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__le32 padding;
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__le32 context_init;
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char debug_name[64];
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};
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