KVM/arm64 updates for Linux 5.11
- PSCI relay at EL2 when "protected KVM" is enabled - New exception injection code - Simplification of AArch32 system register handling - Fix PMU accesses when no PMU is enabled - Expose CSV3 on non-Meltdown hosts - Cache hierarchy discovery fixes - PV steal-time cleanups - Allow function pointers at EL2 - Various host EL2 entry cleanups - Simplification of the EL2 vector allocation -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl/XoggPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDsRYP/3ZtGWsyBc1sKdaTBIwQdnrPQHL+7o1Mmjnl b+YqRMWcJW4g3O81GW6IA+vM0A1UMJxVOjzkZd8KulGv3RCZiqQmWJClWFlYbwLj e+HHx+Zo/qsmDrwcVoFI8/n+iC/a5fIaCbSWMSPaKHrOMxBiHQk0qlaq4AZ8gb7a /eHYqI/hISJQb1ZVFHmwlp8FoMnB2M6/FDpCf8oeGKjpF2hjghIPugJ0oRlPLZjB o3Q6ELEScJV1wBy7d1+5rkm52t9j8gpGhXxja0QwypADNzk5KHEzghXq+rTWUh1S et9OfqkflMtKMsh0qNwe5ZFbqtsH69qtYMAj4ok7rZOwQcbJ97VSrP5ka7VVzSdC AgcQU9c9LoyQ7rk0dbs3t0cd8hMgVu50guZ/iHfW88CcdykN9M0nnSPRAYpNbW85 xndBQ5k/a4FoufwoY4e0hS28HIiRfLoEA68mps+yoMiiKh27HO2v4GFRIJoCNxzp YQ01zOBp9FKYTsxj0h7mMf+5EEyo9E4X/kJOfZpOVVbVKy82wPAGLJpDEnbnoJUe j1jBmiV/trkn+nTnWmDoXcw2ljuIF9dBm2M8r8yGKdNEHptnN8tMVRlCRImVVWW0 BbZGAzoK0tpKXPIlUh4aXS3mtV9qlohs9rzjVyKfGnaRRbRGANM8qrH5aKuDFinM RugpMWyk =hf4L -----END PGP SIGNATURE----- Merge tag 'kvmarm-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 updates for Linux 5.11 - PSCI relay at EL2 when "protected KVM" is enabled - New exception injection code - Simplification of AArch32 system register handling - Fix PMU accesses when no PMU is enabled - Expose CSV3 on non-Meltdown hosts - Cache hierarchy discovery fixes - PV steal-time cleanups - Allow function pointers at EL2 - Various host EL2 entry cleanups - Simplification of the EL2 vector allocation
This commit is contained in:
commit
722e039d9a
267 changed files with 4341 additions and 3274 deletions
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@ -60,12 +60,6 @@
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#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
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#endif
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/* The following are for compatibility with GCC, from compiler-gcc.h,
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* and may be redefined here because they should not be shared with other
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* compilers, like ICC.
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*/
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#define barrier() __asm__ __volatile__("" : : : "memory")
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#if __has_feature(shadow_call_stack)
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# define __noscs __attribute__((__no_sanitize__("shadow-call-stack")))
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#endif
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@ -15,25 +15,6 @@
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# error Sorry, your version of GCC is too old - please use 4.9 or newer.
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#endif
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/* Optimization barrier */
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/* The "volatile" is due to gcc bugs */
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#define barrier() __asm__ __volatile__("": : :"memory")
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/*
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* This version is i.e. to prevent dead stores elimination on @ptr
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* where gcc and llvm may behave differently when otherwise using
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* normal barrier(): while gcc behavior gets along with a normal
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* barrier(), llvm needs an explicit input variable to be assumed
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* clobbered. The issue is as follows: while the inline asm might
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* access any memory it wants, the compiler could have fit all of
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* @ptr into memory registers instead, and since @ptr never escaped
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* from that, it proved that the inline asm wasn't touching any of
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* it. This version works well with both compilers, i.e. we're telling
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* the compiler that the inline asm absolutely may see the contents
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* of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
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*/
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#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
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/*
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* This macro obfuscates arithmetic on a variable address so that gcc
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* shouldn't recognize the original var, and make assumptions about it.
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@ -80,11 +80,25 @@ void ftrace_likely_update(struct ftrace_likely_data *f, int val,
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/* Optimization barrier */
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#ifndef barrier
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# define barrier() __memory_barrier()
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/* The "volatile" is due to gcc bugs */
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# define barrier() __asm__ __volatile__("": : :"memory")
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#endif
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#ifndef barrier_data
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# define barrier_data(ptr) barrier()
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/*
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* This version is i.e. to prevent dead stores elimination on @ptr
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* where gcc and llvm may behave differently when otherwise using
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* normal barrier(): while gcc behavior gets along with a normal
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* barrier(), llvm needs an explicit input variable to be assumed
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* clobbered. The issue is as follows: while the inline asm might
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* access any memory it wants, the compiler could have fit all of
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* @ptr into memory registers instead, and since @ptr never escaped
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* from that, it proved that the inline asm wasn't touching any of
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* it. This version works well with both compilers, i.e. we're telling
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* the compiler that the inline asm absolutely may see the contents
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* of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
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*/
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# define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
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#endif
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/* workaround for GCC PR82365 if needed */
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@ -1580,8 +1580,24 @@ extern struct timespec64 current_time(struct inode *inode);
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* Snapshotting support.
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*/
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void __sb_end_write(struct super_block *sb, int level);
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int __sb_start_write(struct super_block *sb, int level, bool wait);
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/*
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* These are internal functions, please use sb_start_{write,pagefault,intwrite}
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* instead.
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*/
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static inline void __sb_end_write(struct super_block *sb, int level)
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{
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percpu_up_read(sb->s_writers.rw_sem + level-1);
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}
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static inline void __sb_start_write(struct super_block *sb, int level)
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{
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percpu_down_read(sb->s_writers.rw_sem + level - 1);
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}
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static inline bool __sb_start_write_trylock(struct super_block *sb, int level)
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{
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return percpu_down_read_trylock(sb->s_writers.rw_sem + level - 1);
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}
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#define __sb_writers_acquired(sb, lev) \
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percpu_rwsem_acquire(&(sb)->s_writers.rw_sem[(lev)-1], 1, _THIS_IP_)
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@ -1645,12 +1661,12 @@ static inline void sb_end_intwrite(struct super_block *sb)
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*/
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static inline void sb_start_write(struct super_block *sb)
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{
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__sb_start_write(sb, SB_FREEZE_WRITE, true);
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__sb_start_write(sb, SB_FREEZE_WRITE);
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}
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static inline int sb_start_write_trylock(struct super_block *sb)
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static inline bool sb_start_write_trylock(struct super_block *sb)
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{
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return __sb_start_write(sb, SB_FREEZE_WRITE, false);
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return __sb_start_write_trylock(sb, SB_FREEZE_WRITE);
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}
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/**
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@ -1674,7 +1690,7 @@ static inline int sb_start_write_trylock(struct super_block *sb)
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*/
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static inline void sb_start_pagefault(struct super_block *sb)
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{
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__sb_start_write(sb, SB_FREEZE_PAGEFAULT, true);
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__sb_start_write(sb, SB_FREEZE_PAGEFAULT);
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}
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/*
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@ -1692,12 +1708,12 @@ static inline void sb_start_pagefault(struct super_block *sb)
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*/
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static inline void sb_start_intwrite(struct super_block *sb)
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{
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__sb_start_write(sb, SB_FREEZE_FS, true);
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__sb_start_write(sb, SB_FREEZE_FS);
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}
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static inline int sb_start_intwrite_trylock(struct super_block *sb)
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static inline bool sb_start_intwrite_trylock(struct super_block *sb)
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{
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return __sb_start_write(sb, SB_FREEZE_FS, false);
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return __sb_start_write_trylock(sb, SB_FREEZE_FS);
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}
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@ -2756,14 +2772,14 @@ static inline void file_start_write(struct file *file)
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{
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if (!S_ISREG(file_inode(file)->i_mode))
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return;
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__sb_start_write(file_inode(file)->i_sb, SB_FREEZE_WRITE, true);
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sb_start_write(file_inode(file)->i_sb);
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}
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static inline bool file_start_write_trylock(struct file *file)
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{
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if (!S_ISREG(file_inode(file)->i_mode))
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return true;
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return __sb_start_write(file_inode(file)->i_sb, SB_FREEZE_WRITE, false);
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return sb_start_write_trylock(file_inode(file)->i_sb);
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}
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static inline void file_end_write(struct file *file)
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@ -315,7 +315,7 @@ static inline int get_disk_ro(struct gendisk *disk)
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extern void disk_block_events(struct gendisk *disk);
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extern void disk_unblock_events(struct gendisk *disk);
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extern void disk_flush_events(struct gendisk *disk, unsigned int mask);
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void set_capacity_revalidate_and_notify(struct gendisk *disk, sector_t size,
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bool set_capacity_revalidate_and_notify(struct gendisk *disk, sector_t size,
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bool update_bdev);
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/* drivers/char/random.c */
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@ -39,6 +39,8 @@ struct its_vpe {
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irq_hw_number_t vpe_db_lpi;
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/* VPE resident */
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bool resident;
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/* VPT parse complete */
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bool ready;
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union {
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/* GICv4.0 implementations */
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struct {
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@ -104,6 +106,7 @@ enum its_vcpu_info_cmd_type {
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PROP_UPDATE_AND_INV_VLPI,
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SCHEDULE_VPE,
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DESCHEDULE_VPE,
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COMMIT_VPE,
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INVALL_VPE,
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PROP_UPDATE_VSGI,
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};
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@ -129,6 +132,7 @@ int its_alloc_vcpu_irqs(struct its_vm *vm);
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void its_free_vcpu_irqs(struct its_vm *vm);
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int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en);
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int its_make_vpe_non_resident(struct its_vpe *vpe, bool db);
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int its_commit_vpe(struct its_vpe *vpe);
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int its_invall_vpe(struct its_vpe *vpe);
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int its_map_vlpi(int irq, struct its_vlpi_map *map);
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int its_get_vlpi(int irq, struct its_vlpi_map *map);
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@ -900,12 +900,19 @@ static inline void count_memcg_event_mm(struct mm_struct *mm,
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static inline void memcg_memory_event(struct mem_cgroup *memcg,
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enum memcg_memory_event event)
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{
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bool swap_event = event == MEMCG_SWAP_HIGH || event == MEMCG_SWAP_MAX ||
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event == MEMCG_SWAP_FAIL;
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atomic_long_inc(&memcg->memory_events_local[event]);
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cgroup_file_notify(&memcg->events_local_file);
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if (!swap_event)
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cgroup_file_notify(&memcg->events_local_file);
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do {
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atomic_long_inc(&memcg->memory_events[event]);
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cgroup_file_notify(&memcg->events_file);
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if (swap_event)
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cgroup_file_notify(&memcg->swap_events_file);
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else
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cgroup_file_notify(&memcg->events_file);
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if (!cgroup_subsys_on_dfl(memory_cgrp_subsys))
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break;
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@ -1022,13 +1022,7 @@ struct perf_sample_data {
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struct perf_callchain_entry *callchain;
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u64 aux_size;
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/*
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* regs_user may point to task_pt_regs or to regs_user_copy, depending
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* on arch details.
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*/
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struct perf_regs regs_user;
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struct pt_regs regs_user_copy;
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struct perf_regs regs_intr;
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u64 stack_user_size;
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@ -1400,11 +1394,14 @@ perf_event_addr_filters(struct perf_event *event)
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extern void perf_event_addr_filters_sync(struct perf_event *event);
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extern int perf_output_begin(struct perf_output_handle *handle,
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struct perf_sample_data *data,
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struct perf_event *event, unsigned int size);
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extern int perf_output_begin_forward(struct perf_output_handle *handle,
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struct perf_event *event,
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unsigned int size);
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struct perf_sample_data *data,
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struct perf_event *event,
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unsigned int size);
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extern int perf_output_begin_backward(struct perf_output_handle *handle,
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struct perf_sample_data *data,
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struct perf_event *event,
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unsigned int size);
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@ -20,8 +20,7 @@ u64 perf_reg_value(struct pt_regs *regs, int idx);
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int perf_reg_validate(u64 mask);
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u64 perf_reg_abi(struct task_struct *task);
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void perf_get_regs_user(struct perf_regs *regs_user,
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struct pt_regs *regs,
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struct pt_regs *regs_user_copy);
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struct pt_regs *regs);
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#else
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#define PERF_REG_EXTENDED_MASK 0
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@ -42,8 +41,7 @@ static inline u64 perf_reg_abi(struct task_struct *task)
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}
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static inline void perf_get_regs_user(struct perf_regs *regs_user,
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struct pt_regs *regs,
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struct pt_regs *regs_user_copy)
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struct pt_regs *regs)
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{
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regs_user->regs = task_pt_regs(current);
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regs_user->abi = perf_reg_abi(current);
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@ -34,6 +34,15 @@ struct psci_operations {
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extern struct psci_operations psci_ops;
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struct psci_0_1_function_ids {
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u32 cpu_suspend;
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u32 cpu_on;
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u32 cpu_off;
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u32 migrate;
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};
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struct psci_0_1_function_ids get_psci_0_1_function_ids(void);
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#if defined(CONFIG_ARM_PSCI_FW)
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int __init psci_dt_init(void);
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#else
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