Mediatek DRM Next for Linux 5.6
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJeHS14AAoJEOHKc6PJWU4k9RkQAJHWLafLl1EEdViWY3YeK/E0 kKUGv+RcuG/HL8NG+rTN7MAT4zbxCF+r0JJIT6+BKlMTUqt4+sxEPhDRPEz1z++4 GOEniw9ogQGicQTvFVlAr4rDnGpvRaAQ8BH3C9/lg67cOe6mrNQOI0AKl99DuXMg dPRbgs1zpajjw/qN60CSMrCtYa+O8IadSx6/TMBhdzk9K4WRPc78UKtiCw5rkLa8 TJAHOEhImWVV1LDoNK9hTmV7huPqQw6L8ZcpJzjgVJRwtrO01LGG5rBOOdnu2Cc4 XiS81whsPXF+GdZPg9frWXJCG41CG03vEykX3y+2rXMdhDsdfBZo2DXKAkpYvGlN WICjf1aq9BlcjFfNUFqeGgh0ZxNLmItyCfptjRMpclmlj25X7isXPz6iKN/nnucr JApacibMeIrchsk//pykhp9LIcn42sMP+ULOSvwFxtOu4o947+xCAlTEbUwN5Mkc Oxeo/TZoBQAmpTHPh7CuuiENqvJuOGpL1Couzqse0NjFWuDuPmDVO6DwKx7X1U98 hNf28sur0XGrQvuGgV0dcytqPxBCTF2/qDXhbC6O4mhzGvWTWbBY1AzLQEekQS4Z oO4s3JTcGkzv24fXfBVD/Rf9fa6VlnfVuH9vCe7LgX1cG72AaMc0sho3m3gTWJCb qeZXngpzlBw8zal3dNN2 =BXQH -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-5.6' of https://github.com/ckhu-mediatek/linux.git-tags into drm-next Mediatek DRM Next for Linux 5.6 This fix non-smooth cursor problem, add cmdq support, add ctm property support and some refinement. Signed-off-by: Dave Airlie <airlied@redhat.com> From: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.freedesktop.org/patch/msgid/1578972526.14594.8.camel@mtksdaap41
This commit is contained in:
commit
6fc376f026
15 changed files with 665 additions and 260 deletions
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@ -20,6 +20,16 @@
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#define CMDQ_WFE_WAIT BIT(15)
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#define CMDQ_WFE_WAIT_VALUE 0x1
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/*
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* WFE arg_b
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* bit 0-11: wait value
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* bit 15: 1 - wait, 0 - no wait
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* bit 16-27: update value
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* bit 31: 1 - update, 0 - no update
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*/
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#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
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CMDQ_WFE_WAIT_VALUE)
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/** cmdq event maximum */
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#define CMDQ_MAX_EVENT 0x3ff
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@ -45,6 +55,7 @@
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enum cmdq_code {
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CMDQ_CODE_MASK = 0x02,
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CMDQ_CODE_WRITE = 0x04,
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CMDQ_CODE_POLL = 0x08,
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CMDQ_CODE_JUMP = 0x10,
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CMDQ_CODE_WFE = 0x20,
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CMDQ_CODE_EOC = 0x40,
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@ -15,6 +15,12 @@
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struct cmdq_pkt;
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struct cmdq_client_reg {
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u8 subsys;
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u16 offset;
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u16 size;
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};
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struct cmdq_client {
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spinlock_t lock;
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u32 pkt_cnt;
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@ -24,6 +30,21 @@ struct cmdq_client {
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u32 timeout_ms; /* in unit of microsecond */
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};
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/**
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* cmdq_dev_get_client_reg() - parse cmdq client reg from the device
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* node of CMDQ client
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* @dev: device of CMDQ mailbox client
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* @client_reg: CMDQ client reg pointer
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* @idx: the index of desired reg
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*
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* Return: 0 for success; else the error code is returned
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*
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* Help CMDQ client parsing the cmdq client reg
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* from the device node of CMDQ client.
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*/
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int cmdq_dev_get_client_reg(struct device *dev,
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struct cmdq_client_reg *client_reg, int idx);
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/**
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* cmdq_mbox_create() - create CMDQ mailbox client and channel
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* @dev: device of CMDQ mailbox client
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@ -99,6 +120,38 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
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*/
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int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
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/**
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* cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
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* execute an instruction that wait for a specified
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* hardware register to check for the value w/o mask.
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* All GCE hardware threads will be blocked by this
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* instruction.
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value);
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/**
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* cmdq_pkt_poll_mask() - Append polling command to the CMDQ packet, ask GCE to
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* execute an instruction that wait for a specified
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* hardware register to check for the value w/ mask.
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* All GCE hardware threads will be blocked by this
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* instruction.
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* @pkt: the CMDQ packet
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* @subsys: the CMDQ sub system code
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* @offset: register offset from CMDQ sub system
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* @value: the specified target register value
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* @mask: the specified target register mask
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*
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* Return: 0 for success; else the error code is returned
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*/
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int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
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u16 offset, u32 value, u32 mask);
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/**
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* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
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* packet and call back at the end of done packet
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