ARM: SoC changes for 5.14
A few SoC (code) changes have queued up this cycle, mostly for minor
changes and some refactoring and cleanup of legacy platforms. This
branch also contains a few of the fixes that weren't sent in by the end
of the release (all fairly minor).
- Adding an additional maintainer for the TEE subsystem (Sumit Garg)
- Quite a significant modernization of the IXP4xx platforms by Linus
Walleij, revisiting with a new PCI host driver/binding, removing legacy
mach/* include dependencies and moving platform detection/config to
drivers/soc. Also some updates/cleanup of platform data.
- Core power domain support for Tegra platforms, and some improvements
in build test coverage by adding stubs for compile test targets.
- A handful of updates to i.MX platforms, adding legacy (non-PSCI) SMP
support on i.MX7D, SoC ID setup for i.MX50, removal of platform data
and board fixups for iMX6/7.
... and a few smaller changes and fixes for Samsung, OMAP, Allwinner,
Rockchip.
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Merge tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Olof Johansson:
"A few SoC (code) changes have queued up this cycle, mostly for minor
changes and some refactoring and cleanup of legacy platforms. This
branch also contains a few of the fixes that weren't sent in by the
end of the release (all fairly minor).
- Adding an additional maintainer for the TEE subsystem (Sumit Garg)
- Quite a significant modernization of the IXP4xx platforms by Linus
Walleij, revisiting with a new PCI host driver/binding, removing
legacy mach/* include dependencies and moving platform
detection/config to drivers/soc. Also some updates/cleanup of
platform data.
- Core power domain support for Tegra platforms, and some
improvements in build test coverage by adding stubs for compile
test targets.
- A handful of updates to i.MX platforms, adding legacy (non-PSCI)
SMP support on i.MX7D, SoC ID setup for i.MX50, removal of platform
data and board fixups for iMX6/7.
... and a few smaller changes and fixes for Samsung, OMAP, Allwinner,
Rockchip"
* tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (53 commits)
MAINTAINERS: Add myself as TEE subsystem reviewer
ixp4xx: fix spelling mistake in Kconfig "Devce" -> "Device"
hw_random: ixp4xx: Add OF support
hw_random: ixp4xx: Add DT bindings
hw_random: ixp4xx: Turn into a module
hw_random: ixp4xx: Use SPDX license tag
hw_random: ixp4xx: enable compile-testing
pata: ixp4xx: split platform data to its own header
soc: ixp4xx: move cpu detection to linux/soc/ixp4xx/cpu.h
PCI: ixp4xx: Add a new driver for IXP4xx
PCI: ixp4xx: Add device tree bindings for IXP4xx
ARM/ixp4xx: Make NEED_MACH_IO_H optional
ARM/ixp4xx: Move the virtual IObases
MAINTAINERS: ARM/MStar/Sigmastar SoCs: Add a link to the MStar tree
ARM: debug: add UART early console support for MSTAR SoCs
ARM: dts: ux500: Fix LED probing
ARM: imx: add smp support for imx7d
ARM: imx6q: drop of_platform_default_populate() from init_machine
arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
soc/tegra: fuse: Fix Tegra234-only builds
...
This commit is contained in:
Linus Torvalds
commit
6e207b8821
76 changed files with 1841 additions and 460 deletions
21
include/linux/platform_data/pata_ixp4xx_cf.h
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21
include/linux/platform_data/pata_ixp4xx_cf.h
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PLATFORM_DATA_PATA_IXP4XX_H
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#define __PLATFORM_DATA_PATA_IXP4XX_H
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#include <linux/types.h>
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/*
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* This structure provide a means for the board setup code
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* to give information to th pata_ixp4xx driver. It is
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* passed as platform_data.
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*/
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struct ixp4xx_pata_data {
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volatile u32 *cs0_cfg;
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volatile u32 *cs1_cfg;
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unsigned long cs0_bits;
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unsigned long cs1_bits;
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void __iomem *cs0;
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void __iomem *cs1;
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};
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#endif
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106
include/linux/soc/ixp4xx/cpu.h
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106
include/linux/soc/ixp4xx/cpu.h
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@ -0,0 +1,106 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* IXP4XX cpu type detection
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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*/
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#ifndef __SOC_IXP4XX_CPU_H__
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#define __SOC_IXP4XX_CPU_H__
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#include <linux/io.h>
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#ifdef CONFIG_ARM
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#include <asm/cputype.h>
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#endif
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/* Processor id value in CP15 Register 0 */
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#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
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#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
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#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
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#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
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#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
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#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
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/* "fuse" bits of IXP_EXP_CFG2 */
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/* All IXP4xx CPUs */
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#define IXP4XX_FEATURE_RCOMP (1 << 0)
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#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
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#define IXP4XX_FEATURE_HASH (1 << 2)
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#define IXP4XX_FEATURE_AES (1 << 3)
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#define IXP4XX_FEATURE_DES (1 << 4)
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#define IXP4XX_FEATURE_HDLC (1 << 5)
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#define IXP4XX_FEATURE_AAL (1 << 6)
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#define IXP4XX_FEATURE_HSS (1 << 7)
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#define IXP4XX_FEATURE_UTOPIA (1 << 8)
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#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
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#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
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#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
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#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
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#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
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#define IXP4XX_FEATURE_PCI (1 << 14)
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#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
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#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
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#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
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IXP4XX_FEATURE_USB_DEVICE | \
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IXP4XX_FEATURE_HASH | \
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IXP4XX_FEATURE_AES | \
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IXP4XX_FEATURE_DES | \
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IXP4XX_FEATURE_HDLC | \
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IXP4XX_FEATURE_AAL | \
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IXP4XX_FEATURE_HSS | \
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IXP4XX_FEATURE_UTOPIA | \
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IXP4XX_FEATURE_NPEB_ETH0 | \
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IXP4XX_FEATURE_NPEC_ETH | \
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IXP4XX_FEATURE_RESET_NPEA | \
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IXP4XX_FEATURE_RESET_NPEB | \
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IXP4XX_FEATURE_RESET_NPEC | \
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IXP4XX_FEATURE_PCI | \
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IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
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IXP4XX_FEATURE_XSCALE_MAX_FREQ)
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/* IXP43x/46x CPUs */
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#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
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#define IXP4XX_FEATURE_USB_HOST (1 << 18)
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#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
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#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
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IXP4XX_FEATURE_ECC_TIMESYNC | \
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IXP4XX_FEATURE_USB_HOST | \
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IXP4XX_FEATURE_NPEA_ETH)
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/* IXP46x CPU (including IXP455) only */
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#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
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#define IXP4XX_FEATURE_RSA (1 << 21)
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#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
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IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
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IXP4XX_FEATURE_RSA)
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#ifdef CONFIG_ARCH_IXP4XX
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#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
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IXP43X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
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IXP46X_PROCESSOR_ID_VALUE)
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u32 ixp4xx_read_feature_bits(void);
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void ixp4xx_write_feature_bits(u32 value);
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#else
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#define cpu_is_ixp42x_rev_a0() 0
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#define cpu_is_ixp42x() 0
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#define cpu_is_ixp43x() 0
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#define cpu_is_ixp46x() 0
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static inline u32 ixp4xx_read_feature_bits(void)
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{
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return 0;
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}
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static inline void ixp4xx_write_feature_bits(u32 value)
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{
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}
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#endif
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#endif /* _ASM_ARCH_CPU_H */
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@ -611,12 +611,6 @@
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#define EXYNOS5420_FSYS2_OPTION 0x4168
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#define EXYNOS5420_PSGEN_OPTION 0x4188
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/* For EXYNOS_CENTRAL_SEQ_OPTION */
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#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16)
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#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17)
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#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24)
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#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25)
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#define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4)
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#define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5)
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#define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6)
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