arm64: dts: msm8998: Add disabled configuration for DPU1/DSI
This SoC supports both the MDP5 and DPU1 drivers, but the latter was chosen as it's more feature-complete; Configure the DPU1, DSI and related phy and pll in order to achieve display functionality and keep it disabled. Enabling it will be done on board specific DT when needed, as not all boards have a usable display attached to them. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
This commit is contained in:
AngeloGioacchino Del Regno
Jami Kettunen
parent
c7f1a3b9f4
commit
68fbfb6ebe
1 changed files with 260 additions and 4 deletions
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@ -2401,16 +2401,272 @@
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"core_bi_pll_test_se";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_MMSS_GPLL0_CLK>,
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<0>,
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<0>,
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<0>,
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<0>,
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<&dsi0_phy 1>,
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<&dsi0_phy 0>,
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<&dsi1_phy 1>,
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<&dsi1_phy 0>,
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<0>,
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<0>,
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<0>,
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<0>;
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};
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dsi_opp_table: dsi-opp-table {
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compatible = "operating-points-v2";
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opp-131250000 {
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opp-hz = /bits/ 64 <131250000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-210000000 {
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opp-hz = /bits/ 64 <210000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp-312500000 {
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opp-hz = /bits/ 64 <312500000>;
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required-opps = <&rpmpd_opp_nom>;
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};
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};
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mdss: mdss@c900000 {
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compatible = "qcom,sdm845-mdss";
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reg = <0x0c900000 0x1000>;
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reg-names = "mdss";
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "core";
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assigned-clocks = <&mmcc MDSS_MDP_CLK>;
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assigned-clock-rates = <300000000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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iommus = <&mmss_smmu 0>;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&mmcc MDSS_GDSC>;
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ranges;
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status = "disabled";
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mdss_mdp: mdp@c901000 {
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compatible = "qcom,msm8998-dpu";
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reg = <0x0c901000 0x8f000>,
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<0x0c9a8e00 0xf0>,
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<0x0c9b0000 0x2008>,
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<0x0c9b8000 0x1040>;
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reg-names = "mdp", "regdma", "vbif",
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"vbif_nrt";
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assigned-clocks = <&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_VSYNC_CLK>;
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assigned-clock-rates = <412500000>,
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<19200000>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MNOC_AHB_CLK>,
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<&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_VSYNC_CLK>;
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clock-names = "iface", "bus", "mnoc",
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"core", "vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd MSM8998_VDDMX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: mdp-opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmpd_opp_min_svs>;
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};
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opp-150000000 {
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opp-hz = /bits/ 64 <150000000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-275000000 {
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opp-hz = /bits/ 64 <275000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp-330000000 {
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opp-hz = /bits/ 64 <330000000>;
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required-opps = <&rpmpd_opp_nom>;
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};
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opp-412500000 {
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opp-hz = /bits/ 64 <412500000>;
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required-opps = <&rpmpd_opp_turbo>;
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};
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};
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};
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dsi0: dsi@c994000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0x0c994000 0x400>;
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reg-names = "dsi_ctrl";
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clocks = <&mmcc MDSS_BYTE0_CLK>,
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<&mmcc MDSS_BYTE0_INTF_CLK>,
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<&mmcc MNOC_AHB_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MISC_AHB_CLK>,
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<&mmcc MDSS_PCLK0_CLK>,
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<&mmcc MDSS_ESC0_CLK>;
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clock-names = "byte",
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"byte_intf",
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"mnoc",
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"iface",
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"bus",
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"core_mmss",
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"pixel",
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"core";
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interrupt-parent = <&mdss>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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operating-points-v2 = <&dsi_opp_table>;
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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power-domains = <&rpmpd MSM8998_VDDCX>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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};
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dsi0_phy: dsi-phy@c994400 {
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compatible = "qcom,dsi-phy-10nm-8998";
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reg = <0x0c994400 0x200>,
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<0x0c994600 0x280>,
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<0x0c994a00 0x1c0>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface", "ref";
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power-domains = <&rpmpd MSM8998_VDDMX>;
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status = "disabled";
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};
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dsi1: dsi@c996000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0x0c996000 0x400>;
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reg-names = "dsi_ctrl";
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clocks = <&mmcc MDSS_BYTE1_CLK>,
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<&mmcc MDSS_BYTE1_INTF_CLK>,
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<&mmcc MNOC_AHB_CLK>,
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<&mmcc MISC_AHB_CLK>,
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<&mmcc MDSS_PCLK1_CLK>,
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<&mmcc MDSS_ESC1_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"mnoc",
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"iface_mmss",
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"pixel",
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"core",
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"iface",
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"bus";
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interrupt-parent = <&mdss>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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operating-points-v2 = <&dsi_opp_table>;
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phys = <&dsi1_phy>;
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phy-names = "dsi";
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power-domains = <&rpmpd MSM8998_VDDCX>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_out: endpoint {
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};
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};
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};
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};
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dsi1_phy: dsi-phy@c996400 {
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compatible = "qcom,dsi-phy-10nm-8998";
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reg = <0x0c996400 0x200>,
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<0x0c996600 0x280>,
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<0x0c996a00 0x10e>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&mmcc MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface", "ref";
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power-domains = <&rpmpd MSM8998_VDDMX>;
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status = "disabled";
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};
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};
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mmss_smmu: iommu@cd00000 {
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compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
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reg = <0x0cd00000 0x40000>;
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