Merge branch 'mfd/wm8994' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc into for-3.3
This commit is contained in:
Mark Brown
commit
68556ca1e0
727 changed files with 9361 additions and 6394 deletions
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@ -243,7 +243,8 @@
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/*Registers VDD1, VDD2 voltage values definitions */
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#define VDD1_2_NUM_VOLTS 73
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#define VDD1_2_NUM_VOLT_FINE 73
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#define VDD1_2_NUM_VOLT_COARSE 3
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#define VDD1_2_MIN_VOLT 6000
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#define VDD1_2_OFFSET 125
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@ -15,6 +15,7 @@
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#ifndef __MFD_WM8994_CORE_H__
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#define __MFD_WM8994_CORE_H__
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#include <linux/mutex.h>
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#include <linux/interrupt.h>
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enum wm8994_type {
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@ -55,6 +56,7 @@ struct wm8994 {
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struct mutex irq_lock;
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enum wm8994_type type;
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int revision;
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struct device *dev;
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struct regmap *regmap;
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@ -65,13 +67,10 @@ struct wm8994 {
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int irq_base;
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int irq;
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u16 irq_masks_cur[WM8994_NUM_IRQ_REGS];
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u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
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struct regmap_irq_chip_data *irq_data;
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/* Used over suspend/resume */
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bool suspended;
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u16 ldo_regs[WM8994_NUM_LDO_REGS];
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u16 gpio_regs[WM8994_NUM_GPIO_REGS];
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struct regulator_dev *dbvdd;
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int num_supplies;
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@ -23,7 +23,7 @@ struct wm8994_ldo_pdata {
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int enable;
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const char *supply;
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struct regulator_init_data *init_data;
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const struct regulator_init_data *init_data;
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};
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#define WM8994_CONFIGURE_GPIO 0x10000
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@ -197,6 +197,12 @@ struct wm8994_pdata {
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* consumption will rise.
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*/
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bool ldo_ena_always_driven;
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/*
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* SPKMODE must be pulled internally by the device on this
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* system.
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*/
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bool spkmode_pu;
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};
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#endif
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@ -95,11 +95,15 @@
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#define WM8994_FLL1_CONTROL_3 0x222
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#define WM8994_FLL1_CONTROL_4 0x223
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#define WM8994_FLL1_CONTROL_5 0x224
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#define WM8958_FLL1_EFS_1 0x226
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#define WM8958_FLL1_EFS_2 0x227
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#define WM8994_FLL2_CONTROL_1 0x240
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#define WM8994_FLL2_CONTROL_2 0x241
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#define WM8994_FLL2_CONTROL_3 0x242
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#define WM8994_FLL2_CONTROL_4 0x243
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#define WM8994_FLL2_CONTROL_5 0x244
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#define WM8958_FLL2_EFS_1 0x246
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#define WM8958_FLL2_EFS_2 0x247
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#define WM8994_AIF1_CONTROL_1 0x300
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#define WM8994_AIF1_CONTROL_2 0x301
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#define WM8994_AIF1_MASTER_SLAVE 0x302
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@ -116,6 +120,7 @@
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#define WM8994_AIF2DAC_LRCLK 0x315
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#define WM8994_AIF2DAC_DATA 0x316
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#define WM8994_AIF2ADC_DATA 0x317
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#define WM1811_AIF2TX_CONTROL 0x318
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#define WM8958_AIF3_CONTROL_1 0x320
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#define WM8958_AIF3_CONTROL_2 0x321
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#define WM8958_AIF3DAC_DATA 0x322
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@ -166,6 +171,7 @@
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#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
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#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
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#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
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#define WM8994_AIF1_DAC1_EQ_BAND_1_C 0x494
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#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
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#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
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#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
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@ -186,6 +192,7 @@
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#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
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#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
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#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
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#define WM8994_AIF1_DAC2_EQ_BAND_1_C 0x4B4
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#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
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#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
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#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
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@ -219,6 +226,7 @@
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#define WM8994_AIF2_EQ_BAND_5_A 0x591
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#define WM8994_AIF2_EQ_BAND_5_B 0x592
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#define WM8994_AIF2_EQ_BAND_5_PG 0x593
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#define WM8994_AIF2_EQ_BAND_1_C 0x594
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#define WM8994_DAC1_MIXER_VOLUMES 0x600
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#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
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#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
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@ -265,7 +273,43 @@
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#define WM8958_DSP2_RELEASETIME 0xA03
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#define WM8958_DSP2_VERMAJMIN 0xA04
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#define WM8958_DSP2_VERBUILD 0xA05
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#define WM8958_DSP2_TESTREG 0xA06
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#define WM8958_DSP2_XORREG 0xA07
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#define WM8958_DSP2_SHIFTMAXX 0xA08
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#define WM8958_DSP2_SHIFTMAXY 0xA09
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#define WM8958_DSP2_SHIFTMAXZ 0xA0A
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#define WM8958_DSP2_SHIFTMAXEXTLO 0xA0B
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#define WM8958_DSP2_AESSELECT 0xA0C
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#define WM8958_DSP2_EXECCONTROL 0xA0D
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#define WM8958_DSP2_SAMPLEBREAK 0xA0E
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#define WM8958_DSP2_COUNTBREAK 0xA0F
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#define WM8958_DSP2_INTSTATUS 0xA10
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#define WM8958_DSP2_EVENTSTATUS 0xA11
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#define WM8958_DSP2_INTMASK 0xA12
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#define WM8958_DSP2_CONFIGDWIDTH 0xA13
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#define WM8958_DSP2_CONFIGINSTR 0xA14
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#define WM8958_DSP2_CONFIGDMEM 0xA15
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#define WM8958_DSP2_CONFIGDELAYS 0xA16
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#define WM8958_DSP2_CONFIGNUMIO 0xA17
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#define WM8958_DSP2_CONFIGEXTDEPTH 0xA18
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#define WM8958_DSP2_CONFIGMULTIPLIER 0xA19
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#define WM8958_DSP2_CONFIGCTRLDWIDTH 0xA1A
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#define WM8958_DSP2_CONFIGPIPELINE 0xA1B
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#define WM8958_DSP2_SHIFTMAXEXTHI 0xA1C
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#define WM8958_DSP2_SWVERSIONREG 0xA1D
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#define WM8958_DSP2_CONFIGXMEM 0xA1E
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#define WM8958_DSP2_CONFIGYMEM 0xA1F
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#define WM8958_DSP2_CONFIGZMEM 0xA20
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#define WM8958_FW_BUILD_1 0x2000
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#define WM8958_FW_BUILD_0 0x2001
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#define WM8958_FW_ID_1 0x2002
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#define WM8958_FW_ID_0 0x2003
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#define WM8958_FW_MAJOR_1 0x2004
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#define WM8958_FW_MAJOR_0 0x2005
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#define WM8958_FW_MINOR_1 0x2006
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#define WM8958_FW_MINOR_0 0x2007
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#define WM8958_FW_PATCH_1 0x2008
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#define WM8958_FW_PATCH_0 0x2009
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
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#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
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@ -334,6 +378,14 @@
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#define WM8958_MBC_B2_PG2_2 0x242D
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#define WM8958_MBC_B1_PG2_1 0x242E
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#define WM8958_MBC_B1_PG2_2 0x242F
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#define WM8958_MBC_CROSSOVER_1 0x2600
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#define WM8958_MBC_CROSSOVER_2 0x2601
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#define WM8958_MBC_HPF_1 0x2602
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#define WM8958_MBC_HPF_2 0x2603
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#define WM8958_MBC_LPF_1 0x2606
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#define WM8958_MBC_LPF_2 0x2607
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#define WM8958_MBC_RMS_LIMIT_1 0x260A
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#define WM8958_MBC_RMS_LIMIT_2 0x260B
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#define WM8994_WRITE_SEQUENCER_0 0x3000
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#define WM8994_WRITE_SEQUENCER_1 0x3001
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#define WM8994_WRITE_SEQUENCER_2 0x3002
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@ -2393,6 +2445,10 @@
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/*
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* R548 (0x224) - FLL1 Control (5)
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*/
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#define WM8958_FLL1_BYP 0x8000 /* FLL1_BYP */
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#define WM8958_FLL1_BYP_MASK 0x8000 /* FLL1_BYP */
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#define WM8958_FLL1_BYP_SHIFT 15 /* FLL1_BYP */
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#define WM8958_FLL1_BYP_WIDTH 1 /* FLL1_BYP */
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#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
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#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
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#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
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@ -2407,6 +2463,24 @@
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#define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
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#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
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/*
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* R550 (0x226) - FLL1 EFS 1
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*/
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#define WM8958_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
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#define WM8958_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
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#define WM8958_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
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/*
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* R551 (0x227) - FLL1 EFS 2
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*/
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#define WM8958_FLL1_LFSR_SEL_MASK 0x0006 /* FLL1_LFSR_SEL - [2:1] */
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#define WM8958_FLL1_LFSR_SEL_SHIFT 1 /* FLL1_LFSR_SEL - [2:1] */
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#define WM8958_FLL1_LFSR_SEL_WIDTH 2 /* FLL1_LFSR_SEL - [2:1] */
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#define WM8958_FLL1_EFS_ENA 0x0001 /* FLL1_EFS_ENA */
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#define WM8958_FLL1_EFS_ENA_MASK 0x0001 /* FLL1_EFS_ENA */
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#define WM8958_FLL1_EFS_ENA_SHIFT 0 /* FLL1_EFS_ENA */
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#define WM8958_FLL1_EFS_ENA_WIDTH 1 /* FLL1_EFS_ENA */
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/*
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* R576 (0x240) - FLL2 Control (1)
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*/
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@ -2456,6 +2530,10 @@
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/*
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* R580 (0x244) - FLL2 Control (5)
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*/
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#define WM8958_FLL2_BYP 0x8000 /* FLL2_BYP */
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#define WM8958_FLL2_BYP_MASK 0x8000 /* FLL2_BYP */
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#define WM8958_FLL2_BYP_SHIFT 15 /* FLL2_BYP */
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#define WM8958_FLL2_BYP_WIDTH 1 /* FLL2_BYP */
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#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
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#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
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#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
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@ -2470,6 +2548,24 @@
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#define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
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#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
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/*
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* R582 (0x246) - FLL2 EFS 1
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*/
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#define WM8958_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
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#define WM8958_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
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#define WM8958_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
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/*
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* R583 (0x247) - FLL2 EFS 2
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*/
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#define WM8958_FLL2_LFSR_SEL_MASK 0x0006 /* FLL2_LFSR_SEL - [2:1] */
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#define WM8958_FLL2_LFSR_SEL_SHIFT 1 /* FLL2_LFSR_SEL - [2:1] */
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#define WM8958_FLL2_LFSR_SEL_WIDTH 2 /* FLL2_LFSR_SEL - [2:1] */
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#define WM8958_FLL2_EFS_ENA 0x0001 /* FLL2_EFS_ENA */
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#define WM8958_FLL2_EFS_ENA_MASK 0x0001 /* FLL2_EFS_ENA */
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#define WM8958_FLL2_EFS_ENA_SHIFT 0 /* FLL2_EFS_ENA */
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#define WM8958_FLL2_EFS_ENA_WIDTH 1 /* FLL2_EFS_ENA */
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/*
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* R768 (0x300) - AIF1 Control (1)
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*/
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