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arm64: tlb: don't set the ttl value in flush_tlb_page_nosync

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flush_tlb_page_nosync() may be called from pmd level, so we
can not set the ttl = 3 here.

The callstack is as follows:

	pmdp_set_access_flags
		ptep_set_access_flags
			flush_tlb_fix_spurious_fault
				flush_tlb_page
					flush_tlb_page_nosync

Fixes: e735b98a5f ("arm64: Add tlbi_user_level TLB invalidation helper")
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200710094158.468-1-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Zhenyu Ye 2020-07-10 17:41:58 +08:00 • committed by Catalin Marinas
parent 34e36d81a0
commit 61c11656b6
1 changed files with 2 additions and 3 deletions
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5
arch/arm64/include/asm/tlbflush.h
View file

@ -209,9 +209,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
dsb(ishst);
/* This function is only called on a small page */
__tlbi_level(vale1is, addr, 3);
__tlbi_user_level(vale1is, addr, 3);
__tlbi(vale1is, addr);
__tlbi_user(vale1is, addr);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,