Misc driver patches for 5.15-rc1, second round
Here is a second round of misc driver patches for 5.15-rc1. In here is only updates for the Habanalabs driver. This request is late because the previously-objected-to dma-buf patches are all removed and some fixes that you and others found are now included in here as well. All of these have been in linux-next for well over a week with no reports of problems, and they are all self-contained to only this one driver. Full details are in the shortlog. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCYTtnnQ8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+yldxgCfeXoRaaCBSzpbejgf48CQRd/m/v0AmgMRVUxB kJ58eqBrDMdeExOkvkh8 =6d/9 -----END PGP SIGNATURE----- Merge tag 'char-misc-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull habanalabs updates from Greg KH: "Here is another round of misc driver patches for 5.15-rc1. In here is only updates for the Habanalabs driver. This request is late because the previously-objected-to dma-buf patches are all removed and some fixes that you and others found are now included in here as well. All of these have been in linux-next for well over a week with no reports of problems, and they are all self-contained to only this one driver. Full details are in the shortlog" * tag 'char-misc-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (61 commits) habanalabs/gaudi: hwmon default card name habanalabs: add support for f/w reset habanalabs/gaudi: block ICACHE_BASE_ADDERESS_HIGH in TPC habanalabs: cannot sleep while holding spinlock habanalabs: never copy_from_user inside spinlock habanalabs: remove unnecessary device status check habanalabs: disable IRQ in user interrupts spinlock habanalabs: add "in device creation" status habanalabs/gaudi: invalidate PMMU mem cache on init habanalabs/gaudi: size should be printed in decimal habanalabs/gaudi: define DC POWER for secured PMC habanalabs/gaudi: unmask out of bounds SLM access interrupt habanalabs: add userptr_lookup node in debugfs habanalabs/gaudi: fetch TPC/MME ECC errors from F/W habanalabs: modify multi-CS to wait on stream masters habanalabs/gaudi: add monitored SOBs to state dump habanalabs/gaudi: restore user registers when context opens habanalabs/gaudi: increase boot fit timeout habanalabs: update to latest firmware headers habanalabs/gaudi: minimize number of register reads ...
This commit is contained in:
Linus Torvalds
commit
5ffc06ebea
28 changed files with 3880 additions and 796 deletions
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@ -276,7 +276,17 @@ enum hl_device_status {
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HL_DEVICE_STATUS_OPERATIONAL,
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HL_DEVICE_STATUS_IN_RESET,
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HL_DEVICE_STATUS_MALFUNCTION,
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HL_DEVICE_STATUS_NEEDS_RESET
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HL_DEVICE_STATUS_NEEDS_RESET,
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HL_DEVICE_STATUS_IN_DEVICE_CREATION,
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HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION
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};
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enum hl_server_type {
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HL_SERVER_TYPE_UNKNOWN = 0,
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HL_SERVER_GAUDI_HLS1 = 1,
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HL_SERVER_GAUDI_HLS1H = 2,
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HL_SERVER_GAUDI_TYPE1 = 3,
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HL_SERVER_GAUDI_TYPE2 = 4
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};
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/* Opcode for management ioctl
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@ -337,17 +347,49 @@ enum hl_device_status {
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#define HL_INFO_VERSION_MAX_LEN 128
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#define HL_INFO_CARD_NAME_MAX_LEN 16
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/**
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* struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC
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* @sram_base_address: The first SRAM physical base address that is free to be
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* used by the user.
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* @dram_base_address: The first DRAM virtual or physical base address that is
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* free to be used by the user.
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* @dram_size: The DRAM size that is available to the user.
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* @sram_size: The SRAM size that is available to the user.
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* @num_of_events: The number of events that can be received from the f/w. This
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* is needed so the user can what is the size of the h/w events
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* array he needs to pass to the kernel when he wants to fetch
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* the event counters.
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* @device_id: PCI device ID of the ASIC.
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* @module_id: Module ID of the ASIC for mezzanine cards in servers
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* (From OCP spec).
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* @first_available_interrupt_id: The first available interrupt ID for the user
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* to be used when it works with user interrupts.
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* @server_type: Server type that the Gaudi ASIC is currently installed in.
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* The value is according to enum hl_server_type
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* @cpld_version: CPLD version on the board.
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* @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs.
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* @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs.
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* @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs.
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* @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler
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* in some ASICs.
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* @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant
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* for Goya/Gaudi only.
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* @dram_enabled: Whether the DRAM is enabled.
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* @cpucp_version: The CPUCP f/w version.
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* @card_name: The card name as passed by the f/w.
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* @dram_page_size: The DRAM physical page size.
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*/
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struct hl_info_hw_ip_info {
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__u64 sram_base_address;
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__u64 dram_base_address;
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__u64 dram_size;
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__u32 sram_size;
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__u32 num_of_events;
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__u32 device_id; /* PCI Device ID */
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__u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */
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__u32 device_id;
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__u32 module_id;
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__u32 reserved;
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__u16 first_available_interrupt_id;
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__u16 reserved2;
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__u16 server_type;
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__u32 cpld_version;
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__u32 psoc_pci_pll_nr;
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__u32 psoc_pci_pll_nf;
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@ -358,7 +400,7 @@ struct hl_info_hw_ip_info {
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__u8 pad[2];
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__u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
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__u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
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__u64 reserved3;
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__u64 reserved2;
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__u64 dram_page_size;
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};
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@ -628,12 +670,21 @@ struct hl_cs_chunk {
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__u64 cb_handle;
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/* Relevant only when HL_CS_FLAGS_WAIT or
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* HL_CS_FLAGS_COLLECTIVE_WAIT is set.
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* HL_CS_FLAGS_COLLECTIVE_WAIT is set
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* This holds address of array of u64 values that contain
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* signal CS sequence numbers. The wait described by this job
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* will listen on all those signals (wait event per signal)
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* signal CS sequence numbers. The wait described by
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* this job will listen on all those signals
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* (wait event per signal)
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*/
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__u64 signal_seq_arr;
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/*
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* Relevant only when HL_CS_FLAGS_WAIT or
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* HL_CS_FLAGS_COLLECTIVE_WAIT is set
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* along with HL_CS_FLAGS_ENCAP_SIGNALS.
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* This is the CS sequence which has the encapsulated signals.
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*/
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__u64 encaps_signal_seq;
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};
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/* Index of queue to put the CB on */
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@ -651,6 +702,17 @@ struct hl_cs_chunk {
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* Number of entries in signal_seq_arr
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*/
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__u32 num_signal_seq_arr;
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/* Relevant only when HL_CS_FLAGS_WAIT or
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* HL_CS_FLAGS_COLLECTIVE_WAIT is set along
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* with HL_CS_FLAGS_ENCAP_SIGNALS
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* This set the signals range that the user want to wait for
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* out of the whole reserved signals range.
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* e.g if the signals range is 20, and user don't want
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* to wait for signal 8, so he set this offset to 7, then
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* he call the API again with 9 and so on till 20.
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*/
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__u32 encaps_signal_offset;
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};
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/* HL_CS_CHUNK_FLAGS_* */
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@ -678,6 +740,28 @@ struct hl_cs_chunk {
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#define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
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#define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
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/*
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* The encapsulated signals CS is merged into the existing CS ioctls.
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* In order to use this feature need to follow the below procedure:
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* 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY
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* the output of this API will be the SOB offset from CFG_BASE.
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* this address will be used to patch CB cmds to do the signaling for this
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* SOB by incrementing it's value.
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* for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY
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* CS type, note that this might fail if out-of-sync happened to the SOB
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* value, in case other signaling request to the same SOB occurred between
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* reserve-unreserve calls.
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* 2. Use the staged CS to do the encapsulated signaling jobs.
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* use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
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* along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset
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* field. This offset allows app to wait on part of the reserved signals.
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* 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag
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* to wait for the encapsulated signals.
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*/
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#define HL_CS_FLAGS_ENCAP_SIGNALS 0x800
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#define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000
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#define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
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#define HL_CS_STATUS_SUCCESS 0
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#define HL_MAX_JOBS_PER_CS 512
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@ -690,10 +774,35 @@ struct hl_cs_in {
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/* holds address of array of hl_cs_chunk for execution phase */
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__u64 chunks_execute;
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/* Sequence number of a staged submission CS
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* valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set
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*/
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__u64 seq;
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union {
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/*
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* Sequence number of a staged submission CS
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* valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and
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* HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset.
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*/
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__u64 seq;
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/*
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* Encapsulated signals handle id
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* Valid for two flows:
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* 1. CS with encapsulated signals:
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* when HL_CS_FLAGS_STAGED_SUBMISSION and
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* HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
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* and HL_CS_FLAGS_ENCAP_SIGNALS are set.
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* 2. unreserve signals:
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* valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set.
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*/
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__u32 encaps_sig_handle_id;
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/* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
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struct {
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/* Encapsulated signals number */
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__u32 encaps_signals_count;
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/* Encapsulated signals queue index (stream) */
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__u32 encaps_signals_q_idx;
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};
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};
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/* Number of chunks in restore phase array. Maximum number is
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* HL_MAX_JOBS_PER_CS
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@ -718,14 +827,31 @@ struct hl_cs_in {
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};
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struct hl_cs_out {
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/*
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* seq holds the sequence number of the CS to pass to wait ioctl. All
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* values are valid except for 0 and ULLONG_MAX
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*/
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__u64 seq;
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/* HL_CS_STATUS_* */
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union {
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/*
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* seq holds the sequence number of the CS to pass to wait
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* ioctl. All values are valid except for 0 and ULLONG_MAX
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*/
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__u64 seq;
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/* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
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struct {
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/* This is the resereved signal handle id */
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__u32 handle_id;
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/* This is the signals count */
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__u32 count;
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};
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};
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/* HL_CS_STATUS */
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__u32 status;
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__u32 pad;
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/*
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* SOB base address offset
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* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set
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*/
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__u32 sob_base_addr_offset;
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};
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union hl_cs_args {
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@ -735,11 +861,18 @@ union hl_cs_args {
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#define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
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#define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
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#define HL_WAIT_CS_FLAGS_MULTI_CS 0x4
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#define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32
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struct hl_wait_cs_in {
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union {
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struct {
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/* Command submission sequence number */
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/*
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* In case of wait_cs holds the CS sequence number.
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* In case of wait for multi CS hold a user pointer to
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* an array of CS sequence numbers
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*/
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__u64 seq;
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/* Absolute timeout to wait for command submission
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* in microseconds
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@ -767,12 +900,17 @@ struct hl_wait_cs_in {
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/* Context ID - Currently not in use */
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__u32 ctx_id;
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/* HL_WAIT_CS_FLAGS_*
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* If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include
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* interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order
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* not to specify an interrupt id ,set mask to all 1s.
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*/
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__u32 flags;
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/* Multi CS API info- valid entries in multi-CS array */
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__u8 seq_arr_len;
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__u8 pad[7];
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};
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#define HL_WAIT_CS_STATUS_COMPLETED 0
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@ -789,8 +927,15 @@ struct hl_wait_cs_out {
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__u32 status;
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/* HL_WAIT_CS_STATUS_FLAG* */
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__u32 flags;
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/* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set */
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/*
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* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set
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* for wait_cs: timestamp of CS completion
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* for wait_multi_cs: timestamp of FIRST CS completion
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*/
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__s64 timestamp_nsec;
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/* multi CS completion bitmap */
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__u32 cs_completion_map;
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__u32 pad;
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};
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union hl_wait_cs_args {
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@ -813,6 +958,7 @@ union hl_wait_cs_args {
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#define HL_MEM_CONTIGUOUS 0x1
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#define HL_MEM_SHARED 0x2
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#define HL_MEM_USERPTR 0x4
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#define HL_MEM_FORCE_HINT 0x8
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struct hl_mem_in {
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union {
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