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ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface

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The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Marc Zyngier 2017-07-01 15:16:35 +01:00 • committed by Gregory CLEMENT
parent 95696d292e
commit 5f926e889f
1 changed files with 4 additions and 1 deletions
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5
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@ -322,7 +322,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
<0x1d40000 0x40000>; /* GICR */
<0x1d40000 0x40000>, /* GICR */
<0x1d80000 0x2000>, /* GICC */
<0x1d90000 0x2000>, /* GICH */
<0x1da0000 0x20000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};